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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
cff37c9e | 2 | /* Texas Instruments TMP102 SMBus temperature sensor driver |
beb1b6bb | 3 | * |
cff37c9e | 4 | * Copyright (C) 2010 Steven King <sfking@fdwdc.com> |
beb1b6bb SK |
5 | */ |
6 | ||
3d8f7a89 | 7 | #include <linux/delay.h> |
beb1b6bb SK |
8 | #include <linux/module.h> |
9 | #include <linux/init.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/i2c.h> | |
12 | #include <linux/hwmon.h> | |
13 | #include <linux/hwmon-sysfs.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/mutex.h> | |
cff37c9e | 16 | #include <linux/device.h> |
dcd8f392 | 17 | #include <linux/jiffies.h> |
28a340db | 18 | #include <linux/regmap.h> |
6a027523 | 19 | #include <linux/of.h> |
beb1b6bb SK |
20 | |
21 | #define DRIVER_NAME "tmp102" | |
22 | ||
23 | #define TMP102_TEMP_REG 0x00 | |
24 | #define TMP102_CONF_REG 0x01 | |
25 | /* note: these bit definitions are byte swapped */ | |
26 | #define TMP102_CONF_SD 0x0100 | |
27 | #define TMP102_CONF_TM 0x0200 | |
28 | #define TMP102_CONF_POL 0x0400 | |
29 | #define TMP102_CONF_F0 0x0800 | |
30 | #define TMP102_CONF_F1 0x1000 | |
31 | #define TMP102_CONF_R0 0x2000 | |
32 | #define TMP102_CONF_R1 0x4000 | |
33 | #define TMP102_CONF_OS 0x8000 | |
34 | #define TMP102_CONF_EM 0x0010 | |
35 | #define TMP102_CONF_AL 0x0020 | |
36 | #define TMP102_CONF_CR0 0x0040 | |
37 | #define TMP102_CONF_CR1 0x0080 | |
38 | #define TMP102_TLOW_REG 0x02 | |
39 | #define TMP102_THIGH_REG 0x03 | |
40 | ||
a9f92ccf GR |
41 | #define TMP102_CONFREG_MASK (TMP102_CONF_SD | TMP102_CONF_TM | \ |
42 | TMP102_CONF_POL | TMP102_CONF_F0 | \ | |
43 | TMP102_CONF_F1 | TMP102_CONF_OS | \ | |
44 | TMP102_CONF_EM | TMP102_CONF_AL | \ | |
45 | TMP102_CONF_CR0 | TMP102_CONF_CR1) | |
46 | ||
47 | #define TMP102_CONFIG_CLEAR (TMP102_CONF_SD | TMP102_CONF_OS | \ | |
48 | TMP102_CONF_CR0) | |
49 | #define TMP102_CONFIG_SET (TMP102_CONF_TM | TMP102_CONF_EM | \ | |
50 | TMP102_CONF_CR1) | |
51 | ||
3d8f7a89 GR |
52 | #define CONVERSION_TIME_MS 35 /* in milli-seconds */ |
53 | ||
beb1b6bb | 54 | struct tmp102 { |
28a340db | 55 | struct regmap *regmap; |
38806bda | 56 | u16 config_orig; |
3d8f7a89 | 57 | unsigned long ready_time; |
beb1b6bb SK |
58 | }; |
59 | ||
cff37c9e JD |
60 | /* convert left adjusted 13-bit TMP102 register value to milliCelsius */ |
61 | static inline int tmp102_reg_to_mC(s16 val) | |
beb1b6bb | 62 | { |
cff37c9e | 63 | return ((val & ~0x01) * 1000) / 128; |
beb1b6bb SK |
64 | } |
65 | ||
cff37c9e JD |
66 | /* convert milliCelsius to left adjusted 13-bit TMP102 register value */ |
67 | static inline u16 tmp102_mC_to_reg(int val) | |
beb1b6bb SK |
68 | { |
69 | return (val * 128) / 1000; | |
70 | } | |
71 | ||
0208531d GR |
72 | static int tmp102_read(struct device *dev, enum hwmon_sensor_types type, |
73 | u32 attr, int channel, long *temp) | |
6a027523 | 74 | { |
3d8f7a89 | 75 | struct tmp102 *tmp102 = dev_get_drvdata(dev); |
0208531d GR |
76 | unsigned int regval; |
77 | int err, reg; | |
78 | ||
79 | switch (attr) { | |
80 | case hwmon_temp_input: | |
81 | /* Is it too early to return a conversion ? */ | |
82 | if (time_before(jiffies, tmp102->ready_time)) { | |
83 | dev_dbg(dev, "%s: Conversion not ready yet..\n", __func__); | |
84 | return -EAGAIN; | |
85 | } | |
86 | reg = TMP102_TEMP_REG; | |
87 | break; | |
88 | case hwmon_temp_max_hyst: | |
89 | reg = TMP102_TLOW_REG; | |
90 | break; | |
91 | case hwmon_temp_max: | |
92 | reg = TMP102_THIGH_REG; | |
93 | break; | |
94 | default: | |
95 | return -EOPNOTSUPP; | |
00917b5c NM |
96 | } |
97 | ||
0208531d GR |
98 | err = regmap_read(tmp102->regmap, reg, ®val); |
99 | if (err < 0) | |
100 | return err; | |
101 | *temp = tmp102_reg_to_mC(regval); | |
6a027523 EV |
102 | |
103 | return 0; | |
104 | } | |
105 | ||
0208531d GR |
106 | static int tmp102_write(struct device *dev, enum hwmon_sensor_types type, |
107 | u32 attr, int channel, long temp) | |
beb1b6bb | 108 | { |
3d8f7a89 | 109 | struct tmp102 *tmp102 = dev_get_drvdata(dev); |
0208531d GR |
110 | int reg; |
111 | ||
112 | switch (attr) { | |
113 | case hwmon_temp_max_hyst: | |
114 | reg = TMP102_TLOW_REG; | |
115 | break; | |
116 | case hwmon_temp_max: | |
117 | reg = TMP102_THIGH_REG; | |
118 | break; | |
119 | default: | |
120 | return -EOPNOTSUPP; | |
121 | } | |
3d8f7a89 | 122 | |
0208531d GR |
123 | temp = clamp_val(temp, -256000, 255000); |
124 | return regmap_write(tmp102->regmap, reg, tmp102_mC_to_reg(temp)); | |
beb1b6bb SK |
125 | } |
126 | ||
0208531d GR |
127 | static umode_t tmp102_is_visible(const void *data, enum hwmon_sensor_types type, |
128 | u32 attr, int channel) | |
beb1b6bb | 129 | { |
0208531d GR |
130 | if (type != hwmon_temp) |
131 | return 0; | |
132 | ||
133 | switch (attr) { | |
134 | case hwmon_temp_input: | |
51148a23 | 135 | return 0444; |
0208531d GR |
136 | case hwmon_temp_max_hyst: |
137 | case hwmon_temp_max: | |
51148a23 | 138 | return 0644; |
0208531d GR |
139 | default: |
140 | return 0; | |
141 | } | |
beb1b6bb SK |
142 | } |
143 | ||
0208531d | 144 | static const struct hwmon_channel_info *tmp102_info[] = { |
88078254 GR |
145 | HWMON_CHANNEL_INFO(chip, |
146 | HWMON_C_REGISTER_TZ), | |
147 | HWMON_CHANNEL_INFO(temp, | |
148 | HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST), | |
beb1b6bb SK |
149 | NULL |
150 | }; | |
beb1b6bb | 151 | |
0208531d GR |
152 | static const struct hwmon_ops tmp102_hwmon_ops = { |
153 | .is_visible = tmp102_is_visible, | |
154 | .read = tmp102_read, | |
155 | .write = tmp102_write, | |
156 | }; | |
157 | ||
158 | static const struct hwmon_chip_info tmp102_chip_info = { | |
159 | .ops = &tmp102_hwmon_ops, | |
160 | .info = tmp102_info, | |
2251aef6 EV |
161 | }; |
162 | ||
b17ea1ca GR |
163 | static void tmp102_restore_config(void *data) |
164 | { | |
165 | struct tmp102 *tmp102 = data; | |
b17ea1ca | 166 | |
28a340db GR |
167 | regmap_write(tmp102->regmap, TMP102_CONF_REG, tmp102->config_orig); |
168 | } | |
169 | ||
170 | static bool tmp102_is_writeable_reg(struct device *dev, unsigned int reg) | |
171 | { | |
172 | return reg != TMP102_TEMP_REG; | |
b17ea1ca GR |
173 | } |
174 | ||
28a340db GR |
175 | static bool tmp102_is_volatile_reg(struct device *dev, unsigned int reg) |
176 | { | |
177 | return reg == TMP102_TEMP_REG; | |
178 | } | |
179 | ||
180 | static const struct regmap_config tmp102_regmap_config = { | |
181 | .reg_bits = 8, | |
182 | .val_bits = 16, | |
183 | .max_register = TMP102_THIGH_REG, | |
184 | .writeable_reg = tmp102_is_writeable_reg, | |
185 | .volatile_reg = tmp102_is_volatile_reg, | |
186 | .val_format_endian = REGMAP_ENDIAN_BIG, | |
187 | .cache_type = REGCACHE_RBTREE, | |
1c96a2f6 DF |
188 | .use_single_read = true, |
189 | .use_single_write = true, | |
28a340db GR |
190 | }; |
191 | ||
6c931ae1 | 192 | static int tmp102_probe(struct i2c_client *client, |
0208531d | 193 | const struct i2c_device_id *id) |
beb1b6bb | 194 | { |
fbd9af16 | 195 | struct device *dev = &client->dev; |
ad9beea4 | 196 | struct device *hwmon_dev; |
beb1b6bb | 197 | struct tmp102 *tmp102; |
28a340db GR |
198 | unsigned int regval; |
199 | int err; | |
beb1b6bb | 200 | |
cff37c9e | 201 | if (!i2c_check_functionality(client->adapter, |
beb1b6bb | 202 | I2C_FUNC_SMBUS_WORD_DATA)) { |
fbd9af16 | 203 | dev_err(dev, |
b55f3757 | 204 | "adapter doesn't support SMBus word transactions\n"); |
beb1b6bb SK |
205 | return -ENODEV; |
206 | } | |
207 | ||
fbd9af16 | 208 | tmp102 = devm_kzalloc(dev, sizeof(*tmp102), GFP_KERNEL); |
f511a21f | 209 | if (!tmp102) |
beb1b6bb | 210 | return -ENOMEM; |
f511a21f | 211 | |
beb1b6bb SK |
212 | i2c_set_clientdata(client, tmp102); |
213 | ||
28a340db GR |
214 | tmp102->regmap = devm_regmap_init_i2c(client, &tmp102_regmap_config); |
215 | if (IS_ERR(tmp102->regmap)) | |
216 | return PTR_ERR(tmp102->regmap); | |
217 | ||
218 | err = regmap_read(tmp102->regmap, TMP102_CONF_REG, ®val); | |
219 | if (err < 0) { | |
fbd9af16 | 220 | dev_err(dev, "error reading config register\n"); |
28a340db | 221 | return err; |
38806bda | 222 | } |
a9f92ccf | 223 | |
28a340db | 224 | if ((regval & ~TMP102_CONFREG_MASK) != |
a9f92ccf GR |
225 | (TMP102_CONF_R0 | TMP102_CONF_R1)) { |
226 | dev_err(dev, "unexpected config register value\n"); | |
227 | return -ENODEV; | |
228 | } | |
229 | ||
28a340db | 230 | tmp102->config_orig = regval; |
b17ea1ca | 231 | |
1aa4f028 GR |
232 | err = devm_add_action_or_reset(dev, tmp102_restore_config, tmp102); |
233 | if (err) | |
234 | return err; | |
b17ea1ca | 235 | |
28a340db GR |
236 | regval &= ~TMP102_CONFIG_CLEAR; |
237 | regval |= TMP102_CONFIG_SET; | |
a9f92ccf | 238 | |
28a340db GR |
239 | err = regmap_write(tmp102->regmap, TMP102_CONF_REG, regval); |
240 | if (err < 0) { | |
fbd9af16 | 241 | dev_err(dev, "error writing config register\n"); |
28a340db | 242 | return err; |
cff37c9e | 243 | } |
3d8f7a89 | 244 | |
d0725439 GR |
245 | /* |
246 | * Mark that we are not ready with data until the first | |
247 | * conversion is complete | |
248 | */ | |
249 | tmp102->ready_time = jiffies + msecs_to_jiffies(CONVERSION_TIME_MS); | |
3d8f7a89 | 250 | |
0208531d GR |
251 | hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, |
252 | tmp102, | |
253 | &tmp102_chip_info, | |
254 | NULL); | |
ad9beea4 | 255 | if (IS_ERR(hwmon_dev)) { |
fbd9af16 | 256 | dev_dbg(dev, "unable to register hwmon device\n"); |
b17ea1ca | 257 | return PTR_ERR(hwmon_dev); |
beb1b6bb | 258 | } |
fbd9af16 | 259 | dev_info(dev, "initialized\n"); |
beb1b6bb | 260 | |
beb1b6bb SK |
261 | return 0; |
262 | } | |
263 | ||
dd378b1b | 264 | #ifdef CONFIG_PM_SLEEP |
beb1b6bb SK |
265 | static int tmp102_suspend(struct device *dev) |
266 | { | |
267 | struct i2c_client *client = to_i2c_client(dev); | |
28a340db | 268 | struct tmp102 *tmp102 = i2c_get_clientdata(client); |
beb1b6bb | 269 | |
28a340db GR |
270 | return regmap_update_bits(tmp102->regmap, TMP102_CONF_REG, |
271 | TMP102_CONF_SD, TMP102_CONF_SD); | |
beb1b6bb SK |
272 | } |
273 | ||
274 | static int tmp102_resume(struct device *dev) | |
275 | { | |
276 | struct i2c_client *client = to_i2c_client(dev); | |
3d8f7a89 | 277 | struct tmp102 *tmp102 = i2c_get_clientdata(client); |
28a340db | 278 | int err; |
beb1b6bb | 279 | |
28a340db GR |
280 | err = regmap_update_bits(tmp102->regmap, TMP102_CONF_REG, |
281 | TMP102_CONF_SD, 0); | |
beb1b6bb | 282 | |
3d8f7a89 GR |
283 | tmp102->ready_time = jiffies + msecs_to_jiffies(CONVERSION_TIME_MS); |
284 | ||
28a340db | 285 | return err; |
beb1b6bb | 286 | } |
beb1b6bb SK |
287 | #endif /* CONFIG_PM */ |
288 | ||
dd378b1b GS |
289 | static SIMPLE_DEV_PM_OPS(tmp102_dev_pm_ops, tmp102_suspend, tmp102_resume); |
290 | ||
beb1b6bb | 291 | static const struct i2c_device_id tmp102_id[] = { |
cff37c9e | 292 | { "tmp102", 0 }, |
beb1b6bb SK |
293 | { } |
294 | }; | |
cff37c9e | 295 | MODULE_DEVICE_TABLE(i2c, tmp102_id); |
beb1b6bb | 296 | |
07af9a4a | 297 | static const struct of_device_id __maybe_unused tmp102_of_match[] = { |
15390c61 JMC |
298 | { .compatible = "ti,tmp102" }, |
299 | { }, | |
300 | }; | |
301 | MODULE_DEVICE_TABLE(of, tmp102_of_match); | |
302 | ||
beb1b6bb SK |
303 | static struct i2c_driver tmp102_driver = { |
304 | .driver.name = DRIVER_NAME, | |
15390c61 | 305 | .driver.of_match_table = of_match_ptr(tmp102_of_match), |
dd378b1b | 306 | .driver.pm = &tmp102_dev_pm_ops, |
beb1b6bb | 307 | .probe = tmp102_probe, |
beb1b6bb | 308 | .id_table = tmp102_id, |
beb1b6bb SK |
309 | }; |
310 | ||
f0967eea | 311 | module_i2c_driver(tmp102_driver); |
beb1b6bb | 312 | |
beb1b6bb SK |
313 | MODULE_AUTHOR("Steven King <sfking@fdwdc.com>"); |
314 | MODULE_DESCRIPTION("Texas Instruments TMP102 temperature sensor driver"); | |
315 | MODULE_LICENSE("GPL"); |