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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
08e7e278
JD		 8
9 Shamelessly ripped from the w83627hf driver
10 Copyright (C) 2003 Mark Studebaker
11
12 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
13 in testing and debugging this driver.
14
8dd2d2ca
JD		 15 This driver also supports the W83627EHG, which is the lead-free
16 version of the W83627EHF.
17
08e7e278
JD		 18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31
32
33 Supports the following chips:
34
657c93b1
DH		 35 Chip #vin #fan #pwm #temp chip IDs man ID
36 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
37 0x8860 0xa1
38 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 39 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 40 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
08e7e278
JD		 41*/
42
43#include <linux/module.h>
44#include <linux/init.h>
45#include <linux/slab.h>
1ea6dd38
DH		 46#include <linux/jiffies.h>
47#include <linux/platform_device.h>
943b0830 48#include <linux/hwmon.h>
412fec82 49#include <linux/hwmon-sysfs.h>
fc18d6c0 50#include <linux/hwmon-vid.h>
943b0830 51#include <linux/err.h>
9a61bf63 52#include <linux/mutex.h>
b9acb64a 53#include <linux/acpi.h>
08e7e278
JD		 54#include <asm/io.h>
55#include "lm75.h"
56
c1e48dce 57enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg };
08e7e278 58
1ea6dd38
DH		 59/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
60static const char * w83627ehf_device_names[] = {
61 "w83627ehf",
62 "w83627dhg",
c1e48dce 63 "w83627dhg",
237c8d2f 64 "w83667hg",
1ea6dd38
DH		 65};
66
67b671bc
JD		 67static unsigned short force_id;
68module_param(force_id, ushort, 0);
69MODULE_PARM_DESC(force_id, "Override the detected device ID");
70
1ea6dd38 71#define DRVNAME "w83627ehf"
08e7e278 72
657c93b1 73/*
1ea6dd38 74 * Super-I/O constants and functions
657c93b1 75 */
08e7e278
JD		 76
77#define W83627EHF_LD_HWM 0x0b
237c8d2f 78#define W83667HG_LD_VID 0x0d
08e7e278
JD		 79
80#define SIO_REG_LDSEL 0x07 /* Logical device select */
81#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 82#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 83#define SIO_REG_ENABLE 0x30 /* Logical device enable */
84#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 85#define SIO_REG_VID_CTRL 0xF0 /* VID control */
86#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 87
657c93b1
DH		 88#define SIO_W83627EHF_ID 0x8850
89#define SIO_W83627EHG_ID 0x8860
90#define SIO_W83627DHG_ID 0xa020
c1e48dce 91#define SIO_W83627DHG_P_ID 0xb070
237c8d2f 92#define SIO_W83667HG_ID 0xa510
657c93b1 93#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 94
95static inline void
1ea6dd38 96superio_outb(int ioreg, int reg, int val)
08e7e278 97{
1ea6dd38
DH		 98 outb(reg, ioreg);
99 outb(val, ioreg + 1);
08e7e278
JD		 100}
101
102static inline int
1ea6dd38 103superio_inb(int ioreg, int reg)
08e7e278 104{
1ea6dd38
DH		 105 outb(reg, ioreg);
106 return inb(ioreg + 1);
08e7e278
JD		 107}
108
109static inline void
1ea6dd38 110superio_select(int ioreg, int ld)
08e7e278 111{
1ea6dd38
DH		 112 outb(SIO_REG_LDSEL, ioreg);
113 outb(ld, ioreg + 1);
08e7e278
JD		 114}
115
116static inline void
1ea6dd38 117superio_enter(int ioreg)
08e7e278 118{
1ea6dd38
DH		 119 outb(0x87, ioreg);
120 outb(0x87, ioreg);
08e7e278
JD		 121}
122
123static inline void
1ea6dd38 124superio_exit(int ioreg)
08e7e278 125{
1ea6dd38
DH		 126 outb(0x02, ioreg);
127 outb(0x02, ioreg + 1);
08e7e278
JD		 128}
129
130/*
131 * ISA constants
132 */
133
1a641fce
JD		 134#define IOREGION_ALIGNMENT ~7
135#define IOREGION_OFFSET 5
136#define IOREGION_LENGTH 2
1ea6dd38
DH		 137#define ADDR_REG_OFFSET 0
138#define DATA_REG_OFFSET 1
08e7e278
JD		 139
140#define W83627EHF_REG_BANK 0x4E
141#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 142
143/* Not currently used:
144 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
145 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
146 * REG_MAN_ID is at port 0x4f
147 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 148
149static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
150static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
151
cf0676fe
RM		 152/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
153#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
154 (0x554 + (((nr) - 7) * 2)))
155#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
156 (0x555 + (((nr) - 7) * 2)))
157#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
158 (0x550 + (nr) - 7))
159
08e7e278
JD		 160#define W83627EHF_REG_TEMP1 0x27
161#define W83627EHF_REG_TEMP1_HYST 0x3a
162#define W83627EHF_REG_TEMP1_OVER 0x39
163static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
164static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
165static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
166static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
167
168/* Fan clock dividers are spread over the following five registers */
169#define W83627EHF_REG_FANDIV1 0x47
170#define W83627EHF_REG_FANDIV2 0x4B
171#define W83627EHF_REG_VBAT 0x5D
172#define W83627EHF_REG_DIODE 0x59
173#define W83627EHF_REG_SMI_OVT 0x4C
174
a4589dbb
JD		 175#define W83627EHF_REG_ALARM1 0x459
176#define W83627EHF_REG_ALARM2 0x45A
177#define W83627EHF_REG_ALARM3 0x45B
178
08c79950
RM		 179/* SmartFan registers */
180/* DC or PWM output fan configuration */
181static const u8 W83627EHF_REG_PWM_ENABLE[] = {
182 0x04, /* SYS FAN0 output mode and PWM mode */
183 0x04, /* CPU FAN0 output mode and PWM mode */
184 0x12, /* AUX FAN mode */
185 0x62, /* CPU fan1 mode */
186};
187
188static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
189static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
190
191/* FAN Duty Cycle, be used to control */
192static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
193static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
194static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
195
196
197/* Advanced Fan control, some values are common for all fans */
198static const u8 W83627EHF_REG_FAN_MIN_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
199static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0C, 0x0D, 0x17, 0x66 };
200
08e7e278
JD		 201/*
202 * Conversions
203 */
204
08c79950
RM		 205/* 1 is PWM mode, output in ms */
206static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
207{
208 return mode ? 100 * reg : 400 * reg;
209}
210
211static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
212{
213 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
214 (msec + 200) / 400), 1, 255);
215}
216
08e7e278
JD		 217static inline unsigned int
218fan_from_reg(u8 reg, unsigned int div)
219{
220 if (reg == 0 || reg == 255)
221 return 0;
222 return 1350000U / (reg * div);
223}
224
225static inline unsigned int
226div_from_reg(u8 reg)
227{
228 return 1 << reg;
229}
230
231static inline int
232temp1_from_reg(s8 reg)
233{
234 return reg * 1000;
235}
236
237static inline s8
5bfedac0 238temp1_to_reg(long temp, int min, int max)
08e7e278 239{
08c79950
RM		 240 if (temp <= min)
241 return min / 1000;
242 if (temp >= max)
243 return max / 1000;
08e7e278
JD		 244 if (temp < 0)
245 return (temp - 500) / 1000;
246 return (temp + 500) / 1000;
247}
248
cf0676fe
RM		 249/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
250
251static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
252
253static inline long in_from_reg(u8 reg, u8 nr)
254{
255 return reg * scale_in[nr];
256}
257
258static inline u8 in_to_reg(u32 val, u8 nr)
259{
260 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
261}
262
08e7e278
JD		 263/*
264 * Data structures and manipulation thereof
265 */
266
267struct w83627ehf_data {
1ea6dd38
DH		 268 int addr; /* IO base of hw monitor block */
269 const char *name;
270
1beeffe4 271 struct device *hwmon_dev;
9a61bf63 272 struct mutex lock;
08e7e278 273
9a61bf63 274 struct mutex update_lock;
08e7e278
JD		 275 char valid; /* !=0 if following fields are valid */
276 unsigned long last_updated; /* In jiffies */
277
278 /* Register values */
1ea6dd38 279 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 280 u8 in[10]; /* Register value */
281 u8 in_max[10]; /* Register value */
282 u8 in_min[10]; /* Register value */
08e7e278
JD		 283 u8 fan[5];
284 u8 fan_min[5];
285 u8 fan_div[5];
286 u8 has_fan; /* some fan inputs can be disabled */
da667365 287 u8 temp_type[3];
08e7e278
JD		 288 s8 temp1;
289 s8 temp1_max;
290 s8 temp1_max_hyst;
291 s16 temp[2];
292 s16 temp_max[2];
293 s16 temp_max_hyst[2];
a4589dbb 294 u32 alarms;
08c79950
RM		 295
296 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
297 u8 pwm_enable[4]; /* 1->manual
298 2->thermal cruise (also called SmartFan I) */
237c8d2f 299 u8 pwm_num; /* number of pwm */
08c79950
RM		 300 u8 pwm[4];
301 u8 target_temp[4];
302 u8 tolerance[4];
303
304 u8 fan_min_output[4]; /* minimum fan speed */
305 u8 fan_stop_time[4];
fc18d6c0
JD		 306
307 u8 vid;
308 u8 vrm;
a157d06d
GJ		 309
310 u8 temp3_disable;
311 u8 in6_skip;
08e7e278
JD		 312};
313
1ea6dd38
DH		 314struct w83627ehf_sio_data {
315 int sioreg;
316 enum kinds kind;
317};
318
08e7e278
JD		 319static inline int is_word_sized(u16 reg)
320{
321 return (((reg & 0xff00) == 0x100
322 || (reg & 0xff00) == 0x200)
323 && ((reg & 0x00ff) == 0x50
324 || (reg & 0x00ff) == 0x53
325 || (reg & 0x00ff) == 0x55));
326}
327
0956895a 328/* Registers 0x50-0x5f are banked */
1ea6dd38 329static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 330{
0956895a 331 if ((reg & 0x00f0) == 0x50) {
1ea6dd38
DH		 332 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
333 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 334 }
335}
336
0956895a 337/* Not strictly necessary, but play it safe for now */
1ea6dd38 338static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 339{
340 if (reg & 0xff00) {
1ea6dd38
DH		 341 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
342 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 343 }
344}
345
1ea6dd38 346static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 347{
08e7e278
JD		 348 int res, word_sized = is_word_sized(reg);
349
9a61bf63 350 mutex_lock(&data->lock);
08e7e278 351
1ea6dd38
DH		 352 w83627ehf_set_bank(data, reg);
353 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
354 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 355 if (word_sized) {
356 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 357 data->addr + ADDR_REG_OFFSET);
358 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 359 }
1ea6dd38 360 w83627ehf_reset_bank(data, reg);
08e7e278 361
9a61bf63 362 mutex_unlock(&data->lock);
08e7e278
JD		 363
364 return res;
365}
366
1ea6dd38 367static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 368{
08e7e278
JD		 369 int word_sized = is_word_sized(reg);
370
9a61bf63 371 mutex_lock(&data->lock);
08e7e278 372
1ea6dd38
DH		 373 w83627ehf_set_bank(data, reg);
374 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 375 if (word_sized) {
1ea6dd38 376 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 377 outb_p((reg & 0xff) + 1,
1ea6dd38 378 data->addr + ADDR_REG_OFFSET);
08e7e278 379 }
1ea6dd38
DH		 380 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
381 w83627ehf_reset_bank(data, reg);
08e7e278 382
9a61bf63 383 mutex_unlock(&data->lock);
08e7e278
JD		 384 return 0;
385}
386
387/* This function assumes that the caller holds data->update_lock */
1ea6dd38 388static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 389{
08e7e278
JD		 390 u8 reg;
391
392 switch (nr) {
393 case 0:
1ea6dd38 394 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 395 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 396 /* fan5 input control bit is write only, compute the value */
397 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 398 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
399 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 400 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 401 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 402 break;
403 case 1:
1ea6dd38 404 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 405 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 406 /* fan5 input control bit is write only, compute the value */
407 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 408 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
409 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 410 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 411 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 412 break;
413 case 2:
1ea6dd38 414 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 415 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 416 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
417 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 418 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 419 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 420 break;
421 case 3:
1ea6dd38 422 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 423 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 424 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
425 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 426 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 427 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 428 break;
429 case 4:
1ea6dd38 430 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 431 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 432 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 433 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 434 break;
435 }
436}
437
ea7be66c
MH		 438static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
439{
440 int i;
441
442 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
443 data->fan_div[0] = (i >> 4) & 0x03;
444 data->fan_div[1] = (i >> 6) & 0x03;
445 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
446 data->fan_div[2] = (i >> 6) & 0x03;
447 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
448 data->fan_div[0] |= (i >> 3) & 0x04;
449 data->fan_div[1] |= (i >> 4) & 0x04;
450 data->fan_div[2] |= (i >> 5) & 0x04;
451 if (data->has_fan & ((1 << 3) | (1 << 4))) {
452 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
453 data->fan_div[3] = i & 0x03;
454 data->fan_div[4] = ((i >> 2) & 0x03)
455 | ((i >> 5) & 0x04);
456 }
457 if (data->has_fan & (1 << 3)) {
458 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
459 data->fan_div[3] |= (i >> 5) & 0x04;
460 }
461}
462
08e7e278
JD		 463static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
464{
1ea6dd38 465 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 466 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 467 int i;
468
9a61bf63 469 mutex_lock(&data->update_lock);
08e7e278 470
6b3e4645 471 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 472 || !data->valid) {
473 /* Fan clock dividers */
ea7be66c 474 w83627ehf_update_fan_div(data);
08e7e278 475
cf0676fe 476 /* Measured voltages and limits */
1ea6dd38
DH		 477 for (i = 0; i < data->in_num; i++) {
478 data->in[i] = w83627ehf_read_value(data,
cf0676fe 479 W83627EHF_REG_IN(i));
1ea6dd38 480 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 481 W83627EHF_REG_IN_MIN(i));
1ea6dd38 482 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 483 W83627EHF_REG_IN_MAX(i));
484 }
485
08e7e278
JD		 486 /* Measured fan speeds and limits */
487 for (i = 0; i < 5; i++) {
488 if (!(data->has_fan & (1 << i)))
489 continue;
490
1ea6dd38 491 data->fan[i] = w83627ehf_read_value(data,
08e7e278 492 W83627EHF_REG_FAN[i]);
1ea6dd38 493 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 494 W83627EHF_REG_FAN_MIN[i]);
495
496 /* If we failed to measure the fan speed and clock
497 divider can be increased, let's try that for next
498 time */
499 if (data->fan[i] == 0xff
500 && data->fan_div[i] < 0x07) {
1ea6dd38 501 dev_dbg(dev, "Increasing fan%d "
08e7e278 502 "clock divider from %u to %u\n",
33725ad3 503 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 504 div_from_reg(data->fan_div[i] + 1));
505 data->fan_div[i]++;
1ea6dd38 506 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 507 /* Preserve min limit if possible */
508 if (data->fan_min[i] >= 2
509 && data->fan_min[i] != 255)
1ea6dd38 510 w83627ehf_write_value(data,
08e7e278
JD		 511 W83627EHF_REG_FAN_MIN[i],
512 (data->fan_min[i] /= 2));
513 }
514 }
515
08c79950 516 for (i = 0; i < 4; i++) {
77fa49d9 517 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
08c79950 518 if (i != 1) {
1ea6dd38 519 pwmcfg = w83627ehf_read_value(data,
08c79950 520 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 521 tolerance = w83627ehf_read_value(data,
08c79950
RM		 522 W83627EHF_REG_TOLERANCE[i]);
523 }
524 data->pwm_mode[i] =
525 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
526 ? 0 : 1;
527 data->pwm_enable[i] =
528 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
529 & 3) + 1;
1ea6dd38 530 data->pwm[i] = w83627ehf_read_value(data,
08c79950 531 W83627EHF_REG_PWM[i]);
1ea6dd38 532 data->fan_min_output[i] = w83627ehf_read_value(data,
08c79950 533 W83627EHF_REG_FAN_MIN_OUTPUT[i]);
1ea6dd38 534 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950
RM		 535 W83627EHF_REG_FAN_STOP_TIME[i]);
536 data->target_temp[i] =
1ea6dd38 537 w83627ehf_read_value(data,
08c79950
RM		 538 W83627EHF_REG_TARGET[i]) &
539 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
540 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
541 & 0x0f;
542 }
543
08e7e278 544 /* Measured temperatures and limits */
1ea6dd38 545 data->temp1 = w83627ehf_read_value(data,
08e7e278 546 W83627EHF_REG_TEMP1);
1ea6dd38 547 data->temp1_max = w83627ehf_read_value(data,
08e7e278 548 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 549 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 550 W83627EHF_REG_TEMP1_HYST);
551 for (i = 0; i < 2; i++) {
1ea6dd38 552 data->temp[i] = w83627ehf_read_value(data,
08e7e278 553 W83627EHF_REG_TEMP[i]);
1ea6dd38 554 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 555 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 556 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 557 W83627EHF_REG_TEMP_HYST[i]);
558 }
559
1ea6dd38 560 data->alarms = w83627ehf_read_value(data,
a4589dbb 561 W83627EHF_REG_ALARM1) |
1ea6dd38 562 (w83627ehf_read_value(data,
a4589dbb 563 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 564 (w83627ehf_read_value(data,
a4589dbb
JD		 565 W83627EHF_REG_ALARM3) << 16);
566
08e7e278
JD		 567 data->last_updated = jiffies;
568 data->valid = 1;
569 }
570
9a61bf63 571 mutex_unlock(&data->update_lock);
08e7e278
JD		 572 return data;
573}
574
575/*
576 * Sysfs callback functions
577 */
cf0676fe
RM		 578#define show_in_reg(reg) \
579static ssize_t \
580show_##reg(struct device *dev, struct device_attribute *attr, \
581 char *buf) \
582{ \
583 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
584 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
585 int nr = sensor_attr->index; \
586 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
587}
588show_in_reg(in)
589show_in_reg(in_min)
590show_in_reg(in_max)
591
592#define store_in_reg(REG, reg) \
593static ssize_t \
594store_in_##reg (struct device *dev, struct device_attribute *attr, \
595 const char *buf, size_t count) \
596{ \
1ea6dd38 597 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 598 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
599 int nr = sensor_attr->index; \
600 u32 val = simple_strtoul(buf, NULL, 10); \
601 \
602 mutex_lock(&data->update_lock); \
603 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 604 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 605 data->in_##reg[nr]); \
606 mutex_unlock(&data->update_lock); \
607 return count; \
608}
609
610store_in_reg(MIN, min)
611store_in_reg(MAX, max)
612
a4589dbb
JD		 613static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
614{
615 struct w83627ehf_data *data = w83627ehf_update_device(dev);
616 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
617 int nr = sensor_attr->index;
618 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
619}
620
cf0676fe
RM		 621static struct sensor_device_attribute sda_in_input[] = {
622 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
623 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
624 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
625 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
626 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
627 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
628 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
629 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
630 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
631 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
632};
633
a4589dbb
JD		 634static struct sensor_device_attribute sda_in_alarm[] = {
635 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
636 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
637 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
638 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
639 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
640 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
641 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
642 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
643 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
644 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
645};
646
cf0676fe
RM		 647static struct sensor_device_attribute sda_in_min[] = {
648 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
649 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
650 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
651 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
652 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
653 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
654 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
655 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
656 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
657 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
658};
659
660static struct sensor_device_attribute sda_in_max[] = {
661 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
662 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
663 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
664 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
665 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
666 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
667 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
668 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
669 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
670 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
671};
672
08e7e278
JD		 673#define show_fan_reg(reg) \
674static ssize_t \
412fec82
YM		 675show_##reg(struct device *dev, struct device_attribute *attr, \
676 char *buf) \
08e7e278
JD		 677{ \
678 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 679 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
680 int nr = sensor_attr->index; \
08e7e278
JD		 681 return sprintf(buf, "%d\n", \
682 fan_from_reg(data->reg[nr], \
683 div_from_reg(data->fan_div[nr]))); \
684}
685show_fan_reg(fan);
686show_fan_reg(fan_min);
687
688static ssize_t
412fec82
YM		 689show_fan_div(struct device *dev, struct device_attribute *attr,
690 char *buf)
08e7e278
JD		 691{
692 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 693 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
694 int nr = sensor_attr->index;
695 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 696}
697
698static ssize_t
412fec82
YM		 699store_fan_min(struct device *dev, struct device_attribute *attr,
700 const char *buf, size_t count)
08e7e278 701{
1ea6dd38 702 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 703 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
704 int nr = sensor_attr->index;
08e7e278
JD		 705 unsigned int val = simple_strtoul(buf, NULL, 10);
706 unsigned int reg;
707 u8 new_div;
708
9a61bf63 709 mutex_lock(&data->update_lock);
08e7e278
JD		 710 if (!val) {
711 /* No min limit, alarm disabled */
712 data->fan_min[nr] = 255;
713 new_div = data->fan_div[nr]; /* No change */
714 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
715 } else if ((reg = 1350000U / val) >= 128 * 255) {
716 /* Speed below this value cannot possibly be represented,
717 even with the highest divider (128) */
718 data->fan_min[nr] = 254;
719 new_div = 7; /* 128 == (1 << 7) */
720 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
721 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
722 } else if (!reg) {
723 /* Speed above this value cannot possibly be represented,
724 even with the lowest divider (1) */
725 data->fan_min[nr] = 1;
726 new_div = 0; /* 1 == (1 << 0) */
727 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 728 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 729 } else {
730 /* Automatically pick the best divider, i.e. the one such
731 that the min limit will correspond to a register value
732 in the 96..192 range */
733 new_div = 0;
734 while (reg > 192 && new_div < 7) {
735 reg >>= 1;
736 new_div++;
737 }
738 data->fan_min[nr] = reg;
739 }
740
741 /* Write both the fan clock divider (if it changed) and the new
742 fan min (unconditionally) */
743 if (new_div != data->fan_div[nr]) {
158ce075
JD		 744 /* Preserve the fan speed reading */
745 if (data->fan[nr] != 0xff) {
746 if (new_div > data->fan_div[nr])
747 data->fan[nr] >>= new_div - data->fan_div[nr];
748 else if (data->fan[nr] & 0x80)
749 data->fan[nr] = 0xff;
750 else
751 data->fan[nr] <<= data->fan_div[nr] - new_div;
752 }
08e7e278
JD		 753
754 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
755 nr + 1, div_from_reg(data->fan_div[nr]),
756 div_from_reg(new_div));
757 data->fan_div[nr] = new_div;
1ea6dd38 758 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 759 /* Give the chip time to sample a new speed value */
760 data->last_updated = jiffies;
08e7e278 761 }
1ea6dd38 762 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 763 data->fan_min[nr]);
9a61bf63 764 mutex_unlock(&data->update_lock);
08e7e278
JD		 765
766 return count;
767}
768
412fec82
YM		 769static struct sensor_device_attribute sda_fan_input[] = {
770 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
771 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
772 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
773 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
774 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
775};
08e7e278 776
a4589dbb
JD		 777static struct sensor_device_attribute sda_fan_alarm[] = {
778 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
779 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
780 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
781 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
782 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
783};
784
412fec82
YM		 785static struct sensor_device_attribute sda_fan_min[] = {
786 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
787 store_fan_min, 0),
788 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
789 store_fan_min, 1),
790 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
791 store_fan_min, 2),
792 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
793 store_fan_min, 3),
794 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
795 store_fan_min, 4),
796};
08e7e278 797
412fec82
YM		 798static struct sensor_device_attribute sda_fan_div[] = {
799 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
800 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
801 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
802 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
803 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
804};
805
08e7e278
JD		 806#define show_temp1_reg(reg) \
807static ssize_t \
6f637a64
GKH		 808show_##reg(struct device *dev, struct device_attribute *attr, \
809 char *buf) \
08e7e278
JD		 810{ \
811 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
812 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
813}
814show_temp1_reg(temp1);
815show_temp1_reg(temp1_max);
816show_temp1_reg(temp1_max_hyst);
817
818#define store_temp1_reg(REG, reg) \
819static ssize_t \
6f637a64
GKH		 820store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
821 const char *buf, size_t count) \
08e7e278 822{ \
1ea6dd38 823 struct w83627ehf_data *data = dev_get_drvdata(dev); \
5bfedac0 824 long val = simple_strtol(buf, NULL, 10); \
08e7e278 825 \
9a61bf63 826 mutex_lock(&data->update_lock); \
08c79950 827 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 828 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 829 data->temp1_##reg); \
9a61bf63 830 mutex_unlock(&data->update_lock); \
08e7e278
JD		 831 return count; \
832}
833store_temp1_reg(OVER, max);
834store_temp1_reg(HYST, max_hyst);
835
08e7e278
JD		 836#define show_temp_reg(reg) \
837static ssize_t \
412fec82
YM		 838show_##reg(struct device *dev, struct device_attribute *attr, \
839 char *buf) \
08e7e278
JD		 840{ \
841 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 842 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
843 int nr = sensor_attr->index; \
08e7e278
JD		 844 return sprintf(buf, "%d\n", \
845 LM75_TEMP_FROM_REG(data->reg[nr])); \
846}
847show_temp_reg(temp);
848show_temp_reg(temp_max);
849show_temp_reg(temp_max_hyst);
850
851#define store_temp_reg(REG, reg) \
852static ssize_t \
412fec82
YM		 853store_##reg(struct device *dev, struct device_attribute *attr, \
854 const char *buf, size_t count) \
08e7e278 855{ \
1ea6dd38 856 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 857 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
858 int nr = sensor_attr->index; \
5bfedac0 859 long val = simple_strtol(buf, NULL, 10); \
08e7e278 860 \
9a61bf63 861 mutex_lock(&data->update_lock); \
08e7e278 862 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 863 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 864 data->reg[nr]); \
9a61bf63 865 mutex_unlock(&data->update_lock); \
08e7e278
JD		 866 return count; \
867}
868store_temp_reg(OVER, temp_max);
869store_temp_reg(HYST, temp_max_hyst);
870
da667365
JD		 871static ssize_t
872show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
873{
874 struct w83627ehf_data *data = w83627ehf_update_device(dev);
875 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
876 int nr = sensor_attr->index;
877 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
878}
879
a157d06d 880static struct sensor_device_attribute sda_temp_input[] = {
412fec82
YM		 881 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
882 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
883 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
a157d06d
GJ		 884};
885
886static struct sensor_device_attribute sda_temp_max[] = {
412fec82
YM		 887 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
888 store_temp1_max, 0),
889 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
890 store_temp_max, 0),
891 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
892 store_temp_max, 1),
a157d06d
GJ		 893};
894
895static struct sensor_device_attribute sda_temp_max_hyst[] = {
412fec82
YM		 896 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
897 store_temp1_max_hyst, 0),
898 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
899 store_temp_max_hyst, 0),
900 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
901 store_temp_max_hyst, 1),
a157d06d
GJ		 902};
903
904static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 905 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
906 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
907 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 908};
909
910static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 911 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
912 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
913 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 914};
08e7e278 915
08c79950
RM		 916#define show_pwm_reg(reg) \
917static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
918 char *buf) \
919{ \
920 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
921 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
922 int nr = sensor_attr->index; \
923 return sprintf(buf, "%d\n", data->reg[nr]); \
924}
925
926show_pwm_reg(pwm_mode)
927show_pwm_reg(pwm_enable)
928show_pwm_reg(pwm)
929
930static ssize_t
931store_pwm_mode(struct device *dev, struct device_attribute *attr,
932 const char *buf, size_t count)
933{
1ea6dd38 934 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 935 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
936 int nr = sensor_attr->index;
937 u32 val = simple_strtoul(buf, NULL, 10);
938 u16 reg;
939
940 if (val > 1)
941 return -EINVAL;
942 mutex_lock(&data->update_lock);
1ea6dd38 943 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 944 data->pwm_mode[nr] = val;
945 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
946 if (!val)
947 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 948 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 949 mutex_unlock(&data->update_lock);
950 return count;
951}
952
953static ssize_t
954store_pwm(struct device *dev, struct device_attribute *attr,
955 const char *buf, size_t count)
956{
1ea6dd38 957 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 958 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
959 int nr = sensor_attr->index;
960 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
961
962 mutex_lock(&data->update_lock);
963 data->pwm[nr] = val;
1ea6dd38 964 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 965 mutex_unlock(&data->update_lock);
966 return count;
967}
968
969static ssize_t
970store_pwm_enable(struct device *dev, struct device_attribute *attr,
971 const char *buf, size_t count)
972{
1ea6dd38 973 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 974 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
975 int nr = sensor_attr->index;
976 u32 val = simple_strtoul(buf, NULL, 10);
977 u16 reg;
978
979 if (!val || (val > 2)) /* only modes 1 and 2 are supported */
980 return -EINVAL;
981 mutex_lock(&data->update_lock);
1ea6dd38 982 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 983 data->pwm_enable[nr] = val;
984 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
985 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 986 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 987 mutex_unlock(&data->update_lock);
988 return count;
989}
990
991
992#define show_tol_temp(reg) \
993static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
994 char *buf) \
995{ \
996 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
997 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
998 int nr = sensor_attr->index; \
999 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
1000}
1001
1002show_tol_temp(tolerance)
1003show_tol_temp(target_temp)
1004
1005static ssize_t
1006store_target_temp(struct device *dev, struct device_attribute *attr,
1007 const char *buf, size_t count)
1008{
1ea6dd38 1009 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1010 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1011 int nr = sensor_attr->index;
1012 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
1013
1014 mutex_lock(&data->update_lock);
1015 data->target_temp[nr] = val;
1ea6dd38 1016 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 1017 mutex_unlock(&data->update_lock);
1018 return count;
1019}
1020
1021static ssize_t
1022store_tolerance(struct device *dev, struct device_attribute *attr,
1023 const char *buf, size_t count)
1024{
1ea6dd38 1025 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1026 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1027 int nr = sensor_attr->index;
1028 u16 reg;
1029 /* Limit the temp to 0C - 15C */
1030 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
1031
1032 mutex_lock(&data->update_lock);
1ea6dd38 1033 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 1034 data->tolerance[nr] = val;
1035 if (nr == 1)
1036 reg = (reg & 0x0f) | (val << 4);
1037 else
1038 reg = (reg & 0xf0) | val;
1ea6dd38 1039 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 1040 mutex_unlock(&data->update_lock);
1041 return count;
1042}
1043
1044static struct sensor_device_attribute sda_pwm[] = {
1045 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1046 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1047 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1048 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1049};
1050
1051static struct sensor_device_attribute sda_pwm_mode[] = {
1052 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1053 store_pwm_mode, 0),
1054 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1055 store_pwm_mode, 1),
1056 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1057 store_pwm_mode, 2),
1058 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1059 store_pwm_mode, 3),
1060};
1061
1062static struct sensor_device_attribute sda_pwm_enable[] = {
1063 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1064 store_pwm_enable, 0),
1065 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1066 store_pwm_enable, 1),
1067 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1068 store_pwm_enable, 2),
1069 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1070 store_pwm_enable, 3),
1071};
1072
1073static struct sensor_device_attribute sda_target_temp[] = {
1074 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1075 store_target_temp, 0),
1076 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1077 store_target_temp, 1),
1078 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1079 store_target_temp, 2),
1080 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1081 store_target_temp, 3),
1082};
1083
1084static struct sensor_device_attribute sda_tolerance[] = {
1085 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1086 store_tolerance, 0),
1087 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1088 store_tolerance, 1),
1089 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1090 store_tolerance, 2),
1091 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1092 store_tolerance, 3),
1093};
1094
08c79950
RM		 1095/* Smart Fan registers */
1096
1097#define fan_functions(reg, REG) \
1098static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1099 char *buf) \
1100{ \
1101 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1102 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1103 int nr = sensor_attr->index; \
1104 return sprintf(buf, "%d\n", data->reg[nr]); \
1105}\
1106static ssize_t \
1107store_##reg(struct device *dev, struct device_attribute *attr, \
1108 const char *buf, size_t count) \
1109{\
1ea6dd38 1110 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1111 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1112 int nr = sensor_attr->index; \
1113 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1114 mutex_lock(&data->update_lock); \
1115 data->reg[nr] = val; \
1ea6dd38 1116 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1117 mutex_unlock(&data->update_lock); \
1118 return count; \
1119}
1120
1121fan_functions(fan_min_output, FAN_MIN_OUTPUT)
1122
1123#define fan_time_functions(reg, REG) \
1124static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1125 char *buf) \
1126{ \
1127 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1128 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1129 int nr = sensor_attr->index; \
1130 return sprintf(buf, "%d\n", \
1131 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1132} \
1133\
1134static ssize_t \
1135store_##reg(struct device *dev, struct device_attribute *attr, \
1136 const char *buf, size_t count) \
1137{ \
1ea6dd38 1138 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1139 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1140 int nr = sensor_attr->index; \
1141 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1142 data->pwm_mode[nr]); \
1143 mutex_lock(&data->update_lock); \
1144 data->reg[nr] = val; \
1ea6dd38 1145 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1146 mutex_unlock(&data->update_lock); \
1147 return count; \
1148} \
1149
1150fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1151
1ea6dd38
DH		 1152static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1153 char *buf)
1154{
1155 struct w83627ehf_data *data = dev_get_drvdata(dev);
1156
1157 return sprintf(buf, "%s\n", data->name);
1158}
1159static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1160
1161static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1162 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1163 store_fan_stop_time, 3),
1164 SENSOR_ATTR(pwm4_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1165 store_fan_min_output, 3),
1166};
1167
1168static struct sensor_device_attribute sda_sf3_arrays[] = {
1169 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1170 store_fan_stop_time, 0),
1171 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1172 store_fan_stop_time, 1),
1173 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1174 store_fan_stop_time, 2),
1175 SENSOR_ATTR(pwm1_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1176 store_fan_min_output, 0),
1177 SENSOR_ATTR(pwm2_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1178 store_fan_min_output, 1),
1179 SENSOR_ATTR(pwm3_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1180 store_fan_min_output, 2),
1181};
1182
fc18d6c0
JD		 1183static ssize_t
1184show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1185{
1186 struct w83627ehf_data *data = dev_get_drvdata(dev);
1187 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1188}
1189static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1190
08e7e278 1191/*
1ea6dd38 1192 * Driver and device management
08e7e278
JD		 1193 */
1194
c18beb5b
DH		 1195static void w83627ehf_device_remove_files(struct device *dev)
1196{
1197 /* some entries in the following arrays may not have been used in
1198 * device_create_file(), but device_remove_file() will ignore them */
1199 int i;
1ea6dd38 1200 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1201
1202 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1203 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1204 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1205 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1206 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1207 if ((i == 6) && data->in6_skip)
1208 continue;
c18beb5b
DH		 1209 device_remove_file(dev, &sda_in_input[i].dev_attr);
1210 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1211 device_remove_file(dev, &sda_in_min[i].dev_attr);
1212 device_remove_file(dev, &sda_in_max[i].dev_attr);
1213 }
1214 for (i = 0; i < 5; i++) {
1215 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1216 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1217 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1218 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1219 }
237c8d2f 1220 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1221 device_remove_file(dev, &sda_pwm[i].dev_attr);
1222 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1223 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1224 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1225 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1226 }
a157d06d
GJ		 1227 for (i = 0; i < 3; i++) {
1228 if ((i == 2) && data->temp3_disable)
1229 continue;
1230 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1231 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1232 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1233 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1234 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1235 }
c18beb5b 1236
1ea6dd38 1237 device_remove_file(dev, &dev_attr_name);
cbe311f2 1238 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1239}
08e7e278 1240
1ea6dd38
DH		 1241/* Get the monitoring functions started */
1242static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1243{
1244 int i;
da667365 1245 u8 tmp, diode;
08e7e278
JD		 1246
1247 /* Start monitoring is needed */
1ea6dd38 1248 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1249 if (!(tmp & 0x01))
1ea6dd38 1250 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1251 tmp | 0x01);
1252
1253 /* Enable temp2 and temp3 if needed */
1254 for (i = 0; i < 2; i++) {
1ea6dd38 1255 tmp = w83627ehf_read_value(data,
08e7e278 1256 W83627EHF_REG_TEMP_CONFIG[i]);
a157d06d
GJ		 1257 if ((i == 1) && data->temp3_disable)
1258 continue;
08e7e278 1259 if (tmp & 0x01)
1ea6dd38 1260 w83627ehf_write_value(data,
08e7e278
JD		 1261 W83627EHF_REG_TEMP_CONFIG[i],
1262 tmp & 0xfe);
1263 }
d3130f0e
JD		 1264
1265 /* Enable VBAT monitoring if needed */
1266 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1267 if (!(tmp & 0x01))
1268 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1269
1270 /* Get thermal sensor types */
1271 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1272 for (i = 0; i < 3; i++) {
1273 if ((tmp & (0x02 << i)))
1274 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1275 else
1276 data->temp_type[i] = 4; /* thermistor */
1277 }
08e7e278
JD		 1278}
1279
1ea6dd38 1280static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1281{
1ea6dd38
DH		 1282 struct device *dev = &pdev->dev;
1283 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1284 struct w83627ehf_data *data;
1ea6dd38 1285 struct resource *res;
fc18d6c0 1286 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1287 int i, err = 0;
1288
1ea6dd38
DH		 1289 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1290 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1291 err = -EBUSY;
1ea6dd38
DH		 1292 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1293 (unsigned long)res->start,
1294 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1295 goto exit;
1296 }
1297
ba9c2e8d 1298 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1299 err = -ENOMEM;
1300 goto exit_release;
1301 }
08e7e278 1302
1ea6dd38 1303 data->addr = res->start;
9a61bf63 1304 mutex_init(&data->lock);
9a61bf63 1305 mutex_init(&data->update_lock);
1ea6dd38
DH		 1306 data->name = w83627ehf_device_names[sio_data->kind];
1307 platform_set_drvdata(pdev, data);
08e7e278 1308
237c8d2f
GJ		 1309 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1310 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
1311 /* 667HG has 3 pwms */
1312 data->pwm_num = (sio_data->kind == w83667hg) ? 3 : 4;
08e7e278 1313
a157d06d
GJ		 1314 /* Check temp3 configuration bit for 667HG */
1315 if (sio_data->kind == w83667hg) {
1316 data->temp3_disable = w83627ehf_read_value(data,
1317 W83627EHF_REG_TEMP_CONFIG[1]) & 0x01;
1318 data->in6_skip = !data->temp3_disable;
1319 }
1320
08e7e278 1321 /* Initialize the chip */
1ea6dd38 1322 w83627ehf_init_device(data);
08e7e278 1323
fc18d6c0
JD		 1324 data->vrm = vid_which_vrm();
1325 superio_enter(sio_data->sioreg);
fc18d6c0 1326 /* Read VID value */
237c8d2f
GJ		 1327 if (sio_data->kind == w83667hg) {
1328 /* W83667HG has different pins for VID input and output, so
1329 we can get the VID input values directly at logical device D
1330 0xe3. */
1331 superio_select(sio_data->sioreg, W83667HG_LD_VID);
1332 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 1333 err = device_create_file(dev, &dev_attr_cpu0_vid);
1334 if (err)
1335 goto exit_release;
58e6e781 1336 } else {
237c8d2f
GJ		 1337 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1338 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
1339 /* Set VID input sensibility if needed. In theory the
1340 BIOS should have set it, but in practice it's not
1341 always the case. We only do it for the W83627EHF/EHG
1342 because the W83627DHG is more complex in this
1343 respect. */
1344 if (sio_data->kind == w83627ehf) {
1345 en_vrm10 = superio_inb(sio_data->sioreg,
1346 SIO_REG_EN_VRM10);
1347 if ((en_vrm10 & 0x08) && data->vrm == 90) {
1348 dev_warn(dev, "Setting VID input "
1349 "voltage to TTL\n");
1350 superio_outb(sio_data->sioreg,
1351 SIO_REG_EN_VRM10,
1352 en_vrm10 & ~0x08);
1353 } else if (!(en_vrm10 & 0x08)
1354 && data->vrm == 100) {
1355 dev_warn(dev, "Setting VID input "
1356 "voltage to VRM10\n");
1357 superio_outb(sio_data->sioreg,
1358 SIO_REG_EN_VRM10,
1359 en_vrm10 | 0x08);
1360 }
1361 }
1362
1363 data->vid = superio_inb(sio_data->sioreg,
1364 SIO_REG_VID_DATA);
1365 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1366 data->vid &= 0x3f;
1367
1368 err = device_create_file(dev, &dev_attr_cpu0_vid);
1369 if (err)
1370 goto exit_release;
1371 } else {
1372 dev_info(dev, "VID pins in output mode, CPU VID not "
1373 "available\n");
1374 }
fc18d6c0
JD		 1375 }
1376
08c79950 1377 /* fan4 and fan5 share some pins with the GPIO and serial flash */
237c8d2f
GJ		 1378 if (sio_data->kind == w83667hg) {
1379 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1380 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1381 } else {
1382 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1383 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1384 }
1ea6dd38 1385 superio_exit(sio_data->sioreg);
08c79950 1386
08e7e278 1387 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1388 as fan on/off switches, but fan5 control is write only :/
1389 We assume that if the serial interface is disabled, designers
1390 connected fan5 as input unless they are emitting log 1, which
1391 is not the default. */
08c79950 1392
08e7e278 1393 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1394 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1704b26e 1395 if ((i & (1 << 2)) && fan4pin)
08e7e278 1396 data->has_fan |= (1 << 3);
1704b26e 1397 if (!(i & (1 << 1)) && fan5pin)
08e7e278
JD		 1398 data->has_fan |= (1 << 4);
1399
ea7be66c
MH		 1400 /* Read fan clock dividers immediately */
1401 w83627ehf_update_fan_div(data);
1402
08e7e278 1403 /* Register sysfs hooks */
08c79950 1404 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1405 if ((err = device_create_file(dev,
1406 &sda_sf3_arrays[i].dev_attr)))
1407 goto exit_remove;
08c79950
RM		 1408
1409 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 1410 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b
DH		 1411 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1412 if ((err = device_create_file(dev,
1413 &sda_sf3_arrays_fan4[i].dev_attr)))
1414 goto exit_remove;
1415 }
08c79950 1416
a157d06d
GJ		 1417 for (i = 0; i < data->in_num; i++) {
1418 if ((i == 6) && data->in6_skip)
1419 continue;
c18beb5b
DH		 1420 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1421 || (err = device_create_file(dev,
1422 &sda_in_alarm[i].dev_attr))
1423 || (err = device_create_file(dev,
1424 &sda_in_min[i].dev_attr))
1425 || (err = device_create_file(dev,
1426 &sda_in_max[i].dev_attr)))
1427 goto exit_remove;
a157d06d 1428 }
cf0676fe 1429
412fec82 1430 for (i = 0; i < 5; i++) {
08c79950 1431 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1432 if ((err = device_create_file(dev,
1433 &sda_fan_input[i].dev_attr))
1434 || (err = device_create_file(dev,
1435 &sda_fan_alarm[i].dev_attr))
1436 || (err = device_create_file(dev,
1437 &sda_fan_div[i].dev_attr))
1438 || (err = device_create_file(dev,
1439 &sda_fan_min[i].dev_attr)))
1440 goto exit_remove;
237c8d2f 1441 if (i < data->pwm_num &&
c18beb5b
DH		 1442 ((err = device_create_file(dev,
1443 &sda_pwm[i].dev_attr))
1444 || (err = device_create_file(dev,
1445 &sda_pwm_mode[i].dev_attr))
1446 || (err = device_create_file(dev,
1447 &sda_pwm_enable[i].dev_attr))
1448 || (err = device_create_file(dev,
1449 &sda_target_temp[i].dev_attr))
1450 || (err = device_create_file(dev,
1451 &sda_tolerance[i].dev_attr))))
1452 goto exit_remove;
08c79950 1453 }
08e7e278 1454 }
08c79950 1455
a157d06d
GJ		 1456 for (i = 0; i < 3; i++) {
1457 if ((i == 2) && data->temp3_disable)
1458 continue;
1459 if ((err = device_create_file(dev,
1460 &sda_temp_input[i].dev_attr))
1461 || (err = device_create_file(dev,
1462 &sda_temp_max[i].dev_attr))
1463 || (err = device_create_file(dev,
1464 &sda_temp_max_hyst[i].dev_attr))
1465 || (err = device_create_file(dev,
1466 &sda_temp_alarm[i].dev_attr))
1467 || (err = device_create_file(dev,
1468 &sda_temp_type[i].dev_attr)))
c18beb5b 1469 goto exit_remove;
a157d06d 1470 }
c18beb5b 1471
1ea6dd38
DH		 1472 err = device_create_file(dev, &dev_attr_name);
1473 if (err)
1474 goto exit_remove;
1475
1beeffe4
TJ		 1476 data->hwmon_dev = hwmon_device_register(dev);
1477 if (IS_ERR(data->hwmon_dev)) {
1478 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 1479 goto exit_remove;
1480 }
08e7e278
JD		 1481
1482 return 0;
1483
c18beb5b
DH		 1484exit_remove:
1485 w83627ehf_device_remove_files(dev);
08e7e278 1486 kfree(data);
1ea6dd38 1487 platform_set_drvdata(pdev, NULL);
08e7e278 1488exit_release:
1ea6dd38 1489 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1490exit:
1491 return err;
1492}
1493
1ea6dd38 1494static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1495{
1ea6dd38 1496 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1497
1beeffe4 1498 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 1499 w83627ehf_device_remove_files(&pdev->dev);
1500 release_region(data->addr, IOREGION_LENGTH);
1501 platform_set_drvdata(pdev, NULL);
943b0830 1502 kfree(data);
08e7e278
JD		 1503
1504 return 0;
1505}
1506
1ea6dd38 1507static struct platform_driver w83627ehf_driver = {
cdaf7934 1508 .driver = {
87218842 1509 .owner = THIS_MODULE,
1ea6dd38 1510 .name = DRVNAME,
cdaf7934 1511 },
1ea6dd38
DH		 1512 .probe = w83627ehf_probe,
1513 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1514};
1515
1ea6dd38
DH		 1516/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1517static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1518 struct w83627ehf_sio_data *sio_data)
08e7e278 1519{
1ea6dd38
DH		 1520 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1521 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1522 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 1523 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 1524 static const char __initdata sio_name_W83667HG[] = "W83667HG";
1ea6dd38 1525
08e7e278 1526 u16 val;
1ea6dd38 1527 const char *sio_name;
08e7e278 1528
1ea6dd38 1529 superio_enter(sioaddr);
08e7e278 1530
67b671bc
JD		 1531 if (force_id)
1532 val = force_id;
1533 else
1534 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1535 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1536 switch (val & SIO_ID_MASK) {
657c93b1 1537 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1538 sio_data->kind = w83627ehf;
1539 sio_name = sio_name_W83627EHF;
1540 break;
657c93b1 1541 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1542 sio_data->kind = w83627ehf;
1543 sio_name = sio_name_W83627EHG;
1544 break;
1545 case SIO_W83627DHG_ID:
1546 sio_data->kind = w83627dhg;
1547 sio_name = sio_name_W83627DHG;
657c93b1 1548 break;
c1e48dce
JD		 1549 case SIO_W83627DHG_P_ID:
1550 sio_data->kind = w83627dhg_p;
1551 sio_name = sio_name_W83627DHG_P;
1552 break;
237c8d2f
GJ		 1553 case SIO_W83667HG_ID:
1554 sio_data->kind = w83667hg;
1555 sio_name = sio_name_W83667HG;
1556 break;
657c93b1 1557 default:
9f66036b
JD		 1558 if (val != 0xffff)
1559 pr_debug(DRVNAME ": unsupported chip ID: 0x%04x\n",
1560 val);
1ea6dd38 1561 superio_exit(sioaddr);
08e7e278
JD		 1562 return -ENODEV;
1563 }
1564
1ea6dd38
DH		 1565 /* We have a known chip, find the HWM I/O address */
1566 superio_select(sioaddr, W83627EHF_LD_HWM);
1567 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1568 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1569 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1570 if (*addr == 0) {
475ef855
DH		 1571 printk(KERN_ERR DRVNAME ": Refusing to enable a Super-I/O "
1572 "device with a base I/O port 0.\n");
1ea6dd38 1573 superio_exit(sioaddr);
08e7e278
JD		 1574 return -ENODEV;
1575 }
1576
1577 /* Activate logical device if needed */
1ea6dd38 1578 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855
DH		 1579 if (!(val & 0x01)) {
1580 printk(KERN_WARNING DRVNAME ": Forcibly enabling Super-I/O. "
1581 "Sensor is probably unusable.\n");
1ea6dd38 1582 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1583 }
1ea6dd38
DH		 1584
1585 superio_exit(sioaddr);
1586 pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
1587 sio_data->sioreg = sioaddr;
08e7e278 1588
08e7e278
JD		 1589 return 0;
1590}
1591
1ea6dd38
DH		 1592/* when Super-I/O functions move to a separate file, the Super-I/O
1593 * bus will manage the lifetime of the device and this module will only keep
1594 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1595 * must keep track of the device */
1596static struct platform_device *pdev;
1597
08e7e278
JD		 1598static int __init sensors_w83627ehf_init(void)
1599{
1ea6dd38
DH		 1600 int err;
1601 unsigned short address;
1602 struct resource res;
1603 struct w83627ehf_sio_data sio_data;
1604
1605 /* initialize sio_data->kind and sio_data->sioreg.
1606 *
1607 * when Super-I/O functions move to a separate file, the Super-I/O
1608 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1609 * w83627ehf hardware monitor, and call probe() */
1610 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1611 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1612 return -ENODEV;
1613
1ea6dd38
DH		 1614 err = platform_driver_register(&w83627ehf_driver);
1615 if (err)
1616 goto exit;
1617
1618 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1619 err = -ENOMEM;
1620 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1621 goto exit_unregister;
1622 }
1623
1624 err = platform_device_add_data(pdev, &sio_data,
1625 sizeof(struct w83627ehf_sio_data));
1626 if (err) {
1627 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1628 goto exit_device_put;
1629 }
1630
1631 memset(&res, 0, sizeof(res));
1632 res.name = DRVNAME;
1633 res.start = address + IOREGION_OFFSET;
1634 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1635 res.flags = IORESOURCE_IO;
b9acb64a
JD		 1636
1637 err = acpi_check_resource_conflict(&res);
1638 if (err)
18632f84 1639 goto exit_device_put;
b9acb64a 1640
1ea6dd38
DH		 1641 err = platform_device_add_resources(pdev, &res, 1);
1642 if (err) {
1643 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1644 "(%d)\n", err);
1645 goto exit_device_put;
1646 }
1647
1648 /* platform_device_add calls probe() */
1649 err = platform_device_add(pdev);
1650 if (err) {
1651 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1652 err);
1653 goto exit_device_put;
1654 }
1655
1656 return 0;
1657
1658exit_device_put:
1659 platform_device_put(pdev);
1660exit_unregister:
1661 platform_driver_unregister(&w83627ehf_driver);
1662exit:
1663 return err;
08e7e278
JD		 1664}
1665
1666static void __exit sensors_w83627ehf_exit(void)
1667{
1ea6dd38
DH		 1668 platform_device_unregister(pdev);
1669 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1670}
1671
1672MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1673MODULE_DESCRIPTION("W83627EHF driver");
1674MODULE_LICENSE("GPL");
1675
1676module_init(sensors_w83627ehf_init);
1677module_exit(sensors_w83627ehf_exit);
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