]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/hwmon/w83627ehf.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'asoc-v5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-hirsute-kernel.git] / drivers / hwmon / w83627ehf.c
CommitLineData
74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
08e7e278 2/*
8969e84d
GR		 3 * w83627ehf - Driver for the hardware monitoring functionality of
4 * the Winbond W83627EHF Super-I/O chip
7c81c60f 5 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
8969e84d
GR		 6 * Copyright (C) 2006 Yuan Mu (Winbond),
7 * Rudolf Marek <r.marek@assembler.cz>
8 * David Hubbard <david.c.hubbard@gmail.com>
9 * Daniel J Blueman <daniel.blueman@gmail.com>
10 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
11 *
12 * Shamelessly ripped from the w83627hf driver
13 * Copyright (C) 2003 Mark Studebaker
14 *
15 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
16 * in testing and debugging this driver.
17 *
18 * This driver also supports the W83627EHG, which is the lead-free
19 * version of the W83627EHF.
20 *
8969e84d
GR		 21 * Supports the following chips:
22 *
23 * Chip #vin #fan #pwm #temp chip IDs man ID
24 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
25 * 0x8860 0xa1
26 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
27 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
28 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
29 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
30 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
8969e84d 31 */
08e7e278 32
abdc6fd1
JP		 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
08e7e278
JD		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/slab.h>
1ea6dd38
DH		 38#include <linux/jiffies.h>
39#include <linux/platform_device.h>
943b0830 40#include <linux/hwmon.h>
412fec82 41#include <linux/hwmon-sysfs.h>
fc18d6c0 42#include <linux/hwmon-vid.h>
943b0830 43#include <linux/err.h>
9a61bf63 44#include <linux/mutex.h>
b9acb64a 45#include <linux/acpi.h>
6055fae8 46#include <linux/io.h>
08e7e278
JD		 47#include "lm75.h"
48
eff7687d
JD		 49enum kinds {
50 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
3207408a 51 w83667hg, w83667hg_b,
eff7687d 52};
08e7e278 53
1ea6dd38 54/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 55static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 56 "w83627ehf",
57 "w83627dhg",
c1e48dce 58 "w83627dhg",
eff7687d 59 "w83627uhg",
237c8d2f 60 "w83667hg",
c39aedaf 61 "w83667hg",
1ea6dd38
DH		 62};
63
67b671bc
JD		 64static unsigned short force_id;
65module_param(force_id, ushort, 0);
66MODULE_PARM_DESC(force_id, "Override the detected device ID");
67
1ea6dd38 68#define DRVNAME "w83627ehf"
08e7e278 69
657c93b1 70/*
1ea6dd38 71 * Super-I/O constants and functions
657c93b1 72 */
08e7e278
JD		 73
74#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 75#define W83667HG_LD_VID 0x0d
08e7e278
JD		 76
77#define SIO_REG_LDSEL 0x07 /* Logical device select */
78#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 79#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 80#define SIO_REG_ENABLE 0x30 /* Logical device enable */
81#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 82#define SIO_REG_VID_CTRL 0xF0 /* VID control */
83#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 84
657c93b1
DH		 85#define SIO_W83627EHF_ID 0x8850
86#define SIO_W83627EHG_ID 0x8860
87#define SIO_W83627DHG_ID 0xa020
c1e48dce 88#define SIO_W83627DHG_P_ID 0xb070
eff7687d 89#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 90#define SIO_W83667HG_ID 0xa510
c39aedaf 91#define SIO_W83667HG_B_ID 0xb350
657c93b1 92#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 93
94static inline void
1ea6dd38 95superio_outb(int ioreg, int reg, int val)
08e7e278 96{
1ea6dd38
DH		 97 outb(reg, ioreg);
98 outb(val, ioreg + 1);
08e7e278
JD		 99}
100
101static inline int
1ea6dd38 102superio_inb(int ioreg, int reg)
08e7e278 103{
1ea6dd38
DH		 104 outb(reg, ioreg);
105 return inb(ioreg + 1);
08e7e278
JD		 106}
107
108static inline void
1ea6dd38 109superio_select(int ioreg, int ld)
08e7e278 110{
1ea6dd38
DH		 111 outb(SIO_REG_LDSEL, ioreg);
112 outb(ld, ioreg + 1);
08e7e278
JD		 113}
114
0d023530 115static inline int
1ea6dd38 116superio_enter(int ioreg)
08e7e278 117{
0d023530
KS		 118 if (!request_muxed_region(ioreg, 2, DRVNAME))
119 return -EBUSY;
120
1ea6dd38
DH		 121 outb(0x87, ioreg);
122 outb(0x87, ioreg);
0d023530
KS		 123
124 return 0;
08e7e278
JD		 125}
126
127static inline void
1ea6dd38 128superio_exit(int ioreg)
08e7e278 129{
022b75a3 130 outb(0xaa, ioreg);
1ea6dd38
DH		 131 outb(0x02, ioreg);
132 outb(0x02, ioreg + 1);
0d023530 133 release_region(ioreg, 2);
08e7e278
JD		 134}
135
136/*
137 * ISA constants
138 */
139
e7e1ca6e 140#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 141#define IOREGION_OFFSET 5
142#define IOREGION_LENGTH 2
1ea6dd38
DH		 143#define ADDR_REG_OFFSET 0
144#define DATA_REG_OFFSET 1
08e7e278
JD		 145
146#define W83627EHF_REG_BANK 0x4E
147#define W83627EHF_REG_CONFIG 0x40
657c93b1 148
8969e84d
GR		 149/*
150 * Not currently used:
657c93b1
DH		 151 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
152 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
153 * REG_MAN_ID is at port 0x4f
8969e84d
GR		 154 * REG_CHIP_ID is at port 0x58
155 */
08e7e278
JD		 156
157static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
158static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
159
cf0676fe
RM		 160/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
161#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
162 (0x554 + (((nr) - 7) * 2)))
163#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
164 (0x555 + (((nr) - 7) * 2)))
165#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
166 (0x550 + (nr) - 7))
167
d36cf32c
GR		 168static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
169static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
170static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
171static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 172
173/* Fan clock dividers are spread over the following five registers */
174#define W83627EHF_REG_FANDIV1 0x47
175#define W83627EHF_REG_FANDIV2 0x4B
176#define W83627EHF_REG_VBAT 0x5D
177#define W83627EHF_REG_DIODE 0x59
178#define W83627EHF_REG_SMI_OVT 0x4C
179
a4589dbb
JD		 180#define W83627EHF_REG_ALARM1 0x459
181#define W83627EHF_REG_ALARM2 0x45A
182#define W83627EHF_REG_ALARM3 0x45B
183
363a12a4
DA		 184#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
185#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
186
08c79950 187/* SmartFan registers */
41e9a062
DB		 188#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
189#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
190
08c79950
RM		 191/* DC or PWM output fan configuration */
192static const u8 W83627EHF_REG_PWM_ENABLE[] = {
193 0x04, /* SYS FAN0 output mode and PWM mode */
194 0x04, /* CPU FAN0 output mode and PWM mode */
195 0x12, /* AUX FAN mode */
41e9a062 196 0x62, /* CPU FAN1 mode */
08c79950
RM		 197};
198
199static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
200static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
201
202/* FAN Duty Cycle, be used to control */
279af1a9
GR		 203static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
204static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 205static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
206
08c79950 207/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 208static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
209static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
210static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 211
279af1a9 212static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 213 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 214static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 215 = { 0xff, 0x68, 0xff, 0x6a };
216
279af1a9
GR		 217static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
218static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
219 = { 0x68, 0x6a, 0x6c };
08c79950 220
840e191d
GR		 221static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
222
d36cf32c
GR		 223static const char *const w83667hg_b_temp_label[] = {
224 "SYSTIN",
225 "CPUTIN",
226 "AUXTIN",
227 "AMDTSI",
228 "PECI Agent 1",
229 "PECI Agent 2",
230 "PECI Agent 3",
231 "PECI Agent 4"
232};
233
3207408a 234#define NUM_REG_TEMP ARRAY_SIZE(W83627EHF_REG_TEMP)
d36cf32c 235
17296feb 236static int is_word_sized(u16 reg)
bce26c58 237{
ec3e5a16 238 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 239 || (reg & 0xff00) == 0x200)
240 && ((reg & 0x00ff) == 0x50
241 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 242 || (reg & 0x00ff) == 0x55))
243 || (reg & 0xfff0) == 0x630
244 || reg == 0x640 || reg == 0x642
245 || ((reg & 0xfff0) == 0x650
246 && (reg & 0x000f) >= 0x06)
247 || reg == 0x73 || reg == 0x75 || reg == 0x77
248 );
bce26c58
GR		 249}
250
08e7e278
JD		 251/*
252 * Conversions
253 */
254
08c79950
RM		 255/* 1 is PWM mode, output in ms */
256static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
257{
258 return mode ? 100 * reg : 400 * reg;
259}
260
261static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
262{
2a844c14
GR		 263 return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
264 1, 255);
08c79950
RM		 265}
266
26bc440e 267static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 268{
26bc440e 269 if (reg == 0 || reg == 255)
08e7e278 270 return 0;
26bc440e
GR		 271 return 1350000U / (reg << divreg);
272}
273
08e7e278
JD		 274static inline unsigned int
275div_from_reg(u8 reg)
276{
277 return 1 << reg;
278}
279
8969e84d
GR		 280/*
281 * Some of the voltage inputs have internal scaling, the tables below
282 * contain 8 (the ADC LSB in mV) * scaling factor * 100
283 */
eff7687d
JD		 284static const u16 scale_in_common[10] = {
285 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
286};
287static const u16 scale_in_w83627uhg[9] = {
288 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
289};
cf0676fe 290
eff7687d 291static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 292{
eff7687d 293 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 294}
295
eff7687d 296static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 297{
2a844c14 298 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
cf0676fe
RM		 299}
300
08e7e278
JD		 301/*
302 * Data structures and manipulation thereof
303 */
304
305struct w83627ehf_data {
1ea6dd38
DH		 306 int addr; /* IO base of hw monitor block */
307 const char *name;
308
9a61bf63 309 struct mutex lock;
08e7e278 310
ec3e5a16
GR		 311 u16 reg_temp[NUM_REG_TEMP];
312 u16 reg_temp_over[NUM_REG_TEMP];
313 u16 reg_temp_hyst[NUM_REG_TEMP];
314 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 315 u8 temp_src[NUM_REG_TEMP];
316 const char * const *temp_label;
317
279af1a9
GR		 318 const u16 *REG_FAN_MAX_OUTPUT;
319 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 320 const u16 *scale_in;
da2e0255 321
9a61bf63 322 struct mutex update_lock;
08e7e278
JD		 323 char valid; /* !=0 if following fields are valid */
324 unsigned long last_updated; /* In jiffies */
325
326 /* Register values */
83cc8985 327 u8 bank; /* current register bank */
1ea6dd38 328 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 329 u8 in[10]; /* Register value */
330 u8 in_max[10]; /* Register value */
331 u8 in_min[10]; /* Register value */
3382a918 332 unsigned int rpm[5];
ec3e5a16 333 u16 fan_min[5];
08e7e278
JD		 334 u8 fan_div[5];
335 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 336 u8 has_fan_min; /* some fans don't have min register */
da667365 337 u8 temp_type[3];
840e191d 338 s8 temp_offset[3];
ec3e5a16
GR		 339 s16 temp[9];
340 s16 temp_max[9];
341 s16 temp_max_hyst[9];
a4589dbb 342 u32 alarms;
363a12a4 343 u8 caseopen;
08c79950
RM		 344
345 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
346 u8 pwm_enable[4]; /* 1->manual
8969e84d
GR		 347 * 2->thermal cruise mode (also called SmartFan I)
348 * 3->fan speed cruise mode
349 * 4->variable thermal cruise (also called
350 * SmartFan III)
351 * 5->enhanced variable thermal cruise (also called
352 * SmartFan IV)
353 */
b84bb518 354 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 355 u8 pwm_num; /* number of pwm */
08c79950
RM		 356 u8 pwm[4];
357 u8 target_temp[4];
358 u8 tolerance[4];
359
41e9a062
DB		 360 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
361 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
362 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
363 u8 fan_max_output[4]; /* maximum fan speed */
364 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 365
366 u8 vid;
367 u8 vrm;
a157d06d 368
ec3e5a16 369 u16 have_temp;
840e191d 370 u16 have_temp_offset;
eff7687d
JD		 371 u8 in6_skip:1;
372 u8 temp3_val_only:1;
266cd583 373 u8 have_vid:1;
7e630bb5
JD		 374
375#ifdef CONFIG_PM
376 /* Remember extra register values over suspend/resume */
377 u8 vbat;
378 u8 fandiv1;
379 u8 fandiv2;
380#endif
08e7e278
JD		 381};
382
1ea6dd38
DH		 383struct w83627ehf_sio_data {
384 int sioreg;
385 enum kinds kind;
386};
387
83cc8985
GR		 388/*
389 * On older chips, only registers 0x50-0x5f are banked.
390 * On more recent chips, all registers are banked.
391 * Assume that is the case and set the bank number for each access.
392 * Cache the bank number so it only needs to be set if it changes.
393 */
1ea6dd38 394static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 395{
83cc8985
GR		 396 u8 bank = reg >> 8;
397 if (data->bank != bank) {
1ea6dd38 398 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 399 outb_p(bank, data->addr + DATA_REG_OFFSET);
400 data->bank = bank;
08e7e278
JD		 401 }
402}
403
1ea6dd38 404static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 405{
08e7e278
JD		 406 int res, word_sized = is_word_sized(reg);
407
9a61bf63 408 mutex_lock(&data->lock);
08e7e278 409
1ea6dd38
DH		 410 w83627ehf_set_bank(data, reg);
411 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
412 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 413 if (word_sized) {
414 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 415 data->addr + ADDR_REG_OFFSET);
416 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 417 }
08e7e278 418
9a61bf63 419 mutex_unlock(&data->lock);
08e7e278
JD		 420 return res;
421}
422
e7e1ca6e
GR		 423static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
424 u16 value)
08e7e278 425{
08e7e278
JD		 426 int word_sized = is_word_sized(reg);
427
9a61bf63 428 mutex_lock(&data->lock);
08e7e278 429
1ea6dd38
DH		 430 w83627ehf_set_bank(data, reg);
431 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 432 if (word_sized) {
1ea6dd38 433 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 434 outb_p((reg & 0xff) + 1,
1ea6dd38 435 data->addr + ADDR_REG_OFFSET);
08e7e278 436 }
1ea6dd38 437 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 438
9a61bf63 439 mutex_unlock(&data->lock);
08e7e278
JD		 440 return 0;
441}
442
c5794cfa
JD		 443/* We left-align 8-bit temperature values to make the code simpler */
444static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
445{
446 u16 res;
447
448 res = w83627ehf_read_value(data, reg);
449 if (!is_word_sized(reg))
450 res <<= 8;
451
452 return res;
453}
454
455static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
456 u16 value)
457{
458 if (!is_word_sized(reg))
459 value >>= 8;
460 return w83627ehf_write_value(data, reg, value);
461}
462
08e7e278 463/* This function assumes that the caller holds data->update_lock */
1ea6dd38 464static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 465{
08e7e278
JD		 466 u8 reg;
467
468 switch (nr) {
469 case 0:
1ea6dd38 470 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 471 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 472 /* fan5 input control bit is write only, compute the value */
473 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 474 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
475 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 476 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 477 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 478 break;
479 case 1:
1ea6dd38 480 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 481 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 482 /* fan5 input control bit is write only, compute the value */
483 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 484 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
485 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 486 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 487 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 488 break;
489 case 2:
1ea6dd38 490 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 491 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 492 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
493 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 494 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 495 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 496 break;
497 case 3:
1ea6dd38 498 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 499 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 500 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
501 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 502 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 503 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 504 break;
505 case 4:
1ea6dd38 506 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 507 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 508 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 509 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 510 break;
511 }
512}
513
ea7be66c
MH		 514static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
515{
516 int i;
517
518 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
519 data->fan_div[0] = (i >> 4) & 0x03;
520 data->fan_div[1] = (i >> 6) & 0x03;
521 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
522 data->fan_div[2] = (i >> 6) & 0x03;
523 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
524 data->fan_div[0] |= (i >> 3) & 0x04;
525 data->fan_div[1] |= (i >> 4) & 0x04;
526 data->fan_div[2] |= (i >> 5) & 0x04;
527 if (data->has_fan & ((1 << 3) | (1 << 4))) {
528 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
529 data->fan_div[3] = i & 0x03;
530 data->fan_div[4] = ((i >> 2) & 0x03)
531 | ((i >> 5) & 0x04);
532 }
533 if (data->has_fan & (1 << 3)) {
534 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
535 data->fan_div[3] |= (i >> 5) & 0x04;
536 }
537}
538
ec3e5a16
GR		 539static void w83627ehf_update_pwm(struct w83627ehf_data *data)
540{
541 int i;
542 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
543
544 for (i = 0; i < data->pwm_num; i++) {
545 if (!(data->has_fan & (1 << i)))
546 continue;
547
548 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
549 if (i != 1) {
550 pwmcfg = w83627ehf_read_value(data,
551 W83627EHF_REG_PWM_ENABLE[i]);
552 tolerance = w83627ehf_read_value(data,
553 W83627EHF_REG_TOLERANCE[i]);
554 }
555 data->pwm_mode[i] =
556 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
557 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
558 & 3) + 1;
69595502 559 data->pwm[i] = w83627ehf_read_value(data, W83627EHF_REG_PWM[i]);
ec3e5a16
GR		 560
561 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
562 }
563}
564
08e7e278
JD		 565static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
566{
1ea6dd38 567 struct w83627ehf_data *data = dev_get_drvdata(dev);
08e7e278
JD		 568 int i;
569
9a61bf63 570 mutex_lock(&data->update_lock);
08e7e278 571
6b3e4645 572 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 573 || !data->valid) {
574 /* Fan clock dividers */
69595502 575 w83627ehf_update_fan_div(data);
08e7e278 576
cf0676fe 577 /* Measured voltages and limits */
1ea6dd38 578 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 579 if ((i == 6) && data->in6_skip)
580 continue;
581
1ea6dd38 582 data->in[i] = w83627ehf_read_value(data,
cf0676fe 583 W83627EHF_REG_IN(i));
1ea6dd38 584 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 585 W83627EHF_REG_IN_MIN(i));
1ea6dd38 586 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 587 W83627EHF_REG_IN_MAX(i));
588 }
589
08e7e278
JD		 590 /* Measured fan speeds and limits */
591 for (i = 0; i < 5; i++) {
3382a918
GR		 592 u16 reg;
593
08e7e278
JD		 594 if (!(data->has_fan & (1 << i)))
595 continue;
596
69595502
DDAG		 597 reg = w83627ehf_read_value(data, W83627EHF_REG_FAN[i]);
598 data->rpm[i] = fan_from_reg8(reg, data->fan_div[i]);
ec3e5a16
GR		 599
600 if (data->has_fan_min & (1 << i))
601 data->fan_min[i] = w83627ehf_read_value(data,
69595502 602 W83627EHF_REG_FAN_MIN[i]);
08e7e278 603
8969e84d
GR		 604 /*
605 * If we failed to measure the fan speed and clock
606 * divider can be increased, let's try that for next
607 * time
608 */
69595502 609 if (reg >= 0xff && data->fan_div[i] < 0x07) {
b55f3757
GR		 610 dev_dbg(dev,
611 "Increasing fan%d clock divider from %u to %u\n",
33725ad3 612 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 613 div_from_reg(data->fan_div[i] + 1));
614 data->fan_div[i]++;
69595502 615 w83627ehf_write_fan_div(data, i);
08e7e278 616 /* Preserve min limit if possible */
ec3e5a16
GR		 617 if ((data->has_fan_min & (1 << i))
618 && data->fan_min[i] >= 2
08e7e278 619 && data->fan_min[i] != 255)
1ea6dd38 620 w83627ehf_write_value(data,
69595502 621 W83627EHF_REG_FAN_MIN[i],
08e7e278
JD		 622 (data->fan_min[i] /= 2));
623 }
624 }
625
69595502 626 w83627ehf_update_pwm(data);
ec3e5a16 627
da2e0255
GR		 628 for (i = 0; i < data->pwm_num; i++) {
629 if (!(data->has_fan & (1 << i)))
630 continue;
631
ec3e5a16
GR		 632 data->fan_start_output[i] =
633 w83627ehf_read_value(data,
69595502 634 W83627EHF_REG_FAN_START_OUTPUT[i]);
ec3e5a16
GR		 635 data->fan_stop_output[i] =
636 w83627ehf_read_value(data,
69595502 637 W83627EHF_REG_FAN_STOP_OUTPUT[i]);
ec3e5a16
GR		 638 data->fan_stop_time[i] =
639 w83627ehf_read_value(data,
69595502 640 W83627EHF_REG_FAN_STOP_TIME[i]);
ec3e5a16
GR		 641
642 if (data->REG_FAN_MAX_OUTPUT &&
643 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 644 data->fan_max_output[i] =
645 w83627ehf_read_value(data,
ec3e5a16 646 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 647
ec3e5a16
GR		 648 if (data->REG_FAN_STEP_OUTPUT &&
649 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 650 data->fan_step_output[i] =
651 w83627ehf_read_value(data,
ec3e5a16 652 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 653
08c79950 654 data->target_temp[i] =
1ea6dd38 655 w83627ehf_read_value(data,
69595502 656 W83627EHF_REG_TARGET[i]) &
08c79950 657 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 658 }
659
08e7e278 660 /* Measured temperatures and limits */
d36cf32c
GR		 661 for (i = 0; i < NUM_REG_TEMP; i++) {
662 if (!(data->have_temp & (1 << i)))
663 continue;
c5794cfa 664 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 665 data->reg_temp[i]);
666 if (data->reg_temp_over[i])
667 data->temp_max[i]
c5794cfa 668 = w83627ehf_read_temp(data,
ec3e5a16
GR		 669 data->reg_temp_over[i]);
670 if (data->reg_temp_hyst[i])
671 data->temp_max_hyst[i]
c5794cfa 672 = w83627ehf_read_temp(data,
ec3e5a16 673 data->reg_temp_hyst[i]);
45633fb3
JD		 674 if (i > 2)
675 continue;
840e191d
GR		 676 if (data->have_temp_offset & (1 << i))
677 data->temp_offset[i]
678 = w83627ehf_read_value(data,
679 W83627EHF_REG_TEMP_OFFSET[i]);
08e7e278
JD		 680 }
681
1ea6dd38 682 data->alarms = w83627ehf_read_value(data,
a4589dbb 683 W83627EHF_REG_ALARM1) |
1ea6dd38 684 (w83627ehf_read_value(data,
a4589dbb 685 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 686 (w83627ehf_read_value(data,
a4589dbb
JD		 687 W83627EHF_REG_ALARM3) << 16);
688
363a12a4
DA		 689 data->caseopen = w83627ehf_read_value(data,
690 W83627EHF_REG_CASEOPEN_DET);
691
08e7e278
JD		 692 data->last_updated = jiffies;
693 data->valid = 1;
694 }
695
9a61bf63 696 mutex_unlock(&data->update_lock);
08e7e278
JD		 697 return data;
698}
699
cf0676fe 700#define store_in_reg(REG, reg) \
266cd583
DDAG		 701static int \
702store_in_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
703 long val) \
cf0676fe 704{ \
266cd583
DDAG		 705 if (val < 0) \
706 return -EINVAL; \
cf0676fe 707 mutex_lock(&data->update_lock); \
266cd583
DDAG		 708 data->in_##reg[channel] = in_to_reg(val, channel, data->scale_in); \
709 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
710 data->in_##reg[channel]); \
cf0676fe 711 mutex_unlock(&data->update_lock); \
266cd583 712 return 0; \
cf0676fe
RM		 713}
714
715store_in_reg(MIN, min)
716store_in_reg(MAX, max)
717
266cd583
DDAG		 718static int
719store_fan_min(struct device *dev, struct w83627ehf_data *data, int channel,
720 long val)
08e7e278 721{
08e7e278
JD		 722 unsigned int reg;
723 u8 new_div;
724
266cd583
DDAG		 725 if (val < 0)
726 return -EINVAL;
bce26c58 727
9a61bf63 728 mutex_lock(&data->update_lock);
08e7e278
JD		 729 if (!val) {
730 /* No min limit, alarm disabled */
266cd583
DDAG		 731 data->fan_min[channel] = 255;
732 new_div = data->fan_div[channel]; /* No change */
733 dev_info(dev, "fan%u low limit and alarm disabled\n",
734 channel + 1);
08e7e278 735 } else if ((reg = 1350000U / val) >= 128 * 255) {
8969e84d
GR		 736 /*
737 * Speed below this value cannot possibly be represented,
738 * even with the highest divider (128)
739 */
266cd583 740 data->fan_min[channel] = 254;
08e7e278 741 new_div = 7; /* 128 == (1 << 7) */
b55f3757
GR		 742 dev_warn(dev,
743 "fan%u low limit %lu below minimum %u, set to minimum\n",
69595502 744 channel + 1, val, fan_from_reg8(254, 7));
08e7e278 745 } else if (!reg) {
8969e84d
GR		 746 /*
747 * Speed above this value cannot possibly be represented,
748 * even with the lowest divider (1)
749 */
266cd583 750 data->fan_min[channel] = 1;
08e7e278 751 new_div = 0; /* 1 == (1 << 0) */
b55f3757
GR		 752 dev_warn(dev,
753 "fan%u low limit %lu above maximum %u, set to maximum\n",
69595502 754 channel + 1, val, fan_from_reg8(1, 0));
08e7e278 755 } else {
8969e84d
GR		 756 /*
757 * Automatically pick the best divider, i.e. the one such
758 * that the min limit will correspond to a register value
759 * in the 96..192 range
760 */
08e7e278
JD		 761 new_div = 0;
762 while (reg > 192 && new_div < 7) {
763 reg >>= 1;
764 new_div++;
765 }
266cd583 766 data->fan_min[channel] = reg;
08e7e278
JD		 767 }
768
8969e84d
GR		 769 /*
770 * Write both the fan clock divider (if it changed) and the new
771 * fan min (unconditionally)
772 */
266cd583 773 if (new_div != data->fan_div[channel]) {
08e7e278 774 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
266cd583 775 channel + 1, div_from_reg(data->fan_div[channel]),
08e7e278 776 div_from_reg(new_div));
266cd583 777 data->fan_div[channel] = new_div;
69595502 778 w83627ehf_write_fan_div(data, channel);
6b3e4645
JD		 779 /* Give the chip time to sample a new speed value */
780 data->last_updated = jiffies;
08e7e278 781 }
69595502
DDAG		 782
783 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
266cd583 784 data->fan_min[channel]);
9a61bf63 785 mutex_unlock(&data->update_lock);
08e7e278 786
266cd583 787 return 0;
08e7e278 788}
08e7e278 789
ec3e5a16 790#define store_temp_reg(addr, reg) \
266cd583
DDAG		 791static int \
792store_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
793 long val) \
08e7e278 794{ \
9a61bf63 795 mutex_lock(&data->update_lock); \
266cd583
DDAG		 796 data->reg[channel] = LM75_TEMP_TO_REG(val); \
797 w83627ehf_write_temp(data, data->addr[channel], data->reg[channel]); \
9a61bf63 798 mutex_unlock(&data->update_lock); \
266cd583 799 return 0; \
08e7e278 800}
ec3e5a16
GR		 801store_temp_reg(reg_temp_over, temp_max);
802store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 803
266cd583
DDAG		 804static int
805store_temp_offset(struct device *dev, struct w83627ehf_data *data, int channel,
806 long val)
840e191d 807{
2a844c14 808 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
840e191d
GR		 809
810 mutex_lock(&data->update_lock);
266cd583
DDAG		 811 data->temp_offset[channel] = val;
812 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
840e191d 813 mutex_unlock(&data->update_lock);
266cd583 814 return 0;
08c79950
RM		 815}
816
266cd583
DDAG		 817static int
818store_pwm_mode(struct device *dev, struct w83627ehf_data *data, int channel,
819 long val)
08c79950 820{
08c79950
RM		 821 u16 reg;
822
266cd583 823 if (val < 0 || val > 1)
08c79950 824 return -EINVAL;
ad77c3e1 825
08c79950 826 mutex_lock(&data->update_lock);
266cd583
DDAG		 827 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[channel]);
828 data->pwm_mode[channel] = val;
829 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[channel]);
08c79950 830 if (!val)
266cd583
DDAG		 831 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[channel];
832 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
08c79950 833 mutex_unlock(&data->update_lock);
266cd583 834 return 0;
08c79950
RM		 835}
836
266cd583
DDAG		 837static int
838store_pwm(struct device *dev, struct w83627ehf_data *data, int channel,
839 long val)
08c79950 840{
2a844c14 841 val = clamp_val(val, 0, 255);
08c79950
RM		 842
843 mutex_lock(&data->update_lock);
266cd583 844 data->pwm[channel] = val;
69595502 845 w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
08c79950 846 mutex_unlock(&data->update_lock);
266cd583 847 return 0;
08c79950
RM		 848}
849
266cd583
DDAG		 850static int
851store_pwm_enable(struct device *dev, struct w83627ehf_data *data, int channel,
852 long val)
08c79950 853{
08c79950
RM		 854 u16 reg;
855
266cd583
DDAG		 856 if (!val || val < 0 ||
857 (val > 4 && val != data->pwm_enable_orig[channel]))
08c79950 858 return -EINVAL;
ec3e5a16 859
08c79950 860 mutex_lock(&data->update_lock);
266cd583 861 data->pwm_enable[channel] = val;
3207408a
DDAG		 862 reg = w83627ehf_read_value(data,
863 W83627EHF_REG_PWM_ENABLE[channel]);
864 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]);
865 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[channel];
866 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
867 reg);
08c79950 868 mutex_unlock(&data->update_lock);
266cd583 869 return 0;
08c79950
RM		 870}
871
08c79950
RM		 872#define show_tol_temp(reg) \
873static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
874 char *buf) \
875{ \
266cd583 876 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
e7e1ca6e
GR		 877 struct sensor_device_attribute *sensor_attr = \
878 to_sensor_dev_attr(attr); \
08c79950 879 int nr = sensor_attr->index; \
bce26c58 880 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 881}
882
883show_tol_temp(tolerance)
884show_tol_temp(target_temp)
885
886static ssize_t
887store_target_temp(struct device *dev, struct device_attribute *attr,
888 const char *buf, size_t count)
889{
1ea6dd38 890 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 891 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
892 int nr = sensor_attr->index;
bce26c58
GR		 893 long val;
894 int err;
895
179c4fdb 896 err = kstrtol(buf, 10, &val);
bce26c58
GR		 897 if (err < 0)
898 return err;
899
2a844c14 900 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 901
902 mutex_lock(&data->update_lock);
903 data->target_temp[nr] = val;
69595502 904 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 905 mutex_unlock(&data->update_lock);
906 return count;
907}
908
909static ssize_t
910store_tolerance(struct device *dev, struct device_attribute *attr,
911 const char *buf, size_t count)
912{
1ea6dd38 913 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 914 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
915 int nr = sensor_attr->index;
916 u16 reg;
bce26c58
GR		 917 long val;
918 int err;
919
179c4fdb 920 err = kstrtol(buf, 10, &val);
bce26c58
GR		 921 if (err < 0)
922 return err;
923
08c79950 924 /* Limit the temp to 0C - 15C */
2a844c14 925 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 926
927 mutex_lock(&data->update_lock);
3207408a
DDAG		 928 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
929 if (nr == 1)
930 reg = (reg & 0x0f) | (val << 4);
931 else
08c79950 932 reg = (reg & 0xf0) | val;
3207408a 933 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
ec3e5a16 934 data->tolerance[nr] = val;
08c79950
RM		 935 mutex_unlock(&data->update_lock);
936 return count;
937}
938
8f772035 939static SENSOR_DEVICE_ATTR(pwm1_target, 0644, show_target_temp,
266cd583 940 store_target_temp, 0);
8f772035 941static SENSOR_DEVICE_ATTR(pwm2_target, 0644, show_target_temp,
266cd583 942 store_target_temp, 1);
8f772035 943static SENSOR_DEVICE_ATTR(pwm3_target, 0644, show_target_temp,
266cd583 944 store_target_temp, 2);
8f772035 945static SENSOR_DEVICE_ATTR(pwm4_target, 0644, show_target_temp,
266cd583
DDAG		 946 store_target_temp, 3);
947
8f772035 948static SENSOR_DEVICE_ATTR(pwm1_tolerance, 0644, show_tolerance,
266cd583 949 store_tolerance, 0);
8f772035 950static SENSOR_DEVICE_ATTR(pwm2_tolerance, 0644, show_tolerance,
266cd583 951 store_tolerance, 1);
8f772035 952static SENSOR_DEVICE_ATTR(pwm3_tolerance, 0644, show_tolerance,
266cd583 953 store_tolerance, 2);
8f772035 954static SENSOR_DEVICE_ATTR(pwm4_tolerance, 0644, show_tolerance,
266cd583 955 store_tolerance, 3);
08c79950 956
08c79950
RM		 957/* Smart Fan registers */
958
959#define fan_functions(reg, REG) \
960static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
961 char *buf) \
962{ \
266cd583 963 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
e7e1ca6e
GR		 964 struct sensor_device_attribute *sensor_attr = \
965 to_sensor_dev_attr(attr); \
08c79950
RM		 966 int nr = sensor_attr->index; \
967 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 968} \
08c79950
RM		 969static ssize_t \
970store_##reg(struct device *dev, struct device_attribute *attr, \
971 const char *buf, size_t count) \
e7e1ca6e 972{ \
1ea6dd38 973 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 974 struct sensor_device_attribute *sensor_attr = \
975 to_sensor_dev_attr(attr); \
08c79950 976 int nr = sensor_attr->index; \
bce26c58
GR		 977 unsigned long val; \
978 int err; \
179c4fdb 979 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 980 if (err < 0) \
981 return err; \
2a844c14 982 val = clamp_val(val, 1, 255); \
08c79950
RM		 983 mutex_lock(&data->update_lock); \
984 data->reg[nr] = val; \
69595502 985 w83627ehf_write_value(data, REG[nr], val); \
08c79950
RM		 986 mutex_unlock(&data->update_lock); \
987 return count; \
988}
989
69595502
DDAG		 990fan_functions(fan_start_output, W83627EHF_REG_FAN_START_OUTPUT)
991fan_functions(fan_stop_output, W83627EHF_REG_FAN_STOP_OUTPUT)
992fan_functions(fan_max_output, data->REG_FAN_MAX_OUTPUT)
993fan_functions(fan_step_output, data->REG_FAN_STEP_OUTPUT)
08c79950
RM		 994
995#define fan_time_functions(reg, REG) \
996static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
997 char *buf) \
998{ \
266cd583 999 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
e7e1ca6e
GR		 1000 struct sensor_device_attribute *sensor_attr = \
1001 to_sensor_dev_attr(attr); \
08c79950
RM		 1002 int nr = sensor_attr->index; \
1003 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1004 step_time_from_reg(data->reg[nr], \
1005 data->pwm_mode[nr])); \
08c79950
RM		 1006} \
1007\
1008static ssize_t \
1009store_##reg(struct device *dev, struct device_attribute *attr, \
1010 const char *buf, size_t count) \
1011{ \
1ea6dd38 1012 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1013 struct sensor_device_attribute *sensor_attr = \
1014 to_sensor_dev_attr(attr); \
08c79950 1015 int nr = sensor_attr->index; \
bce26c58
GR		 1016 unsigned long val; \
1017 int err; \
179c4fdb 1018 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1019 if (err < 0) \
1020 return err; \
1021 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1022 mutex_lock(&data->update_lock); \
1023 data->reg[nr] = val; \
69595502 1024 w83627ehf_write_value(data, REG[nr], val); \
08c79950
RM		 1025 mutex_unlock(&data->update_lock); \
1026 return count; \
1027} \
1028
69595502 1029fan_time_functions(fan_stop_time, W83627EHF_REG_FAN_STOP_TIME)
08c79950 1030
8f772035 1031static SENSOR_DEVICE_ATTR(pwm4_stop_time, 0644, show_fan_stop_time,
266cd583 1032 store_fan_stop_time, 3);
8f772035 1033static SENSOR_DEVICE_ATTR(pwm4_start_output, 0644, show_fan_start_output,
266cd583 1034 store_fan_start_output, 3);
8f772035 1035static SENSOR_DEVICE_ATTR(pwm4_stop_output, 0644, show_fan_stop_output,
266cd583 1036 store_fan_stop_output, 3);
8f772035 1037static SENSOR_DEVICE_ATTR(pwm4_max_output, 0644, show_fan_max_output,
266cd583 1038 store_fan_max_output, 3);
8f772035 1039static SENSOR_DEVICE_ATTR(pwm4_step_output, 0644, show_fan_step_output,
266cd583
DDAG		 1040 store_fan_step_output, 3);
1041
8f772035 1042static SENSOR_DEVICE_ATTR(pwm3_stop_time, 0644, show_fan_stop_time,
266cd583 1043 store_fan_stop_time, 2);
8f772035 1044static SENSOR_DEVICE_ATTR(pwm3_start_output, 0644, show_fan_start_output,
266cd583 1045 store_fan_start_output, 2);
8f772035 1046static SENSOR_DEVICE_ATTR(pwm3_stop_output, 0644, show_fan_stop_output,
266cd583
DDAG		 1047 store_fan_stop_output, 2);
1048
8f772035 1049static SENSOR_DEVICE_ATTR(pwm1_stop_time, 0644, show_fan_stop_time,
266cd583 1050 store_fan_stop_time, 0);
8f772035 1051static SENSOR_DEVICE_ATTR(pwm2_stop_time, 0644, show_fan_stop_time,
266cd583 1052 store_fan_stop_time, 1);
8f772035 1053static SENSOR_DEVICE_ATTR(pwm1_start_output, 0644, show_fan_start_output,
266cd583 1054 store_fan_start_output, 0);
8f772035 1055static SENSOR_DEVICE_ATTR(pwm2_start_output, 0644, show_fan_start_output,
266cd583 1056 store_fan_start_output, 1);
8f772035 1057static SENSOR_DEVICE_ATTR(pwm1_stop_output, 0644, show_fan_stop_output,
266cd583 1058 store_fan_stop_output, 0);
8f772035 1059static SENSOR_DEVICE_ATTR(pwm2_stop_output, 0644, show_fan_stop_output,
266cd583 1060 store_fan_stop_output, 1);
41e9a062 1061
da2e0255
GR		 1062
1063/*
1064 * pwm1 and pwm3 don't support max and step settings on all chips.
1065 * Need to check support while generating/removing attribute files.
1066 */
8f772035 1067static SENSOR_DEVICE_ATTR(pwm1_max_output, 0644, show_fan_max_output,
266cd583 1068 store_fan_max_output, 0);
8f772035 1069static SENSOR_DEVICE_ATTR(pwm1_step_output, 0644, show_fan_step_output,
266cd583 1070 store_fan_step_output, 0);
8f772035 1071static SENSOR_DEVICE_ATTR(pwm2_max_output, 0644, show_fan_max_output,
266cd583 1072 store_fan_max_output, 1);
8f772035 1073static SENSOR_DEVICE_ATTR(pwm2_step_output, 0644, show_fan_step_output,
266cd583 1074 store_fan_step_output, 1);
8f772035 1075static SENSOR_DEVICE_ATTR(pwm3_max_output, 0644, show_fan_max_output,
266cd583 1076 store_fan_max_output, 2);
8f772035 1077static SENSOR_DEVICE_ATTR(pwm3_step_output, 0644, show_fan_step_output,
266cd583 1078 store_fan_step_output, 2);
08c79950 1079
fc18d6c0 1080static ssize_t
9bbacbfe 1081cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
fc18d6c0
JD		 1082{
1083 struct w83627ehf_data *data = dev_get_drvdata(dev);
1084 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1085}
266cd583 1086DEVICE_ATTR_RO(cpu0_vid);
fc18d6c0 1087
363a12a4
DA		 1088
1089/* Case open detection */
266cd583
DDAG		 1090static int
1091clear_caseopen(struct device *dev, struct w83627ehf_data *data, int channel,
1092 long val)
363a12a4 1093{
931f397b
DDAG		 1094 const u16 mask = 0x80;
1095 u16 reg;
363a12a4 1096
931f397b 1097 if (val != 0 || channel != 0)
363a12a4
DA		 1098 return -EINVAL;
1099
363a12a4
DA		 1100 mutex_lock(&data->update_lock);
1101 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1102 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1103 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1104 data->valid = 0; /* Force cache refresh */
1105 mutex_unlock(&data->update_lock);
1106
266cd583 1107 return 0;
363a12a4
DA		 1108}
1109
266cd583
DDAG		 1110static umode_t w83627ehf_attrs_visible(struct kobject *kobj,
1111 struct attribute *a, int n)
c18beb5b 1112{
266cd583 1113 struct device *dev = container_of(kobj, struct device, kobj);
1ea6dd38 1114 struct w83627ehf_data *data = dev_get_drvdata(dev);
266cd583
DDAG		 1115 struct device_attribute *devattr;
1116 struct sensor_device_attribute *sda;
1117
1118 devattr = container_of(a, struct device_attribute, attr);
1119
1120 /* Not sensor */
1121 if (devattr->show == cpu0_vid_show && data->have_vid)
1122 return a->mode;
1123
1124 sda = (struct sensor_device_attribute *)devattr;
1125
1126 if (sda->index < 2 &&
1127 (devattr->show == show_fan_stop_time ||
1128 devattr->show == show_fan_start_output ||
1129 devattr->show == show_fan_stop_output))
1130 return a->mode;
1131
1132 if (sda->index < 3 &&
1133 (devattr->show == show_fan_max_output ||
1134 devattr->show == show_fan_step_output) &&
1135 data->REG_FAN_STEP_OUTPUT &&
1136 data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff)
1137 return a->mode;
1138
1139 /* if fan3 and fan4 are enabled create the files for them */
1140 if (sda->index == 2 &&
1141 (data->has_fan & (1 << 2)) && data->pwm_num >= 3 &&
1142 (devattr->show == show_fan_stop_time ||
1143 devattr->show == show_fan_start_output ||
1144 devattr->show == show_fan_stop_output))
1145 return a->mode;
1146
1147 if (sda->index == 3 &&
1148 (data->has_fan & (1 << 3)) && data->pwm_num >= 4 &&
1149 (devattr->show == show_fan_stop_time ||
1150 devattr->show == show_fan_start_output ||
1151 devattr->show == show_fan_stop_output ||
1152 devattr->show == show_fan_max_output ||
1153 devattr->show == show_fan_step_output))
1154 return a->mode;
1155
1156 if ((devattr->show == show_target_temp ||
1157 devattr->show == show_tolerance) &&
1158 (data->has_fan & (1 << sda->index)) &&
1159 sda->index < data->pwm_num)
1160 return a->mode;
c18beb5b 1161
266cd583
DDAG		 1162 return 0;
1163}
c18beb5b 1164
266cd583
DDAG		 1165/* These groups handle non-standard attributes used in this device */
1166static struct attribute *w83627ehf_attrs[] = {
1167
1168 &sensor_dev_attr_pwm1_stop_time.dev_attr.attr,
1169 &sensor_dev_attr_pwm1_start_output.dev_attr.attr,
1170 &sensor_dev_attr_pwm1_stop_output.dev_attr.attr,
1171 &sensor_dev_attr_pwm1_max_output.dev_attr.attr,
1172 &sensor_dev_attr_pwm1_step_output.dev_attr.attr,
1173 &sensor_dev_attr_pwm1_target.dev_attr.attr,
1174 &sensor_dev_attr_pwm1_tolerance.dev_attr.attr,
1175
1176 &sensor_dev_attr_pwm2_stop_time.dev_attr.attr,
1177 &sensor_dev_attr_pwm2_start_output.dev_attr.attr,
1178 &sensor_dev_attr_pwm2_stop_output.dev_attr.attr,
1179 &sensor_dev_attr_pwm2_max_output.dev_attr.attr,
1180 &sensor_dev_attr_pwm2_step_output.dev_attr.attr,
1181 &sensor_dev_attr_pwm2_target.dev_attr.attr,
1182 &sensor_dev_attr_pwm2_tolerance.dev_attr.attr,
1183
1184 &sensor_dev_attr_pwm3_stop_time.dev_attr.attr,
1185 &sensor_dev_attr_pwm3_start_output.dev_attr.attr,
1186 &sensor_dev_attr_pwm3_stop_output.dev_attr.attr,
1187 &sensor_dev_attr_pwm3_max_output.dev_attr.attr,
1188 &sensor_dev_attr_pwm3_step_output.dev_attr.attr,
1189 &sensor_dev_attr_pwm3_target.dev_attr.attr,
1190 &sensor_dev_attr_pwm3_tolerance.dev_attr.attr,
1191
1192 &sensor_dev_attr_pwm4_stop_time.dev_attr.attr,
1193 &sensor_dev_attr_pwm4_start_output.dev_attr.attr,
1194 &sensor_dev_attr_pwm4_stop_output.dev_attr.attr,
1195 &sensor_dev_attr_pwm4_max_output.dev_attr.attr,
1196 &sensor_dev_attr_pwm4_step_output.dev_attr.attr,
1197 &sensor_dev_attr_pwm4_target.dev_attr.attr,
1198 &sensor_dev_attr_pwm4_tolerance.dev_attr.attr,
1199
1200 &dev_attr_cpu0_vid.attr,
1201 NULL
1202};
363a12a4 1203
266cd583
DDAG		 1204static const struct attribute_group w83627ehf_group = {
1205 .attrs = w83627ehf_attrs,
1206 .is_visible = w83627ehf_attrs_visible,
1207};
1208
1209static const struct attribute_group *w83627ehf_groups[] = {
1210 &w83627ehf_group,
1211 NULL
1212};
1213
1214/*
1215 * Driver and device management
1216 */
08e7e278 1217
1ea6dd38 1218/* Get the monitoring functions started */
6c931ae1 1219static inline void w83627ehf_init_device(struct w83627ehf_data *data,
bf164c58 1220 enum kinds kind)
08e7e278
JD		 1221{
1222 int i;
da667365 1223 u8 tmp, diode;
08e7e278
JD		 1224
1225 /* Start monitoring is needed */
1ea6dd38 1226 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1227 if (!(tmp & 0x01))
1ea6dd38 1228 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1229 tmp | 0x01);
1230
d36cf32c
GR		 1231 /* Enable temperature sensors if needed */
1232 for (i = 0; i < NUM_REG_TEMP; i++) {
1233 if (!(data->have_temp & (1 << i)))
1234 continue;
ec3e5a16 1235 if (!data->reg_temp_config[i])
d36cf32c 1236 continue;
1ea6dd38 1237 tmp = w83627ehf_read_value(data,
ec3e5a16 1238 data->reg_temp_config[i]);
08e7e278 1239 if (tmp & 0x01)
1ea6dd38 1240 w83627ehf_write_value(data,
ec3e5a16 1241 data->reg_temp_config[i],
08e7e278
JD		 1242 tmp & 0xfe);
1243 }
d3130f0e
JD		 1244
1245 /* Enable VBAT monitoring if needed */
1246 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1247 if (!(tmp & 0x01))
1248 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1249
1250 /* Get thermal sensor types */
bf164c58
JD		 1251 switch (kind) {
1252 case w83627ehf:
1253 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1254 break;
eff7687d
JD		 1255 case w83627uhg:
1256 diode = 0x00;
1257 break;
bf164c58
JD		 1258 default:
1259 diode = 0x70;
1260 }
da667365 1261 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1262 const char *label = NULL;
1263
1264 if (data->temp_label)
1265 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1266
1267 /* Digital source overrides analog type */
bfa02b0d 1268 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1269 data->temp_type[i] = 6;
bfa02b0d 1270 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1271 data->temp_type[i] = 5;
1272 else if ((tmp & (0x02 << i)))
bf164c58 1273 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1274 else
1275 data->temp_type[i] = 4; /* thermistor */
1276 }
08e7e278
JD		 1277}
1278
6c931ae1 1279static void
6ba71de5
JD		 1280w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1281{
1282 int i;
1283
1284 for (i = 0; i < n_temp; i++) {
1285 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1286 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1287 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1288 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1289 }
1290}
1291
6c931ae1 1292static void
03f5de2b
JD		 1293w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1294 struct w83627ehf_data *data)
1295{
39292371 1296 int fan3pin, fan4pin, fan5pin, regval;
03f5de2b 1297
eff7687d
JD		 1298 /* The W83627UHG is simple, only two fan inputs, no config */
1299 if (sio_data->kind == w83627uhg) {
1300 data->has_fan = 0x03; /* fan1 and fan2 */
1301 data->has_fan_min = 0x03;
1302 return;
1303 }
1304
03f5de2b 1305 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3207408a 1306 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
03f5de2b
JD		 1307 fan3pin = 1;
1308 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1309 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
03f5de2b
JD		 1310 } else {
1311 fan3pin = 1;
1312 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1313 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
03f5de2b
JD		 1314 }
1315
03f5de2b
JD		 1316 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
1317 data->has_fan |= (fan3pin << 2);
1318 data->has_fan_min |= (fan3pin << 2);
1319
3207408a
DDAG		 1320 /*
1321 * It looks like fan4 and fan5 pins can be alternatively used
1322 * as fan on/off switches, but fan5 control is write only :/
1323 * We assume that if the serial interface is disabled, designers
1324 * connected fan5 as input unless they are emitting log 1, which
1325 * is not the default.
1326 */
1327 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1328 if ((regval & (1 << 2)) && fan4pin) {
1329 data->has_fan |= (1 << 3);
1330 data->has_fan_min |= (1 << 3);
1331 }
1332 if (!(regval & (1 << 1)) && fan5pin) {
1333 data->has_fan |= (1 << 4);
1334 data->has_fan_min |= (1 << 4);
03f5de2b
JD		 1335 }
1336}
1337
266cd583
DDAG		 1338static umode_t
1339w83627ehf_is_visible(const void *drvdata, enum hwmon_sensor_types type,
1340 u32 attr, int channel)
1341{
1342 const struct w83627ehf_data *data = drvdata;
1343
1344 switch (type) {
1345 case hwmon_temp:
1346 /* channel 0.., name 1.. */
1347 if (!(data->have_temp & (1 << channel)))
1348 return 0;
e61d2392 1349 if (attr == hwmon_temp_input)
266cd583 1350 return 0444;
e61d2392
GR		 1351 if (attr == hwmon_temp_label) {
1352 if (data->temp_label)
1353 return 0444;
1354 return 0;
1355 }
266cd583
DDAG		 1356 if (channel == 2 && data->temp3_val_only)
1357 return 0;
1358 if (attr == hwmon_temp_max) {
1359 if (data->reg_temp_over[channel])
1360 return 0644;
1361 else
1362 return 0;
1363 }
1364 if (attr == hwmon_temp_max_hyst) {
1365 if (data->reg_temp_hyst[channel])
1366 return 0644;
1367 else
1368 return 0;
1369 }
1370 if (channel > 2)
1371 return 0;
1372 if (attr == hwmon_temp_alarm || attr == hwmon_temp_type)
1373 return 0444;
1374 if (attr == hwmon_temp_offset) {
1375 if (data->have_temp_offset & (1 << channel))
1376 return 0644;
1377 else
1378 return 0;
1379 }
1380 break;
1381
1382 case hwmon_fan:
1383 /* channel 0.., name 1.. */
1384 if (!(data->has_fan & (1 << channel)))
1385 return 0;
1386 if (attr == hwmon_fan_input || attr == hwmon_fan_alarm)
1387 return 0444;
1388 if (attr == hwmon_fan_div) {
3207408a 1389 return 0444;
266cd583
DDAG		 1390 }
1391 if (attr == hwmon_fan_min) {
1392 if (data->has_fan_min & (1 << channel))
1393 return 0644;
1394 else
1395 return 0;
1396 }
1397 break;
1398
1399 case hwmon_in:
1400 /* channel 0.., name 0.. */
1401 if (channel >= data->in_num)
1402 return 0;
1403 if (channel == 6 && data->in6_skip)
1404 return 0;
1405 if (attr == hwmon_in_alarm || attr == hwmon_in_input)
1406 return 0444;
1407 if (attr == hwmon_in_min || attr == hwmon_in_max)
1408 return 0644;
1409 break;
1410
1411 case hwmon_pwm:
1412 /* channel 0.., name 1.. */
1413 if (!(data->has_fan & (1 << channel)) ||
1414 channel >= data->pwm_num)
1415 return 0;
1416 if (attr == hwmon_pwm_mode || attr == hwmon_pwm_enable ||
1417 attr == hwmon_pwm_input)
1418 return 0644;
1419 break;
1420
1421 case hwmon_intrusion:
931f397b 1422 return 0644;
266cd583
DDAG		 1423
1424 default: /* Shouldn't happen */
1425 return 0;
1426 }
1427
1428 return 0; /* Shouldn't happen */
1429}
1430
1431static int
1432w83627ehf_do_read_temp(struct w83627ehf_data *data, u32 attr,
1433 int channel, long *val)
1434{
1435 switch (attr) {
1436 case hwmon_temp_input:
1437 *val = LM75_TEMP_FROM_REG(data->temp[channel]);
1438 return 0;
1439 case hwmon_temp_max:
1440 *val = LM75_TEMP_FROM_REG(data->temp_max[channel]);
1441 return 0;
1442 case hwmon_temp_max_hyst:
1443 *val = LM75_TEMP_FROM_REG(data->temp_max_hyst[channel]);
1444 return 0;
1445 case hwmon_temp_offset:
1446 *val = data->temp_offset[channel] * 1000;
1447 return 0;
1448 case hwmon_temp_type:
1449 *val = (int)data->temp_type[channel];
1450 return 0;
1451 case hwmon_temp_alarm:
1452 if (channel < 3) {
1453 int bit[] = { 4, 5, 13 };
1454 *val = (data->alarms >> bit[channel]) & 1;
1455 return 0;
1456 }
1457 break;
1458
1459 default:
1460 break;
1461 }
1462
1463 return -EOPNOTSUPP;
1464}
1465
1466static int
1467w83627ehf_do_read_in(struct w83627ehf_data *data, u32 attr,
1468 int channel, long *val)
1469{
1470 switch (attr) {
1471 case hwmon_in_input:
1472 *val = in_from_reg(data->in[channel], channel, data->scale_in);
1473 return 0;
1474 case hwmon_in_min:
1475 *val = in_from_reg(data->in_min[channel], channel,
1476 data->scale_in);
1477 return 0;
1478 case hwmon_in_max:
1479 *val = in_from_reg(data->in_max[channel], channel,
1480 data->scale_in);
1481 return 0;
1482 case hwmon_in_alarm:
1483 if (channel < 10) {
1484 int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 };
1485 *val = (data->alarms >> bit[channel]) & 1;
1486 return 0;
1487 }
1488 break;
1489 default:
1490 break;
1491 }
1492 return -EOPNOTSUPP;
1493}
1494
1495static int
1496w83627ehf_do_read_fan(struct w83627ehf_data *data, u32 attr,
1497 int channel, long *val)
1498{
1499 switch (attr) {
1500 case hwmon_fan_input:
1501 *val = data->rpm[channel];
1502 return 0;
1503 case hwmon_fan_min:
69595502
DDAG		 1504 *val = fan_from_reg8(data->fan_min[channel],
1505 data->fan_div[channel]);
266cd583
DDAG		 1506 return 0;
1507 case hwmon_fan_div:
1508 *val = div_from_reg(data->fan_div[channel]);
1509 return 0;
1510 case hwmon_fan_alarm:
1511 if (channel < 5) {
1512 int bit[] = { 6, 7, 11, 10, 23 };
1513 *val = (data->alarms >> bit[channel]) & 1;
1514 return 0;
1515 }
1516 break;
1517 default:
1518 break;
1519 }
1520 return -EOPNOTSUPP;
1521}
1522
1523static int
1524w83627ehf_do_read_pwm(struct w83627ehf_data *data, u32 attr,
1525 int channel, long *val)
1526{
1527 switch (attr) {
1528 case hwmon_pwm_input:
1529 *val = data->pwm[channel];
1530 return 0;
1531 case hwmon_pwm_enable:
1532 *val = data->pwm_enable[channel];
1533 return 0;
1534 case hwmon_pwm_mode:
1535 *val = data->pwm_enable[channel];
1536 return 0;
1537 default:
1538 break;
1539 }
1540 return -EOPNOTSUPP;
1541}
1542
1543static int
1544w83627ehf_do_read_intrusion(struct w83627ehf_data *data, u32 attr,
1545 int channel, long *val)
1546{
931f397b 1547 if (attr != hwmon_intrusion_alarm || channel != 0)
266cd583
DDAG		 1548 return -EOPNOTSUPP; /* shouldn't happen */
1549
931f397b 1550 *val = !!(data->caseopen & 0x10);
266cd583
DDAG		 1551 return 0;
1552}
1553
1554static int
1555w83627ehf_read(struct device *dev, enum hwmon_sensor_types type,
1556 u32 attr, int channel, long *val)
1557{
1558 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent);
1559
1560 switch (type) {
1561 case hwmon_fan:
1562 return w83627ehf_do_read_fan(data, attr, channel, val);
1563
1564 case hwmon_in:
1565 return w83627ehf_do_read_in(data, attr, channel, val);
1566
1567 case hwmon_pwm:
1568 return w83627ehf_do_read_pwm(data, attr, channel, val);
1569
1570 case hwmon_temp:
1571 return w83627ehf_do_read_temp(data, attr, channel, val);
1572
1573 case hwmon_intrusion:
1574 return w83627ehf_do_read_intrusion(data, attr, channel, val);
1575
1576 default:
1577 break;
1578 }
1579
1580 return -EOPNOTSUPP;
1581}
1582
1583static int
1584w83627ehf_read_string(struct device *dev, enum hwmon_sensor_types type,
1585 u32 attr, int channel, const char **str)
1586{
1587 struct w83627ehf_data *data = dev_get_drvdata(dev);
1588
1589 switch (type) {
1590 case hwmon_temp:
1591 if (attr == hwmon_temp_label) {
1592 *str = data->temp_label[data->temp_src[channel]];
1593 return 0;
1594 }
1595 break;
1596
1597 default:
1598 break;
1599 }
1600 /* Nothing else should be read as a string */
1601 return -EOPNOTSUPP;
1602}
1603
1604static int
1605w83627ehf_write(struct device *dev, enum hwmon_sensor_types type,
1606 u32 attr, int channel, long val)
1607{
1608 struct w83627ehf_data *data = dev_get_drvdata(dev);
1609
1610 if (type == hwmon_in && attr == hwmon_in_min)
1611 return store_in_min(dev, data, channel, val);
1612 if (type == hwmon_in && attr == hwmon_in_max)
1613 return store_in_max(dev, data, channel, val);
1614
1615 if (type == hwmon_fan && attr == hwmon_fan_min)
1616 return store_fan_min(dev, data, channel, val);
1617
1618 if (type == hwmon_temp && attr == hwmon_temp_max)
1619 return store_temp_max(dev, data, channel, val);
1620 if (type == hwmon_temp && attr == hwmon_temp_max_hyst)
1621 return store_temp_max_hyst(dev, data, channel, val);
1622 if (type == hwmon_temp && attr == hwmon_temp_offset)
1623 return store_temp_offset(dev, data, channel, val);
1624
1625 if (type == hwmon_pwm && attr == hwmon_pwm_mode)
1626 return store_pwm_mode(dev, data, channel, val);
1627 if (type == hwmon_pwm && attr == hwmon_pwm_enable)
1628 return store_pwm_enable(dev, data, channel, val);
1629 if (type == hwmon_pwm && attr == hwmon_pwm_input)
1630 return store_pwm(dev, data, channel, val);
1631
1632 if (type == hwmon_intrusion && attr == hwmon_intrusion_alarm)
1633 return clear_caseopen(dev, data, channel, val);
1634
1635 return -EOPNOTSUPP;
1636}
1637
1638static const struct hwmon_ops w83627ehf_ops = {
1639 .is_visible = w83627ehf_is_visible,
1640 .read = w83627ehf_read,
1641 .read_string = w83627ehf_read_string,
1642 .write = w83627ehf_write,
1643};
1644
1645static const struct hwmon_channel_info *w83627ehf_info[] = {
1646 HWMON_CHANNEL_INFO(fan,
1647 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1648 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1649 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1650 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1651 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN),
1652 HWMON_CHANNEL_INFO(in,
1653 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1654 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1655 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1656 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1657 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1658 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1659 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1660 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1661 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1662 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN),
1663 HWMON_CHANNEL_INFO(pwm,
1664 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1665 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1666 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1667 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE),
1668 HWMON_CHANNEL_INFO(temp,
1669 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1670 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1671 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1672 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1673 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1674 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1675 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1676 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1677 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1678 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1679 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1680 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1681 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1682 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1683 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1684 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1685 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1686 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE),
1687 HWMON_CHANNEL_INFO(intrusion,
266cd583
DDAG		 1688 HWMON_INTRUSION_ALARM),
1689 NULL
1690};
1691
1692static const struct hwmon_chip_info w83627ehf_chip_info = {
1693 .ops = &w83627ehf_ops,
1694 .info = w83627ehf_info,
1695};
1696
6c931ae1 1697static int w83627ehf_probe(struct platform_device *pdev)
08e7e278 1698{
1ea6dd38 1699 struct device *dev = &pdev->dev;
a8b3a3a5 1700 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08e7e278 1701 struct w83627ehf_data *data;
1ea6dd38 1702 struct resource *res;
03f5de2b 1703 u8 en_vrm10;
08e7e278 1704 int i, err = 0;
266cd583 1705 struct device *hwmon_dev;
08e7e278 1706
1ea6dd38
DH		 1707 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1708 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1709 err = -EBUSY;
1ea6dd38
DH		 1710 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1711 (unsigned long)res->start,
1712 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1713 goto exit;
1714 }
1715
32260d94
GR		 1716 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
1717 GFP_KERNEL);
e7e1ca6e 1718 if (!data) {
08e7e278
JD		 1719 err = -ENOMEM;
1720 goto exit_release;
1721 }
08e7e278 1722
1ea6dd38 1723 data->addr = res->start;
9a61bf63 1724 mutex_init(&data->lock);
9a61bf63 1725 mutex_init(&data->update_lock);
1ea6dd38 1726 data->name = w83627ehf_device_names[sio_data->kind];
3300fb4f 1727 data->bank = 0xff; /* Force initial bank selection */
1ea6dd38 1728 platform_set_drvdata(pdev, data);
08e7e278 1729
237c8d2f
GJ		 1730 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1731 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
3207408a 1732 /* 667HG has 3 pwms, and 627UHG has only 2 */
eff7687d
JD		 1733 switch (sio_data->kind) {
1734 default:
1735 data->pwm_num = 4;
1736 break;
1737 case w83667hg:
1738 case w83667hg_b:
eff7687d
JD		 1739 data->pwm_num = 3;
1740 break;
1741 case w83627uhg:
1742 data->pwm_num = 2;
1743 break;
1744 }
08e7e278 1745
6ba71de5 1746 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 1747 data->have_temp = 0x07;
ec3e5a16
GR		 1748
1749 /* Deal with temperature register setup first. */
3207408a 1750 if (sio_data->kind == w83667hg_b) {
d36cf32c
GR		 1751 u8 reg;
1752
6ba71de5
JD		 1753 w83627ehf_set_temp_reg_ehf(data, 4);
1754
ec3e5a16
GR		 1755 /*
1756 * Temperature sources are selected with bank 0, registers 0x49
1757 * and 0x4a.
1758 */
d36cf32c
GR		 1759 reg = w83627ehf_read_value(data, 0x4a);
1760 data->temp_src[0] = reg >> 5;
1761 reg = w83627ehf_read_value(data, 0x49);
1762 data->temp_src[1] = reg & 0x07;
ec3e5a16 1763 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 1764
1765 /*
1766 * W83667HG-B has another temperature register at 0x7e.
1767 * The temperature source is selected with register 0x7d.
1768 * Support it if the source differs from already reported
1769 * sources.
1770 */
1771 reg = w83627ehf_read_value(data, 0x7d);
1772 reg &= 0x07;
1773 if (reg != data->temp_src[0] && reg != data->temp_src[1]
1774 && reg != data->temp_src[2]) {
1775 data->temp_src[3] = reg;
1776 data->have_temp |= 1 << 3;
1777 }
1778
1779 /*
1780 * Chip supports either AUXTIN or VIN3. Try to find out which
1781 * one.
1782 */
1783 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1784 if (data->temp_src[2] == 2 && (reg & 0x01))
1785 data->have_temp &= ~(1 << 2);
1786
1787 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
1788 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
1789 data->in6_skip = 1;
1790
eff7687d 1791 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 1792 data->have_temp_offset = data->have_temp & 0x07;
1793 for (i = 0; i < 3; i++) {
1794 if (data->temp_src[i] > 2)
1795 data->have_temp_offset &= ~(1 << i);
1796 }
eff7687d
JD		 1797 } else if (sio_data->kind == w83627uhg) {
1798 u8 reg;
1799
1800 w83627ehf_set_temp_reg_ehf(data, 3);
1801
1802 /*
aacb6b00 1803 * Temperature sources for temp2 and temp3 are selected with
eff7687d
JD		 1804 * bank 0, registers 0x49 and 0x4a.
1805 */
1806 data->temp_src[0] = 0; /* SYSTIN */
1807 reg = w83627ehf_read_value(data, 0x49) & 0x07;
1808 /* Adjust to have the same mapping as other source registers */
1809 if (reg == 0)
aacb6b00 1810 data->temp_src[1] = 1;
eff7687d 1811 else if (reg >= 2 && reg <= 5)
aacb6b00 1812 data->temp_src[1] = reg + 2;
eff7687d
JD		 1813 else /* should never happen */
1814 data->have_temp &= ~(1 << 1);
1815 reg = w83627ehf_read_value(data, 0x4a);
1816 data->temp_src[2] = reg >> 5;
1817
1818 /*
1819 * Skip temp3 if source is invalid or the same as temp1
1820 * or temp2.
1821 */
1822 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
1823 data->temp_src[2] == data->temp_src[0] ||
1824 ((data->have_temp & (1 << 1)) &&
1825 data->temp_src[2] == data->temp_src[1]))
1826 data->have_temp &= ~(1 << 2);
1827 else
1828 data->temp3_val_only = 1; /* No limit regs */
1829
1830 data->in6_skip = 1; /* No VIN3 */
1831
d36cf32c 1832 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 1833 data->have_temp_offset = data->have_temp & 0x03;
1834 for (i = 0; i < 3; i++) {
1835 if (data->temp_src[i] > 1)
1836 data->have_temp_offset &= ~(1 << i);
1837 }
ec3e5a16 1838 } else {
6ba71de5
JD		 1839 w83627ehf_set_temp_reg_ehf(data, 3);
1840
ec3e5a16 1841 /* Temperature sources are fixed */
6ba71de5
JD		 1842
1843 if (sio_data->kind == w83667hg) {
1844 u8 reg;
1845
1846 /*
1847 * Chip supports either AUXTIN or VIN3. Try to find
1848 * out which one.
1849 */
1850 reg = w83627ehf_read_value(data,
1851 W83627EHF_REG_TEMP_CONFIG[2]);
1852 if (reg & 0x01)
1853 data->have_temp &= ~(1 << 2);
1854 else
1855 data->in6_skip = 1;
ec3e5a16 1856 }
840e191d 1857 data->have_temp_offset = data->have_temp & 0x07;
a157d06d
GJ		 1858 }
1859
3207408a 1860 if (sio_data->kind == w83667hg_b) {
c39aedaf
GR		 1861 data->REG_FAN_MAX_OUTPUT =
1862 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
1863 data->REG_FAN_STEP_OUTPUT =
1864 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
1865 } else {
1866 data->REG_FAN_MAX_OUTPUT =
1867 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
1868 data->REG_FAN_STEP_OUTPUT =
1869 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
1870 }
da2e0255 1871
eff7687d
JD		 1872 /* Setup input voltage scaling factors */
1873 if (sio_data->kind == w83627uhg)
1874 data->scale_in = scale_in_w83627uhg;
1875 else
1876 data->scale_in = scale_in_common;
1877
08e7e278 1878 /* Initialize the chip */
bf164c58 1879 w83627ehf_init_device(data, sio_data->kind);
08e7e278 1880
fc18d6c0 1881 data->vrm = vid_which_vrm();
0d023530
KS		 1882
1883 err = superio_enter(sio_data->sioreg);
1884 if (err)
1885 goto exit_release;
1886
fc18d6c0 1887 /* Read VID value */
3207408a 1888 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
8969e84d
GR		 1889 /*
1890 * W83667HG has different pins for VID input and output, so
1891 * we can get the VID input values directly at logical device D
1892 * 0xe3.
1893 */
237c8d2f
GJ		 1894 superio_select(sio_data->sioreg, W83667HG_LD_VID);
1895 data->vid = superio_inb(sio_data->sioreg, 0xe3);
266cd583 1896 data->have_vid = true;
eff7687d 1897 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 1898 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1899 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
8969e84d
GR		 1900 /*
1901 * Set VID input sensibility if needed. In theory the
1902 * BIOS should have set it, but in practice it's not
1903 * always the case. We only do it for the W83627EHF/EHG
1904 * because the W83627DHG is more complex in this
1905 * respect.
1906 */
237c8d2f
GJ		 1907 if (sio_data->kind == w83627ehf) {
1908 en_vrm10 = superio_inb(sio_data->sioreg,
1909 SIO_REG_EN_VRM10);
1910 if ((en_vrm10 & 0x08) && data->vrm == 90) {
b55f3757
GR		 1911 dev_warn(dev,
1912 "Setting VID input voltage to TTL\n");
237c8d2f
GJ		 1913 superio_outb(sio_data->sioreg,
1914 SIO_REG_EN_VRM10,
1915 en_vrm10 & ~0x08);
1916 } else if (!(en_vrm10 & 0x08)
1917 && data->vrm == 100) {
b55f3757
GR		 1918 dev_warn(dev,
1919 "Setting VID input voltage to VRM10\n");
237c8d2f
GJ		 1920 superio_outb(sio_data->sioreg,
1921 SIO_REG_EN_VRM10,
1922 en_vrm10 | 0x08);
1923 }
1924 }
1925
1926 data->vid = superio_inb(sio_data->sioreg,
1927 SIO_REG_VID_DATA);
1928 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1929 data->vid &= 0x3f;
266cd583 1930 data->have_vid = true;
237c8d2f 1931 } else {
b55f3757
GR		 1932 dev_info(dev,
1933 "VID pins in output mode, CPU VID not available\n");
237c8d2f 1934 }
fc18d6c0
JD		 1935 }
1936
03f5de2b 1937 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 1938
0d023530
KS		 1939 superio_exit(sio_data->sioreg);
1940
ea7be66c 1941 /* Read fan clock dividers immediately */
69595502 1942 w83627ehf_update_fan_div(data);
ec3e5a16 1943
b84bb518 1944 /* Read pwm data to save original values */
69595502 1945 w83627ehf_update_pwm(data);
b84bb518
GR		 1946 for (i = 0; i < data->pwm_num; i++)
1947 data->pwm_enable_orig[i] = data->pwm_enable[i];
1948
266cd583
DDAG		 1949 hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
1950 data->name,
1951 data,
1952 &w83627ehf_chip_info,
1953 w83627ehf_groups);
cf0676fe 1954
266cd583 1955 return PTR_ERR_OR_ZERO(hwmon_dev);
08e7e278 1956
08e7e278 1957exit_release:
1ea6dd38 1958 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1959exit:
1960 return err;
1961}
1962
281dfd0b 1963static int w83627ehf_remove(struct platform_device *pdev)
08e7e278 1964{
1ea6dd38 1965 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1966
1ea6dd38 1967 release_region(data->addr, IOREGION_LENGTH);
08e7e278
JD		 1968
1969 return 0;
1970}
1971
7e630bb5
JD		 1972#ifdef CONFIG_PM
1973static int w83627ehf_suspend(struct device *dev)
1974{
1975 struct w83627ehf_data *data = w83627ehf_update_device(dev);
7e630bb5
JD		 1976
1977 mutex_lock(&data->update_lock);
1978 data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
7e630bb5
JD		 1979 mutex_unlock(&data->update_lock);
1980
1981 return 0;
1982}
1983
1984static int w83627ehf_resume(struct device *dev)
1985{
1986 struct w83627ehf_data *data = dev_get_drvdata(dev);
7e630bb5
JD		 1987 int i;
1988
1989 mutex_lock(&data->update_lock);
1990 data->bank = 0xff; /* Force initial bank selection */
1991
1992 /* Restore limits */
1993 for (i = 0; i < data->in_num; i++) {
1994 if ((i == 6) && data->in6_skip)
1995 continue;
1996
1997 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
1998 data->in_min[i]);
1999 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2000 data->in_max[i]);
2001 }
2002
2003 for (i = 0; i < 5; i++) {
2004 if (!(data->has_fan_min & (1 << i)))
2005 continue;
2006
69595502 2007 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
7e630bb5
JD		 2008 data->fan_min[i]);
2009 }
2010
2011 for (i = 0; i < NUM_REG_TEMP; i++) {
2012 if (!(data->have_temp & (1 << i)))
2013 continue;
2014
2015 if (data->reg_temp_over[i])
2016 w83627ehf_write_temp(data, data->reg_temp_over[i],
2017 data->temp_max[i]);
2018 if (data->reg_temp_hyst[i])
2019 w83627ehf_write_temp(data, data->reg_temp_hyst[i],
2020 data->temp_max_hyst[i]);
45633fb3
JD		 2021 if (i > 2)
2022 continue;
7e630bb5
JD		 2023 if (data->have_temp_offset & (1 << i))
2024 w83627ehf_write_value(data,
2025 W83627EHF_REG_TEMP_OFFSET[i],
2026 data->temp_offset[i]);
2027 }
2028
2029 /* Restore other settings */
2030 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
7e630bb5
JD		 2031
2032 /* Force re-reading all values */
2033 data->valid = 0;
2034 mutex_unlock(&data->update_lock);
2035
2036 return 0;
2037}
2038
2039static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
2040 .suspend = w83627ehf_suspend,
2041 .resume = w83627ehf_resume,
e3b20b3f
HJ		 2042 .freeze = w83627ehf_suspend,
2043 .restore = w83627ehf_resume,
7e630bb5
JD		 2044};
2045
2046#define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
2047#else
2048#define W83627EHF_DEV_PM_OPS NULL
2049#endif /* CONFIG_PM */
2050
1ea6dd38 2051static struct platform_driver w83627ehf_driver = {
cdaf7934 2052 .driver = {
1ea6dd38 2053 .name = DRVNAME,
7e630bb5 2054 .pm = W83627EHF_DEV_PM_OPS,
cdaf7934 2055 },
1ea6dd38 2056 .probe = w83627ehf_probe,
9e5e9b7a 2057 .remove = w83627ehf_remove,
08e7e278
JD		 2058};
2059
1ea6dd38
DH		 2060/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2061static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2062 struct w83627ehf_sio_data *sio_data)
08e7e278 2063{
6f7805a8
UKK		 2064 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2065 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2066 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2067 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2068 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2069 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2070 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
1ea6dd38 2071
08e7e278 2072 u16 val;
1ea6dd38 2073 const char *sio_name;
0d023530 2074 int err;
08e7e278 2075
0d023530
KS		 2076 err = superio_enter(sioaddr);
2077 if (err)
2078 return err;
08e7e278 2079
67b671bc
JD		 2080 if (force_id)
2081 val = force_id;
2082 else
2083 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2084 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2085 switch (val & SIO_ID_MASK) {
657c93b1 2086 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2087 sio_data->kind = w83627ehf;
2088 sio_name = sio_name_W83627EHF;
2089 break;
657c93b1 2090 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2091 sio_data->kind = w83627ehf;
2092 sio_name = sio_name_W83627EHG;
2093 break;
2094 case SIO_W83627DHG_ID:
2095 sio_data->kind = w83627dhg;
2096 sio_name = sio_name_W83627DHG;
657c93b1 2097 break;
c1e48dce
JD		 2098 case SIO_W83627DHG_P_ID:
2099 sio_data->kind = w83627dhg_p;
2100 sio_name = sio_name_W83627DHG_P;
2101 break;
eff7687d
JD		 2102 case SIO_W83627UHG_ID:
2103 sio_data->kind = w83627uhg;
2104 sio_name = sio_name_W83627UHG;
2105 break;
237c8d2f
GJ		 2106 case SIO_W83667HG_ID:
2107 sio_data->kind = w83667hg;
2108 sio_name = sio_name_W83667HG;
2109 break;
c39aedaf
GR		 2110 case SIO_W83667HG_B_ID:
2111 sio_data->kind = w83667hg_b;
2112 sio_name = sio_name_W83667HG_B;
2113 break;
657c93b1 2114 default:
9f66036b 2115 if (val != 0xffff)
abdc6fd1 2116 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2117 superio_exit(sioaddr);
08e7e278
JD		 2118 return -ENODEV;
2119 }
2120
1ea6dd38
DH		 2121 /* We have a known chip, find the HWM I/O address */
2122 superio_select(sioaddr, W83627EHF_LD_HWM);
2123 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2124 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2125 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2126 if (*addr == 0) {
abdc6fd1 2127 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2128 superio_exit(sioaddr);
08e7e278
JD		 2129 return -ENODEV;
2130 }
2131
2132 /* Activate logical device if needed */
1ea6dd38 2133 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2134 if (!(val & 0x01)) {
b55f3757 2135 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
1ea6dd38 2136 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2137 }
1ea6dd38
DH		 2138
2139 superio_exit(sioaddr);
abdc6fd1 2140 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2141 sio_data->sioreg = sioaddr;
08e7e278 2142
08e7e278
JD		 2143 return 0;
2144}
2145
8969e84d
GR		 2146/*
2147 * when Super-I/O functions move to a separate file, the Super-I/O
1ea6dd38
DH		 2148 * bus will manage the lifetime of the device and this module will only keep
2149 * track of the w83627ehf driver. But since we platform_device_alloc(), we
8969e84d
GR		 2150 * must keep track of the device
2151 */
1ea6dd38
DH		 2152static struct platform_device *pdev;
2153
08e7e278
JD		 2154static int __init sensors_w83627ehf_init(void)
2155{
1ea6dd38
DH		 2156 int err;
2157 unsigned short address;
2158 struct resource res;
2159 struct w83627ehf_sio_data sio_data;
2160
8969e84d
GR		 2161 /*
2162 * initialize sio_data->kind and sio_data->sioreg.
1ea6dd38
DH		 2163 *
2164 * when Super-I/O functions move to a separate file, the Super-I/O
2165 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
8969e84d
GR		 2166 * w83627ehf hardware monitor, and call probe()
2167 */
1ea6dd38
DH		 2168 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2169 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2170 return -ENODEV;
2171
1ea6dd38
DH		 2172 err = platform_driver_register(&w83627ehf_driver);
2173 if (err)
2174 goto exit;
2175
e7e1ca6e
GR		 2176 pdev = platform_device_alloc(DRVNAME, address);
2177 if (!pdev) {
1ea6dd38 2178 err = -ENOMEM;
abdc6fd1 2179 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2180 goto exit_unregister;
2181 }
2182
2183 err = platform_device_add_data(pdev, &sio_data,
2184 sizeof(struct w83627ehf_sio_data));
2185 if (err) {
abdc6fd1 2186 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2187 goto exit_device_put;
2188 }
2189
2190 memset(&res, 0, sizeof(res));
2191 res.name = DRVNAME;
2192 res.start = address + IOREGION_OFFSET;
2193 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2194 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2195
2196 err = acpi_check_resource_conflict(&res);
2197 if (err)
18632f84 2198 goto exit_device_put;
b9acb64a 2199
1ea6dd38
DH		 2200 err = platform_device_add_resources(pdev, &res, 1);
2201 if (err) {
abdc6fd1 2202 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2203 goto exit_device_put;
2204 }
2205
2206 /* platform_device_add calls probe() */
2207 err = platform_device_add(pdev);
2208 if (err) {
abdc6fd1 2209 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2210 goto exit_device_put;
2211 }
2212
2213 return 0;
2214
2215exit_device_put:
2216 platform_device_put(pdev);
2217exit_unregister:
2218 platform_driver_unregister(&w83627ehf_driver);
2219exit:
2220 return err;
08e7e278
JD		 2221}
2222
2223static void __exit sensors_w83627ehf_exit(void)
2224{
1ea6dd38
DH		 2225 platform_device_unregister(pdev);
2226 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2227}
2228
7c81c60f 2229MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
08e7e278
JD		 2230MODULE_DESCRIPTION("W83627EHF driver");
2231MODULE_LICENSE("GPL");
2232
2233module_init(sensors_w83627ehf_init);
2234module_exit(sensors_w83627ehf_exit);
Ubuntu Hirsute Linux kernel mirror