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Linux 3.3-rc2
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
e7e1ca6e 3 the Winbond W83627EHF Super-I/O chip
eff7687d 4 Copyright (C) 2005-2011 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
e7e1ca6e
GR		 6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
ec3e5a16 9 Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
08e7e278
JD		 10
11 Shamelessly ripped from the w83627hf driver
12 Copyright (C) 2003 Mark Studebaker
13
14 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 in testing and debugging this driver.
16
8dd2d2ca
JD		 17 This driver also supports the W83627EHG, which is the lead-free
18 version of the W83627EHF.
19
08e7e278
JD		 20 This program is free software; you can redistribute it and/or modify
21 it under the terms of the GNU General Public License as published by
22 the Free Software Foundation; either version 2 of the License, or
23 (at your option) any later version.
24
25 This program is distributed in the hope that it will be useful,
26 but WITHOUT ANY WARRANTY; without even the implied warranty of
27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 GNU General Public License for more details.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33
34
35 Supports the following chips:
36
657c93b1
DH		 37 Chip #vin #fan #pwm #temp chip IDs man ID
38 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
e7e1ca6e 39 0x8860 0xa1
657c93b1 40 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 41 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
eff7687d 42 w83627uhg 8 2 2 2 0xa230 0xc1 0x5ca3
237c8d2f 43 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
d36cf32c 44 w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
ec3e5a16
GR		 45 nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
46 nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
08e7e278
JD		 47*/
48
abdc6fd1
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
08e7e278
JD		 51#include <linux/module.h>
52#include <linux/init.h>
53#include <linux/slab.h>
1ea6dd38
DH		 54#include <linux/jiffies.h>
55#include <linux/platform_device.h>
943b0830 56#include <linux/hwmon.h>
412fec82 57#include <linux/hwmon-sysfs.h>
fc18d6c0 58#include <linux/hwmon-vid.h>
943b0830 59#include <linux/err.h>
9a61bf63 60#include <linux/mutex.h>
b9acb64a 61#include <linux/acpi.h>
6055fae8 62#include <linux/io.h>
08e7e278
JD		 63#include "lm75.h"
64
eff7687d
JD		 65enum kinds {
66 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
67 w83667hg, w83667hg_b, nct6775, nct6776,
68};
08e7e278 69
1ea6dd38 70/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 71static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 72 "w83627ehf",
73 "w83627dhg",
c1e48dce 74 "w83627dhg",
eff7687d 75 "w83627uhg",
237c8d2f 76 "w83667hg",
c39aedaf 77 "w83667hg",
ec3e5a16
GR		 78 "nct6775",
79 "nct6776",
1ea6dd38
DH		 80};
81
67b671bc
JD		 82static unsigned short force_id;
83module_param(force_id, ushort, 0);
84MODULE_PARM_DESC(force_id, "Override the detected device ID");
85
d42e869a
ID		 86static unsigned short fan_debounce;
87module_param(fan_debounce, ushort, 0);
88MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
89
1ea6dd38 90#define DRVNAME "w83627ehf"
08e7e278 91
657c93b1 92/*
1ea6dd38 93 * Super-I/O constants and functions
657c93b1 94 */
08e7e278
JD		 95
96#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 97#define W83667HG_LD_VID 0x0d
08e7e278
JD		 98
99#define SIO_REG_LDSEL 0x07 /* Logical device select */
100#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 101#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 102#define SIO_REG_ENABLE 0x30 /* Logical device enable */
103#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 104#define SIO_REG_VID_CTRL 0xF0 /* VID control */
105#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 106
657c93b1
DH		 107#define SIO_W83627EHF_ID 0x8850
108#define SIO_W83627EHG_ID 0x8860
109#define SIO_W83627DHG_ID 0xa020
c1e48dce 110#define SIO_W83627DHG_P_ID 0xb070
eff7687d 111#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 112#define SIO_W83667HG_ID 0xa510
c39aedaf 113#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 114#define SIO_NCT6775_ID 0xb470
115#define SIO_NCT6776_ID 0xc330
657c93b1 116#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 117
118static inline void
1ea6dd38 119superio_outb(int ioreg, int reg, int val)
08e7e278 120{
1ea6dd38
DH		 121 outb(reg, ioreg);
122 outb(val, ioreg + 1);
08e7e278
JD		 123}
124
125static inline int
1ea6dd38 126superio_inb(int ioreg, int reg)
08e7e278 127{
1ea6dd38
DH		 128 outb(reg, ioreg);
129 return inb(ioreg + 1);
08e7e278
JD		 130}
131
132static inline void
1ea6dd38 133superio_select(int ioreg, int ld)
08e7e278 134{
1ea6dd38
DH		 135 outb(SIO_REG_LDSEL, ioreg);
136 outb(ld, ioreg + 1);
08e7e278
JD		 137}
138
139static inline void
1ea6dd38 140superio_enter(int ioreg)
08e7e278 141{
1ea6dd38
DH		 142 outb(0x87, ioreg);
143 outb(0x87, ioreg);
08e7e278
JD		 144}
145
146static inline void
1ea6dd38 147superio_exit(int ioreg)
08e7e278 148{
022b75a3 149 outb(0xaa, ioreg);
1ea6dd38
DH		 150 outb(0x02, ioreg);
151 outb(0x02, ioreg + 1);
08e7e278
JD		 152}
153
154/*
155 * ISA constants
156 */
157
e7e1ca6e 158#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 159#define IOREGION_OFFSET 5
160#define IOREGION_LENGTH 2
1ea6dd38
DH		 161#define ADDR_REG_OFFSET 0
162#define DATA_REG_OFFSET 1
08e7e278
JD		 163
164#define W83627EHF_REG_BANK 0x4E
165#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 166
167/* Not currently used:
168 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
169 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
170 * REG_MAN_ID is at port 0x4f
171 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 172
173static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
174static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
175
cf0676fe
RM		 176/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
177#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
178 (0x554 + (((nr) - 7) * 2)))
179#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
180 (0x555 + (((nr) - 7) * 2)))
181#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
182 (0x550 + (nr) - 7))
183
d36cf32c
GR		 184static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
185static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
186static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
187static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 188
189/* Fan clock dividers are spread over the following five registers */
190#define W83627EHF_REG_FANDIV1 0x47
191#define W83627EHF_REG_FANDIV2 0x4B
192#define W83627EHF_REG_VBAT 0x5D
193#define W83627EHF_REG_DIODE 0x59
194#define W83627EHF_REG_SMI_OVT 0x4C
195
ec3e5a16
GR		 196/* NCT6775F has its own fan divider registers */
197#define NCT6775_REG_FANDIV1 0x506
198#define NCT6775_REG_FANDIV2 0x507
d42e869a 199#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 200
a4589dbb
JD		 201#define W83627EHF_REG_ALARM1 0x459
202#define W83627EHF_REG_ALARM2 0x45A
203#define W83627EHF_REG_ALARM3 0x45B
204
363a12a4
DA		 205#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
206#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
207
08c79950 208/* SmartFan registers */
41e9a062
DB		 209#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
210#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
211
08c79950
RM		 212/* DC or PWM output fan configuration */
213static const u8 W83627EHF_REG_PWM_ENABLE[] = {
214 0x04, /* SYS FAN0 output mode and PWM mode */
215 0x04, /* CPU FAN0 output mode and PWM mode */
216 0x12, /* AUX FAN mode */
41e9a062 217 0x62, /* CPU FAN1 mode */
08c79950
RM		 218};
219
220static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
221static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
222
223/* FAN Duty Cycle, be used to control */
279af1a9
GR		 224static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
225static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 226static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
227
08c79950 228/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 229static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
230static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
231static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 232
279af1a9 233static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 234 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 235static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 236 = { 0xff, 0x68, 0xff, 0x6a };
237
279af1a9
GR		 238static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
239static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
240 = { 0x68, 0x6a, 0x6c };
08c79950 241
ec3e5a16
GR		 242static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
243static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
244static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
245static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
246static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
247static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
248static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
249static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 250static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 251static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
252
253static const u16 NCT6775_REG_TEMP[]
254 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
255static const u16 NCT6775_REG_TEMP_CONFIG[]
256 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
257static const u16 NCT6775_REG_TEMP_HYST[]
258 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
259static const u16 NCT6775_REG_TEMP_OVER[]
260 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
261static const u16 NCT6775_REG_TEMP_SOURCE[]
262 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
263
d36cf32c
GR		 264static const char *const w83667hg_b_temp_label[] = {
265 "SYSTIN",
266 "CPUTIN",
267 "AUXTIN",
268 "AMDTSI",
269 "PECI Agent 1",
270 "PECI Agent 2",
271 "PECI Agent 3",
272 "PECI Agent 4"
273};
274
ec3e5a16
GR		 275static const char *const nct6775_temp_label[] = {
276 "",
277 "SYSTIN",
278 "CPUTIN",
279 "AUXTIN",
280 "AMD SB-TSI",
281 "PECI Agent 0",
282 "PECI Agent 1",
283 "PECI Agent 2",
284 "PECI Agent 3",
285 "PECI Agent 4",
286 "PECI Agent 5",
287 "PECI Agent 6",
288 "PECI Agent 7",
289 "PCH_CHIP_CPU_MAX_TEMP",
290 "PCH_CHIP_TEMP",
291 "PCH_CPU_TEMP",
292 "PCH_MCH_TEMP",
293 "PCH_DIM0_TEMP",
294 "PCH_DIM1_TEMP",
295 "PCH_DIM2_TEMP",
296 "PCH_DIM3_TEMP"
297};
298
299static const char *const nct6776_temp_label[] = {
300 "",
301 "SYSTIN",
302 "CPUTIN",
303 "AUXTIN",
304 "SMBUSMASTER 0",
305 "SMBUSMASTER 1",
306 "SMBUSMASTER 2",
307 "SMBUSMASTER 3",
308 "SMBUSMASTER 4",
309 "SMBUSMASTER 5",
310 "SMBUSMASTER 6",
311 "SMBUSMASTER 7",
312 "PECI Agent 0",
313 "PECI Agent 1",
314 "PCH_CHIP_CPU_MAX_TEMP",
315 "PCH_CHIP_TEMP",
316 "PCH_CPU_TEMP",
317 "PCH_MCH_TEMP",
318 "PCH_DIM0_TEMP",
319 "PCH_DIM1_TEMP",
320 "PCH_DIM2_TEMP",
321 "PCH_DIM3_TEMP",
322 "BYTE_TEMP"
323};
324
325#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 326
17296feb 327static int is_word_sized(u16 reg)
bce26c58 328{
ec3e5a16 329 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 330 || (reg & 0xff00) == 0x200)
331 && ((reg & 0x00ff) == 0x50
332 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 333 || (reg & 0x00ff) == 0x55))
334 || (reg & 0xfff0) == 0x630
335 || reg == 0x640 || reg == 0x642
336 || ((reg & 0xfff0) == 0x650
337 && (reg & 0x000f) >= 0x06)
338 || reg == 0x73 || reg == 0x75 || reg == 0x77
339 );
bce26c58
GR		 340}
341
08e7e278
JD		 342/*
343 * Conversions
344 */
345
08c79950
RM		 346/* 1 is PWM mode, output in ms */
347static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
348{
349 return mode ? 100 * reg : 400 * reg;
350}
351
352static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
353{
354 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
355 (msec + 200) / 400), 1, 255);
356}
357
26bc440e 358static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 359{
26bc440e 360 if (reg == 0 || reg == 255)
08e7e278 361 return 0;
26bc440e
GR		 362 return 1350000U / (reg << divreg);
363}
364
365static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
366{
367 if ((reg & 0xff1f) == 0xff1f)
368 return 0;
369
370 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
371
372 if (reg == 0)
373 return 0;
374
375 return 1350000U / reg;
376}
377
378static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
379{
380 if (reg == 0 || reg == 0xffff)
381 return 0;
382
383 /*
384 * Even though the registers are 16 bit wide, the fan divisor
385 * still applies.
386 */
387 return 1350000U / (reg << divreg);
08e7e278
JD		 388}
389
390static inline unsigned int
391div_from_reg(u8 reg)
392{
393 return 1 << reg;
394}
395
eff7687d
JD		 396/* Some of the voltage inputs have internal scaling, the tables below
397 * contain 8 (the ADC LSB in mV) * scaling factor * 100 */
398static const u16 scale_in_common[10] = {
399 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
400};
401static const u16 scale_in_w83627uhg[9] = {
402 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
403};
cf0676fe 404
eff7687d 405static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 406{
eff7687d 407 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 408}
409
eff7687d 410static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 411{
eff7687d 412 return SENSORS_LIMIT(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0,
e7e1ca6e 413 255);
cf0676fe
RM		 414}
415
08e7e278
JD		 416/*
417 * Data structures and manipulation thereof
418 */
419
420struct w83627ehf_data {
1ea6dd38
DH		 421 int addr; /* IO base of hw monitor block */
422 const char *name;
423
1beeffe4 424 struct device *hwmon_dev;
9a61bf63 425 struct mutex lock;
08e7e278 426
ec3e5a16
GR		 427 u16 reg_temp[NUM_REG_TEMP];
428 u16 reg_temp_over[NUM_REG_TEMP];
429 u16 reg_temp_hyst[NUM_REG_TEMP];
430 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 431 u8 temp_src[NUM_REG_TEMP];
432 const char * const *temp_label;
433
279af1a9
GR		 434 const u16 *REG_PWM;
435 const u16 *REG_TARGET;
436 const u16 *REG_FAN;
437 const u16 *REG_FAN_MIN;
438 const u16 *REG_FAN_START_OUTPUT;
439 const u16 *REG_FAN_STOP_OUTPUT;
440 const u16 *REG_FAN_STOP_TIME;
441 const u16 *REG_FAN_MAX_OUTPUT;
442 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 443 const u16 *scale_in;
da2e0255 444
26bc440e
GR		 445 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
446 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
447
9a61bf63 448 struct mutex update_lock;
08e7e278
JD		 449 char valid; /* !=0 if following fields are valid */
450 unsigned long last_updated; /* In jiffies */
451
452 /* Register values */
83cc8985 453 u8 bank; /* current register bank */
1ea6dd38 454 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 455 u8 in[10]; /* Register value */
456 u8 in_max[10]; /* Register value */
457 u8 in_min[10]; /* Register value */
3382a918 458 unsigned int rpm[5];
ec3e5a16 459 u16 fan_min[5];
08e7e278
JD		 460 u8 fan_div[5];
461 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 462 u8 has_fan_min; /* some fans don't have min register */
26bc440e 463 bool has_fan_div;
da667365 464 u8 temp_type[3];
ec3e5a16
GR		 465 s16 temp[9];
466 s16 temp_max[9];
467 s16 temp_max_hyst[9];
a4589dbb 468 u32 alarms;
363a12a4 469 u8 caseopen;
08c79950
RM		 470
471 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
472 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 473 2->thermal cruise mode (also called SmartFan I)
474 3->fan speed cruise mode
e7e1ca6e 475 4->variable thermal cruise (also called
b84bb518
GR		 476 SmartFan III)
477 5->enhanced variable thermal cruise (also called
478 SmartFan IV) */
479 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 480 u8 pwm_num; /* number of pwm */
08c79950
RM		 481 u8 pwm[4];
482 u8 target_temp[4];
483 u8 tolerance[4];
484
41e9a062
DB		 485 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
486 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
487 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
488 u8 fan_max_output[4]; /* maximum fan speed */
489 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 490
491 u8 vid;
492 u8 vrm;
a157d06d 493
ec3e5a16 494 u16 have_temp;
eff7687d
JD		 495 u8 in6_skip:1;
496 u8 temp3_val_only:1;
08e7e278
JD		 497};
498
1ea6dd38
DH		 499struct w83627ehf_sio_data {
500 int sioreg;
501 enum kinds kind;
502};
503
83cc8985
GR		 504/*
505 * On older chips, only registers 0x50-0x5f are banked.
506 * On more recent chips, all registers are banked.
507 * Assume that is the case and set the bank number for each access.
508 * Cache the bank number so it only needs to be set if it changes.
509 */
1ea6dd38 510static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 511{
83cc8985
GR		 512 u8 bank = reg >> 8;
513 if (data->bank != bank) {
1ea6dd38 514 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 515 outb_p(bank, data->addr + DATA_REG_OFFSET);
516 data->bank = bank;
08e7e278
JD		 517 }
518}
519
1ea6dd38 520static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 521{
08e7e278
JD		 522 int res, word_sized = is_word_sized(reg);
523
9a61bf63 524 mutex_lock(&data->lock);
08e7e278 525
1ea6dd38
DH		 526 w83627ehf_set_bank(data, reg);
527 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
528 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 529 if (word_sized) {
530 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 531 data->addr + ADDR_REG_OFFSET);
532 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 533 }
08e7e278 534
9a61bf63 535 mutex_unlock(&data->lock);
08e7e278
JD		 536 return res;
537}
538
e7e1ca6e
GR		 539static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
540 u16 value)
08e7e278 541{
08e7e278
JD		 542 int word_sized = is_word_sized(reg);
543
9a61bf63 544 mutex_lock(&data->lock);
08e7e278 545
1ea6dd38
DH		 546 w83627ehf_set_bank(data, reg);
547 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 548 if (word_sized) {
1ea6dd38 549 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 550 outb_p((reg & 0xff) + 1,
1ea6dd38 551 data->addr + ADDR_REG_OFFSET);
08e7e278 552 }
1ea6dd38 553 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 554
9a61bf63 555 mutex_unlock(&data->lock);
08e7e278
JD		 556 return 0;
557}
558
c5794cfa
JD		 559/* We left-align 8-bit temperature values to make the code simpler */
560static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
561{
562 u16 res;
563
564 res = w83627ehf_read_value(data, reg);
565 if (!is_word_sized(reg))
566 res <<= 8;
567
568 return res;
569}
570
571static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
572 u16 value)
573{
574 if (!is_word_sized(reg))
575 value >>= 8;
576 return w83627ehf_write_value(data, reg, value);
577}
578
ec3e5a16
GR		 579/* This function assumes that the caller holds data->update_lock */
580static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
581{
582 u8 reg;
583
584 switch (nr) {
585 case 0:
586 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
587 | (data->fan_div[0] & 0x7);
588 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
589 break;
590 case 1:
591 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
592 | ((data->fan_div[1] << 4) & 0x70);
593 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
594 case 2:
595 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
596 | (data->fan_div[2] & 0x7);
597 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
598 break;
599 case 3:
600 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
601 | ((data->fan_div[3] << 4) & 0x70);
602 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
603 break;
604 }
605}
606
08e7e278 607/* This function assumes that the caller holds data->update_lock */
1ea6dd38 608static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 609{
08e7e278
JD		 610 u8 reg;
611
612 switch (nr) {
613 case 0:
1ea6dd38 614 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 615 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 616 /* fan5 input control bit is write only, compute the value */
617 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 618 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
619 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 620 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 621 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 622 break;
623 case 1:
1ea6dd38 624 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 625 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 626 /* fan5 input control bit is write only, compute the value */
627 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 628 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
629 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 630 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 631 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 632 break;
633 case 2:
1ea6dd38 634 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 635 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 636 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
637 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 638 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 639 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 640 break;
641 case 3:
1ea6dd38 642 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 643 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 644 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
645 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 646 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 647 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 648 break;
649 case 4:
1ea6dd38 650 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 651 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 652 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 653 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 654 break;
655 }
656}
657
ec3e5a16
GR		 658static void w83627ehf_write_fan_div_common(struct device *dev,
659 struct w83627ehf_data *data, int nr)
660{
661 struct w83627ehf_sio_data *sio_data = dev->platform_data;
662
663 if (sio_data->kind == nct6776)
664 ; /* no dividers, do nothing */
665 else if (sio_data->kind == nct6775)
666 nct6775_write_fan_div(data, nr);
667 else
668 w83627ehf_write_fan_div(data, nr);
669}
670
671static void nct6775_update_fan_div(struct w83627ehf_data *data)
672{
673 u8 i;
674
675 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
676 data->fan_div[0] = i & 0x7;
677 data->fan_div[1] = (i & 0x70) >> 4;
678 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
679 data->fan_div[2] = i & 0x7;
680 if (data->has_fan & (1<<3))
681 data->fan_div[3] = (i & 0x70) >> 4;
682}
683
ea7be66c
MH		 684static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
685{
686 int i;
687
688 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
689 data->fan_div[0] = (i >> 4) & 0x03;
690 data->fan_div[1] = (i >> 6) & 0x03;
691 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
692 data->fan_div[2] = (i >> 6) & 0x03;
693 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
694 data->fan_div[0] |= (i >> 3) & 0x04;
695 data->fan_div[1] |= (i >> 4) & 0x04;
696 data->fan_div[2] |= (i >> 5) & 0x04;
697 if (data->has_fan & ((1 << 3) | (1 << 4))) {
698 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
699 data->fan_div[3] = i & 0x03;
700 data->fan_div[4] = ((i >> 2) & 0x03)
701 | ((i >> 5) & 0x04);
702 }
703 if (data->has_fan & (1 << 3)) {
704 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
705 data->fan_div[3] |= (i >> 5) & 0x04;
706 }
707}
708
ec3e5a16
GR		 709static void w83627ehf_update_fan_div_common(struct device *dev,
710 struct w83627ehf_data *data)
711{
712 struct w83627ehf_sio_data *sio_data = dev->platform_data;
713
714 if (sio_data->kind == nct6776)
715 ; /* no dividers, do nothing */
716 else if (sio_data->kind == nct6775)
717 nct6775_update_fan_div(data);
718 else
719 w83627ehf_update_fan_div(data);
720}
721
722static void nct6775_update_pwm(struct w83627ehf_data *data)
723{
724 int i;
725 int pwmcfg, fanmodecfg;
726
727 for (i = 0; i < data->pwm_num; i++) {
728 pwmcfg = w83627ehf_read_value(data,
729 W83627EHF_REG_PWM_ENABLE[i]);
730 fanmodecfg = w83627ehf_read_value(data,
731 NCT6775_REG_FAN_MODE[i]);
732 data->pwm_mode[i] =
733 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
734 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
735 data->tolerance[i] = fanmodecfg & 0x0f;
736 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
737 }
738}
739
740static void w83627ehf_update_pwm(struct w83627ehf_data *data)
741{
742 int i;
743 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
744
745 for (i = 0; i < data->pwm_num; i++) {
746 if (!(data->has_fan & (1 << i)))
747 continue;
748
749 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
750 if (i != 1) {
751 pwmcfg = w83627ehf_read_value(data,
752 W83627EHF_REG_PWM_ENABLE[i]);
753 tolerance = w83627ehf_read_value(data,
754 W83627EHF_REG_TOLERANCE[i]);
755 }
756 data->pwm_mode[i] =
757 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
758 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
759 & 3) + 1;
760 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
761
762 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
763 }
764}
765
766static void w83627ehf_update_pwm_common(struct device *dev,
767 struct w83627ehf_data *data)
768{
769 struct w83627ehf_sio_data *sio_data = dev->platform_data;
770
771 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
772 nct6775_update_pwm(data);
773 else
774 w83627ehf_update_pwm(data);
775}
776
08e7e278
JD		 777static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
778{
1ea6dd38 779 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16
GR		 780 struct w83627ehf_sio_data *sio_data = dev->platform_data;
781
08e7e278
JD		 782 int i;
783
9a61bf63 784 mutex_lock(&data->update_lock);
08e7e278 785
6b3e4645 786 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 787 || !data->valid) {
788 /* Fan clock dividers */
ec3e5a16 789 w83627ehf_update_fan_div_common(dev, data);
08e7e278 790
cf0676fe 791 /* Measured voltages and limits */
1ea6dd38 792 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 793 if ((i == 6) && data->in6_skip)
794 continue;
795
1ea6dd38 796 data->in[i] = w83627ehf_read_value(data,
cf0676fe 797 W83627EHF_REG_IN(i));
1ea6dd38 798 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 799 W83627EHF_REG_IN_MIN(i));
1ea6dd38 800 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 801 W83627EHF_REG_IN_MAX(i));
802 }
803
08e7e278
JD		 804 /* Measured fan speeds and limits */
805 for (i = 0; i < 5; i++) {
3382a918
GR		 806 u16 reg;
807
08e7e278
JD		 808 if (!(data->has_fan & (1 << i)))
809 continue;
810
3382a918
GR		 811 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
812 data->rpm[i] = data->fan_from_reg(reg,
813 data->fan_div[i]);
ec3e5a16
GR		 814
815 if (data->has_fan_min & (1 << i))
816 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 817 data->REG_FAN_MIN[i]);
08e7e278
JD		 818
819 /* If we failed to measure the fan speed and clock
820 divider can be increased, let's try that for next
821 time */
26bc440e 822 if (data->has_fan_div
3382a918
GR		 823 && (reg >= 0xff || (sio_data->kind == nct6775
824 && reg == 0x00))
ec3e5a16 825 && data->fan_div[i] < 0x07) {
e7e1ca6e 826 dev_dbg(dev, "Increasing fan%d "
08e7e278 827 "clock divider from %u to %u\n",
33725ad3 828 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 829 div_from_reg(data->fan_div[i] + 1));
830 data->fan_div[i]++;
ec3e5a16 831 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 832 /* Preserve min limit if possible */
ec3e5a16
GR		 833 if ((data->has_fan_min & (1 << i))
834 && data->fan_min[i] >= 2
08e7e278 835 && data->fan_min[i] != 255)
1ea6dd38 836 w83627ehf_write_value(data,
279af1a9 837 data->REG_FAN_MIN[i],
08e7e278
JD		 838 (data->fan_min[i] /= 2));
839 }
840 }
841
ec3e5a16
GR		 842 w83627ehf_update_pwm_common(dev, data);
843
da2e0255
GR		 844 for (i = 0; i < data->pwm_num; i++) {
845 if (!(data->has_fan & (1 << i)))
846 continue;
847
ec3e5a16
GR		 848 data->fan_start_output[i] =
849 w83627ehf_read_value(data,
850 data->REG_FAN_START_OUTPUT[i]);
851 data->fan_stop_output[i] =
852 w83627ehf_read_value(data,
853 data->REG_FAN_STOP_OUTPUT[i]);
854 data->fan_stop_time[i] =
855 w83627ehf_read_value(data,
856 data->REG_FAN_STOP_TIME[i]);
857
858 if (data->REG_FAN_MAX_OUTPUT &&
859 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 860 data->fan_max_output[i] =
861 w83627ehf_read_value(data,
ec3e5a16 862 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 863
ec3e5a16
GR		 864 if (data->REG_FAN_STEP_OUTPUT &&
865 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 866 data->fan_step_output[i] =
867 w83627ehf_read_value(data,
ec3e5a16 868 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 869
08c79950 870 data->target_temp[i] =
1ea6dd38 871 w83627ehf_read_value(data,
279af1a9 872 data->REG_TARGET[i]) &
08c79950 873 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 874 }
875
08e7e278 876 /* Measured temperatures and limits */
d36cf32c
GR		 877 for (i = 0; i < NUM_REG_TEMP; i++) {
878 if (!(data->have_temp & (1 << i)))
879 continue;
c5794cfa 880 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 881 data->reg_temp[i]);
882 if (data->reg_temp_over[i])
883 data->temp_max[i]
c5794cfa 884 = w83627ehf_read_temp(data,
ec3e5a16
GR		 885 data->reg_temp_over[i]);
886 if (data->reg_temp_hyst[i])
887 data->temp_max_hyst[i]
c5794cfa 888 = w83627ehf_read_temp(data,
ec3e5a16 889 data->reg_temp_hyst[i]);
08e7e278
JD		 890 }
891
1ea6dd38 892 data->alarms = w83627ehf_read_value(data,
a4589dbb 893 W83627EHF_REG_ALARM1) |
1ea6dd38 894 (w83627ehf_read_value(data,
a4589dbb 895 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 896 (w83627ehf_read_value(data,
a4589dbb
JD		 897 W83627EHF_REG_ALARM3) << 16);
898
363a12a4
DA		 899 data->caseopen = w83627ehf_read_value(data,
900 W83627EHF_REG_CASEOPEN_DET);
901
08e7e278
JD		 902 data->last_updated = jiffies;
903 data->valid = 1;
904 }
905
9a61bf63 906 mutex_unlock(&data->update_lock);
08e7e278
JD		 907 return data;
908}
909
910/*
911 * Sysfs callback functions
912 */
cf0676fe
RM		 913#define show_in_reg(reg) \
914static ssize_t \
915show_##reg(struct device *dev, struct device_attribute *attr, \
916 char *buf) \
917{ \
918 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 919 struct sensor_device_attribute *sensor_attr = \
920 to_sensor_dev_attr(attr); \
cf0676fe 921 int nr = sensor_attr->index; \
eff7687d
JD		 922 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
923 data->scale_in)); \
cf0676fe
RM		 924}
925show_in_reg(in)
926show_in_reg(in_min)
927show_in_reg(in_max)
928
929#define store_in_reg(REG, reg) \
930static ssize_t \
e7e1ca6e
GR		 931store_in_##reg(struct device *dev, struct device_attribute *attr, \
932 const char *buf, size_t count) \
cf0676fe 933{ \
1ea6dd38 934 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 935 struct sensor_device_attribute *sensor_attr = \
936 to_sensor_dev_attr(attr); \
cf0676fe 937 int nr = sensor_attr->index; \
bce26c58
GR		 938 unsigned long val; \
939 int err; \
179c4fdb 940 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 941 if (err < 0) \
942 return err; \
cf0676fe 943 mutex_lock(&data->update_lock); \
eff7687d 944 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
1ea6dd38 945 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 946 data->in_##reg[nr]); \
947 mutex_unlock(&data->update_lock); \
948 return count; \
949}
950
951store_in_reg(MIN, min)
952store_in_reg(MAX, max)
953
e7e1ca6e
GR		 954static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
955 char *buf)
a4589dbb
JD		 956{
957 struct w83627ehf_data *data = w83627ehf_update_device(dev);
958 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
959 int nr = sensor_attr->index;
960 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
961}
962
cf0676fe
RM		 963static struct sensor_device_attribute sda_in_input[] = {
964 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
965 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
966 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
967 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
968 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
969 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
970 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
971 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
972 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
973 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
974};
975
a4589dbb
JD		 976static struct sensor_device_attribute sda_in_alarm[] = {
977 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
978 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
979 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
980 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
981 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
982 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
983 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
984 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
985 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
986 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
987};
988
cf0676fe 989static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 990 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
991 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
992 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
993 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
994 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
995 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
996 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
997 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
998 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
999 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 1000};
1001
1002static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 1003 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1004 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1005 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1006 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1007 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1008 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1009 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1010 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1011 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1012 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 1013};
1014
ec3e5a16
GR		 1015static ssize_t
1016show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1017{
1018 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1019 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1020 int nr = sensor_attr->index;
3382a918 1021 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 1022}
1023
1024static ssize_t
1025show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1026{
1027 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1028 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1029 int nr = sensor_attr->index;
1030 return sprintf(buf, "%d\n",
26bc440e
GR		 1031 data->fan_from_reg_min(data->fan_min[nr],
1032 data->fan_div[nr]));
08e7e278 1033}
08e7e278
JD		 1034
1035static ssize_t
412fec82
YM		 1036show_fan_div(struct device *dev, struct device_attribute *attr,
1037 char *buf)
08e7e278
JD		 1038{
1039 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1040 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1041 int nr = sensor_attr->index;
1042 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1043}
1044
1045static ssize_t
412fec82
YM		 1046store_fan_min(struct device *dev, struct device_attribute *attr,
1047 const char *buf, size_t count)
08e7e278 1048{
1ea6dd38 1049 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1050 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1051 int nr = sensor_attr->index;
bce26c58
GR		 1052 unsigned long val;
1053 int err;
08e7e278
JD		 1054 unsigned int reg;
1055 u8 new_div;
1056
179c4fdb 1057 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1058 if (err < 0)
1059 return err;
1060
9a61bf63 1061 mutex_lock(&data->update_lock);
26bc440e
GR		 1062 if (!data->has_fan_div) {
1063 /*
1064 * Only NCT6776F for now, so we know that this is a 13 bit
1065 * register
1066 */
ec3e5a16
GR		 1067 if (!val) {
1068 val = 0xff1f;
1069 } else {
1070 if (val > 1350000U)
1071 val = 135000U;
1072 val = 1350000U / val;
1073 val = (val & 0x1f) | ((val << 3) & 0xff00);
1074 }
1075 data->fan_min[nr] = val;
1076 goto done; /* Leave fan divider alone */
1077 }
08e7e278
JD		 1078 if (!val) {
1079 /* No min limit, alarm disabled */
1080 data->fan_min[nr] = 255;
1081 new_div = data->fan_div[nr]; /* No change */
1082 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1083 } else if ((reg = 1350000U / val) >= 128 * 255) {
1084 /* Speed below this value cannot possibly be represented,
1085 even with the highest divider (128) */
1086 data->fan_min[nr] = 254;
1087 new_div = 7; /* 128 == (1 << 7) */
bce26c58 1088 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
ec3e5a16 1089 "minimum\n", nr + 1, val,
26bc440e 1090 data->fan_from_reg_min(254, 7));
08e7e278
JD		 1091 } else if (!reg) {
1092 /* Speed above this value cannot possibly be represented,
1093 even with the lowest divider (1) */
1094 data->fan_min[nr] = 1;
1095 new_div = 0; /* 1 == (1 << 0) */
bce26c58 1096 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
ec3e5a16 1097 "maximum\n", nr + 1, val,
26bc440e 1098 data->fan_from_reg_min(1, 0));
08e7e278
JD		 1099 } else {
1100 /* Automatically pick the best divider, i.e. the one such
1101 that the min limit will correspond to a register value
1102 in the 96..192 range */
1103 new_div = 0;
1104 while (reg > 192 && new_div < 7) {
1105 reg >>= 1;
1106 new_div++;
1107 }
1108 data->fan_min[nr] = reg;
1109 }
1110
1111 /* Write both the fan clock divider (if it changed) and the new
1112 fan min (unconditionally) */
1113 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1114 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1115 nr + 1, div_from_reg(data->fan_div[nr]),
1116 div_from_reg(new_div));
1117 data->fan_div[nr] = new_div;
ec3e5a16 1118 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1119 /* Give the chip time to sample a new speed value */
1120 data->last_updated = jiffies;
08e7e278 1121 }
ec3e5a16 1122done:
279af1a9 1123 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1124 data->fan_min[nr]);
9a61bf63 1125 mutex_unlock(&data->update_lock);
08e7e278
JD		 1126
1127 return count;
1128}
1129
412fec82
YM		 1130static struct sensor_device_attribute sda_fan_input[] = {
1131 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1132 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1133 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1134 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1135 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1136};
08e7e278 1137
a4589dbb
JD		 1138static struct sensor_device_attribute sda_fan_alarm[] = {
1139 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1140 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1141 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1142 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1143 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1144};
1145
412fec82
YM		 1146static struct sensor_device_attribute sda_fan_min[] = {
1147 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1148 store_fan_min, 0),
1149 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1150 store_fan_min, 1),
1151 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1152 store_fan_min, 2),
1153 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1154 store_fan_min, 3),
1155 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1156 store_fan_min, 4),
1157};
08e7e278 1158
412fec82
YM		 1159static struct sensor_device_attribute sda_fan_div[] = {
1160 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1161 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1162 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1163 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1164 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1165};
1166
d36cf32c
GR		 1167static ssize_t
1168show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1169{
1170 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1171 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1172 int nr = sensor_attr->index;
1173 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1174}
1175
ec3e5a16 1176#define show_temp_reg(addr, reg) \
08e7e278 1177static ssize_t \
412fec82
YM		 1178show_##reg(struct device *dev, struct device_attribute *attr, \
1179 char *buf) \
08e7e278
JD		 1180{ \
1181 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1182 struct sensor_device_attribute *sensor_attr = \
1183 to_sensor_dev_attr(attr); \
412fec82 1184 int nr = sensor_attr->index; \
c5794cfa 1185 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
08e7e278 1186}
ec3e5a16
GR		 1187show_temp_reg(reg_temp, temp);
1188show_temp_reg(reg_temp_over, temp_max);
1189show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1190
ec3e5a16 1191#define store_temp_reg(addr, reg) \
08e7e278 1192static ssize_t \
412fec82
YM		 1193store_##reg(struct device *dev, struct device_attribute *attr, \
1194 const char *buf, size_t count) \
08e7e278 1195{ \
1ea6dd38 1196 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1197 struct sensor_device_attribute *sensor_attr = \
1198 to_sensor_dev_attr(attr); \
412fec82 1199 int nr = sensor_attr->index; \
bce26c58
GR		 1200 int err; \
1201 long val; \
179c4fdb 1202 err = kstrtol(buf, 10, &val); \
bce26c58
GR		 1203 if (err < 0) \
1204 return err; \
9a61bf63 1205 mutex_lock(&data->update_lock); \
c5794cfa
JD		 1206 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1207 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
9a61bf63 1208 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1209 return count; \
1210}
ec3e5a16
GR		 1211store_temp_reg(reg_temp_over, temp_max);
1212store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1213
da667365
JD		 1214static ssize_t
1215show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1216{
1217 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1218 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1219 int nr = sensor_attr->index;
1220 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1221}
1222
a157d06d 1223static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1224 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1225 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1226 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1227 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1228 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1229 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1230 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1231 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1232 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1233};
1234
1235static struct sensor_device_attribute sda_temp_label[] = {
1236 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1237 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1238 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1239 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1240 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1241 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1242 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1243 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1244 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1245};
1246
1247static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1248 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1249 store_temp_max, 0),
bce26c58 1250 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1251 store_temp_max, 1),
bce26c58
GR		 1252 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1253 store_temp_max, 2),
ec3e5a16
GR		 1254 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1255 store_temp_max, 3),
1256 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1257 store_temp_max, 4),
1258 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1259 store_temp_max, 5),
1260 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1261 store_temp_max, 6),
1262 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1263 store_temp_max, 7),
1264 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1265 store_temp_max, 8),
a157d06d
GJ		 1266};
1267
1268static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1269 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1270 store_temp_max_hyst, 0),
bce26c58 1271 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1272 store_temp_max_hyst, 1),
bce26c58
GR		 1273 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1274 store_temp_max_hyst, 2),
ec3e5a16
GR		 1275 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1276 store_temp_max_hyst, 3),
1277 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1278 store_temp_max_hyst, 4),
1279 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1280 store_temp_max_hyst, 5),
1281 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1282 store_temp_max_hyst, 6),
1283 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1284 store_temp_max_hyst, 7),
1285 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1286 store_temp_max_hyst, 8),
a157d06d
GJ		 1287};
1288
1289static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1290 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1291 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1292 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1293};
1294
1295static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1296 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1297 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1298 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1299};
08e7e278 1300
08c79950 1301#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1302static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1303 char *buf) \
08c79950
RM		 1304{ \
1305 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1306 struct sensor_device_attribute *sensor_attr = \
1307 to_sensor_dev_attr(attr); \
08c79950
RM		 1308 int nr = sensor_attr->index; \
1309 return sprintf(buf, "%d\n", data->reg[nr]); \
1310}
1311
1312show_pwm_reg(pwm_mode)
1313show_pwm_reg(pwm_enable)
1314show_pwm_reg(pwm)
1315
1316static ssize_t
1317store_pwm_mode(struct device *dev, struct device_attribute *attr,
1318 const char *buf, size_t count)
1319{
1ea6dd38 1320 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 1321 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
ad77c3e1 1322 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950 1323 int nr = sensor_attr->index;
bce26c58
GR		 1324 unsigned long val;
1325 int err;
08c79950
RM		 1326 u16 reg;
1327
179c4fdb 1328 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1329 if (err < 0)
1330 return err;
1331
08c79950
RM		 1332 if (val > 1)
1333 return -EINVAL;
ad77c3e1
GR		 1334
1335 /* On NCT67766F, DC mode is only supported for pwm1 */
1336 if (sio_data->kind == nct6776 && nr && val != 1)
1337 return -EINVAL;
1338
08c79950 1339 mutex_lock(&data->update_lock);
1ea6dd38 1340 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1341 data->pwm_mode[nr] = val;
1342 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1343 if (!val)
1344 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1345 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1346 mutex_unlock(&data->update_lock);
1347 return count;
1348}
1349
1350static ssize_t
1351store_pwm(struct device *dev, struct device_attribute *attr,
1352 const char *buf, size_t count)
1353{
1ea6dd38 1354 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1355 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1356 int nr = sensor_attr->index;
bce26c58
GR		 1357 unsigned long val;
1358 int err;
1359
179c4fdb 1360 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1361 if (err < 0)
1362 return err;
1363
1364 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 1365
1366 mutex_lock(&data->update_lock);
1367 data->pwm[nr] = val;
279af1a9 1368 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1369 mutex_unlock(&data->update_lock);
1370 return count;
1371}
1372
1373static ssize_t
1374store_pwm_enable(struct device *dev, struct device_attribute *attr,
1375 const char *buf, size_t count)
1376{
1ea6dd38 1377 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1378 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1379 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1380 int nr = sensor_attr->index;
bce26c58
GR		 1381 unsigned long val;
1382 int err;
08c79950
RM		 1383 u16 reg;
1384
179c4fdb 1385 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1386 if (err < 0)
1387 return err;
1388
b84bb518 1389 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1390 return -EINVAL;
ec3e5a16
GR		 1391 /* SmartFan III mode is not supported on NCT6776F */
1392 if (sio_data->kind == nct6776 && val == 4)
1393 return -EINVAL;
1394
08c79950 1395 mutex_lock(&data->update_lock);
08c79950 1396 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1397 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1398 reg = w83627ehf_read_value(data,
1399 NCT6775_REG_FAN_MODE[nr]);
1400 reg &= 0x0f;
1401 reg |= (val - 1) << 4;
1402 w83627ehf_write_value(data,
1403 NCT6775_REG_FAN_MODE[nr], reg);
1404 } else {
1405 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1406 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1407 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1408 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1409 }
08c79950
RM		 1410 mutex_unlock(&data->update_lock);
1411 return count;
1412}
1413
1414
1415#define show_tol_temp(reg) \
1416static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1417 char *buf) \
1418{ \
1419 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1420 struct sensor_device_attribute *sensor_attr = \
1421 to_sensor_dev_attr(attr); \
08c79950 1422 int nr = sensor_attr->index; \
bce26c58 1423 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1424}
1425
1426show_tol_temp(tolerance)
1427show_tol_temp(target_temp)
1428
1429static ssize_t
1430store_target_temp(struct device *dev, struct device_attribute *attr,
1431 const char *buf, size_t count)
1432{
1ea6dd38 1433 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1434 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1435 int nr = sensor_attr->index;
bce26c58
GR		 1436 long val;
1437 int err;
1438
179c4fdb 1439 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1440 if (err < 0)
1441 return err;
1442
1443 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1444
1445 mutex_lock(&data->update_lock);
1446 data->target_temp[nr] = val;
279af1a9 1447 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1448 mutex_unlock(&data->update_lock);
1449 return count;
1450}
1451
1452static ssize_t
1453store_tolerance(struct device *dev, struct device_attribute *attr,
1454 const char *buf, size_t count)
1455{
1ea6dd38 1456 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1457 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1458 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1459 int nr = sensor_attr->index;
1460 u16 reg;
bce26c58
GR		 1461 long val;
1462 int err;
1463
179c4fdb 1464 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1465 if (err < 0)
1466 return err;
1467
08c79950 1468 /* Limit the temp to 0C - 15C */
bce26c58 1469 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1470
1471 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1472 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1473 /* Limit tolerance further for NCT6776F */
1474 if (sio_data->kind == nct6776 && val > 7)
1475 val = 7;
1476 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1477 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1478 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1479 } else {
1480 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1481 if (nr == 1)
1482 reg = (reg & 0x0f) | (val << 4);
1483 else
1484 reg = (reg & 0xf0) | val;
1485 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1486 }
1487 data->tolerance[nr] = val;
08c79950
RM		 1488 mutex_unlock(&data->update_lock);
1489 return count;
1490}
1491
1492static struct sensor_device_attribute sda_pwm[] = {
1493 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1494 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1495 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1496 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1497};
1498
1499static struct sensor_device_attribute sda_pwm_mode[] = {
1500 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1501 store_pwm_mode, 0),
1502 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1503 store_pwm_mode, 1),
1504 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1505 store_pwm_mode, 2),
1506 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1507 store_pwm_mode, 3),
1508};
1509
1510static struct sensor_device_attribute sda_pwm_enable[] = {
1511 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1512 store_pwm_enable, 0),
1513 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1514 store_pwm_enable, 1),
1515 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1516 store_pwm_enable, 2),
1517 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1518 store_pwm_enable, 3),
1519};
1520
1521static struct sensor_device_attribute sda_target_temp[] = {
1522 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1523 store_target_temp, 0),
1524 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1525 store_target_temp, 1),
1526 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1527 store_target_temp, 2),
1528 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1529 store_target_temp, 3),
1530};
1531
1532static struct sensor_device_attribute sda_tolerance[] = {
1533 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1534 store_tolerance, 0),
1535 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1536 store_tolerance, 1),
1537 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1538 store_tolerance, 2),
1539 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1540 store_tolerance, 3),
1541};
1542
08c79950
RM		 1543/* Smart Fan registers */
1544
1545#define fan_functions(reg, REG) \
1546static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1547 char *buf) \
1548{ \
1549 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1550 struct sensor_device_attribute *sensor_attr = \
1551 to_sensor_dev_attr(attr); \
08c79950
RM		 1552 int nr = sensor_attr->index; \
1553 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1554} \
08c79950
RM		 1555static ssize_t \
1556store_##reg(struct device *dev, struct device_attribute *attr, \
1557 const char *buf, size_t count) \
e7e1ca6e 1558{ \
1ea6dd38 1559 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1560 struct sensor_device_attribute *sensor_attr = \
1561 to_sensor_dev_attr(attr); \
08c79950 1562 int nr = sensor_attr->index; \
bce26c58
GR		 1563 unsigned long val; \
1564 int err; \
179c4fdb 1565 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1566 if (err < 0) \
1567 return err; \
1568 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1569 mutex_lock(&data->update_lock); \
1570 data->reg[nr] = val; \
da2e0255 1571 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1572 mutex_unlock(&data->update_lock); \
1573 return count; \
1574}
1575
41e9a062
DB		 1576fan_functions(fan_start_output, FAN_START_OUTPUT)
1577fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1578fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1579fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1580
1581#define fan_time_functions(reg, REG) \
1582static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1583 char *buf) \
1584{ \
1585 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1586 struct sensor_device_attribute *sensor_attr = \
1587 to_sensor_dev_attr(attr); \
08c79950
RM		 1588 int nr = sensor_attr->index; \
1589 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1590 step_time_from_reg(data->reg[nr], \
1591 data->pwm_mode[nr])); \
08c79950
RM		 1592} \
1593\
1594static ssize_t \
1595store_##reg(struct device *dev, struct device_attribute *attr, \
1596 const char *buf, size_t count) \
1597{ \
1ea6dd38 1598 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1599 struct sensor_device_attribute *sensor_attr = \
1600 to_sensor_dev_attr(attr); \
08c79950 1601 int nr = sensor_attr->index; \
bce26c58
GR		 1602 unsigned long val; \
1603 int err; \
179c4fdb 1604 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1605 if (err < 0) \
1606 return err; \
1607 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1608 mutex_lock(&data->update_lock); \
1609 data->reg[nr] = val; \
1ea6dd38 1610 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1611 mutex_unlock(&data->update_lock); \
1612 return count; \
1613} \
1614
1615fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1616
1ea6dd38
DH		 1617static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1618 char *buf)
1619{
1620 struct w83627ehf_data *data = dev_get_drvdata(dev);
1621
1622 return sprintf(buf, "%s\n", data->name);
1623}
1624static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1625
1626static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1627 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1628 store_fan_stop_time, 3),
41e9a062
DB		 1629 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1630 store_fan_start_output, 3),
1631 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1632 store_fan_stop_output, 3),
1633 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1634 store_fan_max_output, 3),
1635 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1636 store_fan_step_output, 3),
08c79950
RM		 1637};
1638
eff7687d
JD		 1639static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1640 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1641 store_fan_stop_time, 2),
1642 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1643 store_fan_start_output, 2),
1644 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1645 store_fan_stop_output, 2),
1646};
1647
08c79950
RM		 1648static struct sensor_device_attribute sda_sf3_arrays[] = {
1649 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1650 store_fan_stop_time, 0),
1651 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1652 store_fan_stop_time, 1),
41e9a062
DB		 1653 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1654 store_fan_start_output, 0),
1655 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1656 store_fan_start_output, 1),
41e9a062
DB		 1657 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1658 store_fan_stop_output, 0),
1659 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1660 store_fan_stop_output, 1),
da2e0255 1661};
41e9a062 1662
da2e0255
GR		 1663
1664/*
1665 * pwm1 and pwm3 don't support max and step settings on all chips.
1666 * Need to check support while generating/removing attribute files.
1667 */
1668static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1669 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1670 store_fan_max_output, 0),
1671 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1672 store_fan_step_output, 0),
41e9a062
DB		 1673 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1674 store_fan_max_output, 1),
1675 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1676 store_fan_step_output, 1),
da2e0255
GR		 1677 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1678 store_fan_max_output, 2),
1679 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1680 store_fan_step_output, 2),
08c79950
RM		 1681};
1682
fc18d6c0
JD		 1683static ssize_t
1684show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1685{
1686 struct w83627ehf_data *data = dev_get_drvdata(dev);
1687 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1688}
1689static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1690
363a12a4
DA		 1691
1692/* Case open detection */
1693
1694static ssize_t
1695show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1696{
1697 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1698
1699 return sprintf(buf, "%d\n",
1700 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1701}
1702
1703static ssize_t
1704clear_caseopen(struct device *dev, struct device_attribute *attr,
1705 const char *buf, size_t count)
1706{
1707 struct w83627ehf_data *data = dev_get_drvdata(dev);
1708 unsigned long val;
1709 u16 reg, mask;
1710
179c4fdb 1711 if (kstrtoul(buf, 10, &val) || val != 0)
363a12a4
DA		 1712 return -EINVAL;
1713
1714 mask = to_sensor_dev_attr_2(attr)->nr;
1715
1716 mutex_lock(&data->update_lock);
1717 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1718 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1719 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1720 data->valid = 0; /* Force cache refresh */
1721 mutex_unlock(&data->update_lock);
1722
1723 return count;
1724}
1725
1726static struct sensor_device_attribute_2 sda_caseopen[] = {
1727 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1728 clear_caseopen, 0x80, 0x10),
1729 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1730 clear_caseopen, 0x40, 0x40),
1731};
1732
08e7e278 1733/*
1ea6dd38 1734 * Driver and device management
08e7e278
JD		 1735 */
1736
c18beb5b
DH		 1737static void w83627ehf_device_remove_files(struct device *dev)
1738{
1739 /* some entries in the following arrays may not have been used in
1740 * device_create_file(), but device_remove_file() will ignore them */
1741 int i;
1ea6dd38 1742 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1743
1744 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1745 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1746 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1747 struct sensor_device_attribute *attr =
1748 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1749 if (data->REG_FAN_STEP_OUTPUT &&
1750 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1751 device_remove_file(dev, &attr->dev_attr);
1752 }
eff7687d
JD		 1753 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1754 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
c18beb5b
DH		 1755 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1756 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1757 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1758 if ((i == 6) && data->in6_skip)
1759 continue;
c18beb5b
DH		 1760 device_remove_file(dev, &sda_in_input[i].dev_attr);
1761 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1762 device_remove_file(dev, &sda_in_min[i].dev_attr);
1763 device_remove_file(dev, &sda_in_max[i].dev_attr);
1764 }
1765 for (i = 0; i < 5; i++) {
1766 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1767 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1768 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1769 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1770 }
237c8d2f 1771 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1772 device_remove_file(dev, &sda_pwm[i].dev_attr);
1773 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1774 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1775 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1776 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1777 }
d36cf32c
GR		 1778 for (i = 0; i < NUM_REG_TEMP; i++) {
1779 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1780 continue;
1781 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1782 device_remove_file(dev, &sda_temp_label[i].dev_attr);
eff7687d
JD		 1783 if (i == 2 && data->temp3_val_only)
1784 continue;
a157d06d
GJ		 1785 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1786 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1787 if (i > 2)
1788 continue;
a157d06d
GJ		 1789 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1790 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1791 }
c18beb5b 1792
363a12a4
DA		 1793 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1794 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1795
1ea6dd38 1796 device_remove_file(dev, &dev_attr_name);
cbe311f2 1797 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1798}
08e7e278 1799
1ea6dd38 1800/* Get the monitoring functions started */
bf164c58
JD		 1801static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
1802 enum kinds kind)
08e7e278
JD		 1803{
1804 int i;
da667365 1805 u8 tmp, diode;
08e7e278
JD		 1806
1807 /* Start monitoring is needed */
1ea6dd38 1808 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1809 if (!(tmp & 0x01))
1ea6dd38 1810 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1811 tmp | 0x01);
1812
d36cf32c
GR		 1813 /* Enable temperature sensors if needed */
1814 for (i = 0; i < NUM_REG_TEMP; i++) {
1815 if (!(data->have_temp & (1 << i)))
1816 continue;
ec3e5a16 1817 if (!data->reg_temp_config[i])
d36cf32c 1818 continue;
1ea6dd38 1819 tmp = w83627ehf_read_value(data,
ec3e5a16 1820 data->reg_temp_config[i]);
08e7e278 1821 if (tmp & 0x01)
1ea6dd38 1822 w83627ehf_write_value(data,
ec3e5a16 1823 data->reg_temp_config[i],
08e7e278
JD		 1824 tmp & 0xfe);
1825 }
d3130f0e
JD		 1826
1827 /* Enable VBAT monitoring if needed */
1828 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1829 if (!(tmp & 0x01))
1830 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1831
1832 /* Get thermal sensor types */
bf164c58
JD		 1833 switch (kind) {
1834 case w83627ehf:
1835 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1836 break;
eff7687d
JD		 1837 case w83627uhg:
1838 diode = 0x00;
1839 break;
bf164c58
JD		 1840 default:
1841 diode = 0x70;
1842 }
da667365 1843 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1844 const char *label = NULL;
1845
1846 if (data->temp_label)
1847 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1848
1849 /* Digital source overrides analog type */
bfa02b0d 1850 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1851 data->temp_type[i] = 6;
bfa02b0d 1852 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1853 data->temp_type[i] = 5;
1854 else if ((tmp & (0x02 << i)))
bf164c58 1855 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1856 else
1857 data->temp_type[i] = 4; /* thermistor */
1858 }
08e7e278
JD		 1859}
1860
ec3e5a16
GR		 1861static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1862 int r1, int r2)
1863{
1864 u16 tmp;
1865
1866 tmp = data->temp_src[r1];
1867 data->temp_src[r1] = data->temp_src[r2];
1868 data->temp_src[r2] = tmp;
1869
1870 tmp = data->reg_temp[r1];
1871 data->reg_temp[r1] = data->reg_temp[r2];
1872 data->reg_temp[r2] = tmp;
1873
1874 tmp = data->reg_temp_over[r1];
1875 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1876 data->reg_temp_over[r2] = tmp;
1877
1878 tmp = data->reg_temp_hyst[r1];
1879 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1880 data->reg_temp_hyst[r2] = tmp;
1881
1882 tmp = data->reg_temp_config[r1];
1883 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1884 data->reg_temp_config[r2] = tmp;
1885}
1886
6ba71de5
JD		 1887static void __devinit
1888w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1889{
1890 int i;
1891
1892 for (i = 0; i < n_temp; i++) {
1893 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1894 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1895 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1896 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1897 }
1898}
1899
03f5de2b
JD		 1900static void __devinit
1901w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1902 struct w83627ehf_data *data)
1903{
1904 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1905
eff7687d
JD		 1906 /* The W83627UHG is simple, only two fan inputs, no config */
1907 if (sio_data->kind == w83627uhg) {
1908 data->has_fan = 0x03; /* fan1 and fan2 */
1909 data->has_fan_min = 0x03;
1910 return;
1911 }
1912
03f5de2b
JD		 1913 superio_enter(sio_data->sioreg);
1914
1915 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1916 if (sio_data->kind == nct6775) {
1917 /* On NCT6775, fan4 shares pins with the fdc interface */
1918 fan3pin = 1;
1919 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1920 fan4min = 0;
1921 fan5pin = 0;
1922 } else if (sio_data->kind == nct6776) {
1923 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
1924 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
1925 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
1926 fan4min = fan4pin;
1927 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
1928 fan3pin = 1;
1929 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1930 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1931 fan4min = fan4pin;
1932 } else {
1933 fan3pin = 1;
1934 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1935 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1936 fan4min = fan4pin;
1937 }
1938
1939 superio_exit(sio_data->sioreg);
1940
1941 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
1942 data->has_fan |= (fan3pin << 2);
1943 data->has_fan_min |= (fan3pin << 2);
1944
1945 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1946 /*
1947 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
1948 * register
1949 */
1950 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
1951 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
1952 } else {
1953 /*
1954 * It looks like fan4 and fan5 pins can be alternatively used
1955 * as fan on/off switches, but fan5 control is write only :/
1956 * We assume that if the serial interface is disabled, designers
1957 * connected fan5 as input unless they are emitting log 1, which
1958 * is not the default.
1959 */
1960 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1961 if ((regval & (1 << 2)) && fan4pin) {
1962 data->has_fan |= (1 << 3);
1963 data->has_fan_min |= (1 << 3);
1964 }
1965 if (!(regval & (1 << 1)) && fan5pin) {
1966 data->has_fan |= (1 << 4);
1967 data->has_fan_min |= (1 << 4);
1968 }
1969 }
1970}
1971
1ea6dd38 1972static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1973{
1ea6dd38
DH		 1974 struct device *dev = &pdev->dev;
1975 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1976 struct w83627ehf_data *data;
1ea6dd38 1977 struct resource *res;
03f5de2b 1978 u8 en_vrm10;
08e7e278
JD		 1979 int i, err = 0;
1980
1ea6dd38
DH		 1981 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1982 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1983 err = -EBUSY;
1ea6dd38
DH		 1984 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1985 (unsigned long)res->start,
1986 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1987 goto exit;
1988 }
1989
e7e1ca6e
GR		 1990 data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL);
1991 if (!data) {
08e7e278
JD		 1992 err = -ENOMEM;
1993 goto exit_release;
1994 }
08e7e278 1995
1ea6dd38 1996 data->addr = res->start;
9a61bf63 1997 mutex_init(&data->lock);
9a61bf63 1998 mutex_init(&data->update_lock);
1ea6dd38
DH		 1999 data->name = w83627ehf_device_names[sio_data->kind];
2000 platform_set_drvdata(pdev, data);
08e7e278 2001
237c8d2f
GJ		 2002 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2003 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
eff7687d
JD		 2004 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2005 switch (sio_data->kind) {
2006 default:
2007 data->pwm_num = 4;
2008 break;
2009 case w83667hg:
2010 case w83667hg_b:
2011 case nct6775:
2012 case nct6776:
2013 data->pwm_num = 3;
2014 break;
2015 case w83627uhg:
2016 data->pwm_num = 2;
2017 break;
2018 }
08e7e278 2019
6ba71de5 2020 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 2021 data->have_temp = 0x07;
ec3e5a16
GR		 2022
2023 /* Deal with temperature register setup first. */
2024 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2025 int mask = 0;
2026
2027 /*
2028 * Display temperature sensor output only if it monitors
2029 * a source other than one already reported. Always display
2030 * first three temperature registers, though.
2031 */
2032 for (i = 0; i < NUM_REG_TEMP; i++) {
2033 u8 src;
2034
2035 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2036 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2037 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2038 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2039
2040 src = w83627ehf_read_value(data,
2041 NCT6775_REG_TEMP_SOURCE[i]);
2042 src &= 0x1f;
2043 if (src && !(mask & (1 << src))) {
2044 data->have_temp |= 1 << i;
2045 mask |= 1 << src;
2046 }
2047
2048 data->temp_src[i] = src;
2049
2050 /*
2051 * Now do some register swapping if index 0..2 don't
2052 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2053 * Idea is to have the first three attributes
2054 * report SYSTIN, CPUIN, and AUXIN if possible
2055 * without overriding the basic system configuration.
2056 */
2057 if (i > 0 && data->temp_src[0] != 1
2058 && data->temp_src[i] == 1)
2059 w82627ehf_swap_tempreg(data, 0, i);
2060 if (i > 1 && data->temp_src[1] != 2
2061 && data->temp_src[i] == 2)
2062 w82627ehf_swap_tempreg(data, 1, i);
2063 if (i > 2 && data->temp_src[2] != 3
2064 && data->temp_src[i] == 3)
2065 w82627ehf_swap_tempreg(data, 2, i);
2066 }
2067 if (sio_data->kind == nct6776) {
2068 /*
2069 * On NCT6776, AUXTIN and VIN3 pins are shared.
2070 * Only way to detect it is to check if AUXTIN is used
2071 * as a temperature source, and if that source is
2072 * enabled.
2073 *
2074 * If that is the case, disable in6, which reports VIN3.
2075 * Otherwise disable temp3.
2076 */
2077 if (data->temp_src[2] == 3) {
2078 u8 reg;
2079
2080 if (data->reg_temp_config[2])
2081 reg = w83627ehf_read_value(data,
2082 data->reg_temp_config[2]);
2083 else
2084 reg = 0; /* Assume AUXTIN is used */
2085
2086 if (reg & 0x01)
2087 data->have_temp &= ~(1 << 2);
2088 else
2089 data->in6_skip = 1;
2090 }
02309ad2
GR		 2091 data->temp_label = nct6776_temp_label;
2092 } else {
2093 data->temp_label = nct6775_temp_label;
ec3e5a16 2094 }
d36cf32c
GR		 2095 } else if (sio_data->kind == w83667hg_b) {
2096 u8 reg;
2097
6ba71de5
JD		 2098 w83627ehf_set_temp_reg_ehf(data, 4);
2099
ec3e5a16
GR		 2100 /*
2101 * Temperature sources are selected with bank 0, registers 0x49
2102 * and 0x4a.
2103 */
d36cf32c
GR		 2104 reg = w83627ehf_read_value(data, 0x4a);
2105 data->temp_src[0] = reg >> 5;
2106 reg = w83627ehf_read_value(data, 0x49);
2107 data->temp_src[1] = reg & 0x07;
ec3e5a16 2108 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 2109
2110 /*
2111 * W83667HG-B has another temperature register at 0x7e.
2112 * The temperature source is selected with register 0x7d.
2113 * Support it if the source differs from already reported
2114 * sources.
2115 */
2116 reg = w83627ehf_read_value(data, 0x7d);
2117 reg &= 0x07;
2118 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2119 && reg != data->temp_src[2]) {
2120 data->temp_src[3] = reg;
2121 data->have_temp |= 1 << 3;
2122 }
2123
2124 /*
2125 * Chip supports either AUXTIN or VIN3. Try to find out which
2126 * one.
2127 */
2128 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2129 if (data->temp_src[2] == 2 && (reg & 0x01))
2130 data->have_temp &= ~(1 << 2);
2131
2132 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2133 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2134 data->in6_skip = 1;
2135
eff7687d
JD		 2136 data->temp_label = w83667hg_b_temp_label;
2137 } else if (sio_data->kind == w83627uhg) {
2138 u8 reg;
2139
2140 w83627ehf_set_temp_reg_ehf(data, 3);
2141
2142 /*
2143 * Temperature sources for temp1 and temp2 are selected with
2144 * bank 0, registers 0x49 and 0x4a.
2145 */
2146 data->temp_src[0] = 0; /* SYSTIN */
2147 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2148 /* Adjust to have the same mapping as other source registers */
2149 if (reg == 0)
2150 data->temp_src[1]++;
2151 else if (reg >= 2 && reg <= 5)
2152 data->temp_src[1] += 2;
2153 else /* should never happen */
2154 data->have_temp &= ~(1 << 1);
2155 reg = w83627ehf_read_value(data, 0x4a);
2156 data->temp_src[2] = reg >> 5;
2157
2158 /*
2159 * Skip temp3 if source is invalid or the same as temp1
2160 * or temp2.
2161 */
2162 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2163 data->temp_src[2] == data->temp_src[0] ||
2164 ((data->have_temp & (1 << 1)) &&
2165 data->temp_src[2] == data->temp_src[1]))
2166 data->have_temp &= ~(1 << 2);
2167 else
2168 data->temp3_val_only = 1; /* No limit regs */
2169
2170 data->in6_skip = 1; /* No VIN3 */
2171
d36cf32c 2172 data->temp_label = w83667hg_b_temp_label;
ec3e5a16 2173 } else {
6ba71de5
JD		 2174 w83627ehf_set_temp_reg_ehf(data, 3);
2175
ec3e5a16 2176 /* Temperature sources are fixed */
6ba71de5
JD		 2177
2178 if (sio_data->kind == w83667hg) {
2179 u8 reg;
2180
2181 /*
2182 * Chip supports either AUXTIN or VIN3. Try to find
2183 * out which one.
2184 */
2185 reg = w83627ehf_read_value(data,
2186 W83627EHF_REG_TEMP_CONFIG[2]);
2187 if (reg & 0x01)
2188 data->have_temp &= ~(1 << 2);
2189 else
2190 data->in6_skip = 1;
ec3e5a16 2191 }
a157d06d
GJ		 2192 }
2193
ec3e5a16 2194 if (sio_data->kind == nct6775) {
26bc440e
GR		 2195 data->has_fan_div = true;
2196 data->fan_from_reg = fan_from_reg16;
2197 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2198 data->REG_PWM = NCT6775_REG_PWM;
2199 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2200 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2201 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2202 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2203 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2204 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2205 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2206 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2207 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2208 data->has_fan_div = false;
2209 data->fan_from_reg = fan_from_reg13;
2210 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2211 data->REG_PWM = NCT6775_REG_PWM;
2212 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2213 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2214 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2215 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2216 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2217 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2218 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2219 data->has_fan_div = true;
2220 data->fan_from_reg = fan_from_reg8;
2221 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2222 data->REG_PWM = W83627EHF_REG_PWM;
2223 data->REG_TARGET = W83627EHF_REG_TARGET;
2224 data->REG_FAN = W83627EHF_REG_FAN;
2225 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2226 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2227 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2228 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2229 data->REG_FAN_MAX_OUTPUT =
2230 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2231 data->REG_FAN_STEP_OUTPUT =
2232 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2233 } else {
26bc440e
GR		 2234 data->has_fan_div = true;
2235 data->fan_from_reg = fan_from_reg8;
2236 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2237 data->REG_PWM = W83627EHF_REG_PWM;
2238 data->REG_TARGET = W83627EHF_REG_TARGET;
2239 data->REG_FAN = W83627EHF_REG_FAN;
2240 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2241 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2242 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2243 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2244 data->REG_FAN_MAX_OUTPUT =
2245 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2246 data->REG_FAN_STEP_OUTPUT =
2247 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2248 }
da2e0255 2249
eff7687d
JD		 2250 /* Setup input voltage scaling factors */
2251 if (sio_data->kind == w83627uhg)
2252 data->scale_in = scale_in_w83627uhg;
2253 else
2254 data->scale_in = scale_in_common;
2255
08e7e278 2256 /* Initialize the chip */
bf164c58 2257 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2258
fc18d6c0
JD		 2259 data->vrm = vid_which_vrm();
2260 superio_enter(sio_data->sioreg);
fc18d6c0 2261 /* Read VID value */
ec3e5a16
GR		 2262 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2263 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
237c8d2f
GJ		 2264 /* W83667HG has different pins for VID input and output, so
2265 we can get the VID input values directly at logical device D
2266 0xe3. */
2267 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2268 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2269 err = device_create_file(dev, &dev_attr_cpu0_vid);
2270 if (err)
2271 goto exit_release;
eff7687d 2272 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 2273 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2274 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2275 /* Set VID input sensibility if needed. In theory the
2276 BIOS should have set it, but in practice it's not
2277 always the case. We only do it for the W83627EHF/EHG
2278 because the W83627DHG is more complex in this
2279 respect. */
2280 if (sio_data->kind == w83627ehf) {
2281 en_vrm10 = superio_inb(sio_data->sioreg,
2282 SIO_REG_EN_VRM10);
2283 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2284 dev_warn(dev, "Setting VID input "
2285 "voltage to TTL\n");
2286 superio_outb(sio_data->sioreg,
2287 SIO_REG_EN_VRM10,
2288 en_vrm10 & ~0x08);
2289 } else if (!(en_vrm10 & 0x08)
2290 && data->vrm == 100) {
2291 dev_warn(dev, "Setting VID input "
2292 "voltage to VRM10\n");
2293 superio_outb(sio_data->sioreg,
2294 SIO_REG_EN_VRM10,
2295 en_vrm10 | 0x08);
2296 }
2297 }
2298
2299 data->vid = superio_inb(sio_data->sioreg,
2300 SIO_REG_VID_DATA);
2301 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2302 data->vid &= 0x3f;
2303
2304 err = device_create_file(dev, &dev_attr_cpu0_vid);
2305 if (err)
2306 goto exit_release;
2307 } else {
2308 dev_info(dev, "VID pins in output mode, CPU VID not "
2309 "available\n");
2310 }
fc18d6c0
JD		 2311 }
2312
d42e869a
ID		 2313 if (fan_debounce &&
2314 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2315 u8 tmp;
2316
2317 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2318 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2319 if (sio_data->kind == nct6776)
2320 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2321 0x3e | tmp);
2322 else
2323 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2324 0x1e | tmp);
2325 pr_info("Enabled fan debounce for chip %s\n", data->name);
2326 }
2327
1ea6dd38 2328 superio_exit(sio_data->sioreg);
08c79950 2329
03f5de2b 2330 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 2331
ea7be66c 2332 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2333 w83627ehf_update_fan_div_common(dev, data);
2334
2335 /* Read pwm data to save original values */
2336 w83627ehf_update_pwm_common(dev, data);
2337 for (i = 0; i < data->pwm_num; i++)
2338 data->pwm_enable_orig[i] = data->pwm_enable[i];
ea7be66c 2339
b84bb518
GR		 2340 /* Read pwm data to save original values */
2341 w83627ehf_update_pwm_common(dev, data);
2342 for (i = 0; i < data->pwm_num; i++)
2343 data->pwm_enable_orig[i] = data->pwm_enable[i];
2344
08e7e278 2345 /* Register sysfs hooks */
e7e1ca6e
GR		 2346 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2347 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2348 if (err)
c18beb5b 2349 goto exit_remove;
e7e1ca6e 2350 }
08c79950 2351
da2e0255
GR		 2352 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2353 struct sensor_device_attribute *attr =
2354 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2355 if (data->REG_FAN_STEP_OUTPUT &&
2356 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2357 err = device_create_file(dev, &attr->dev_attr);
2358 if (err)
2359 goto exit_remove;
2360 }
2361 }
eff7687d
JD		 2362 /* if fan3 and fan4 are enabled create the sf3 files for them */
2363 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2364 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2365 err = device_create_file(dev,
2366 &sda_sf3_arrays_fan3[i].dev_attr);
2367 if (err)
2368 goto exit_remove;
2369 }
237c8d2f 2370 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2371 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2372 err = device_create_file(dev,
2373 &sda_sf3_arrays_fan4[i].dev_attr);
2374 if (err)
c18beb5b
DH		 2375 goto exit_remove;
2376 }
08c79950 2377
a157d06d
GJ		 2378 for (i = 0; i < data->in_num; i++) {
2379 if ((i == 6) && data->in6_skip)
2380 continue;
c18beb5b
DH		 2381 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2382 || (err = device_create_file(dev,
2383 &sda_in_alarm[i].dev_attr))
2384 || (err = device_create_file(dev,
2385 &sda_in_min[i].dev_attr))
2386 || (err = device_create_file(dev,
2387 &sda_in_max[i].dev_attr)))
2388 goto exit_remove;
a157d06d 2389 }
cf0676fe 2390
412fec82 2391 for (i = 0; i < 5; i++) {
08c79950 2392 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2393 if ((err = device_create_file(dev,
2394 &sda_fan_input[i].dev_attr))
2395 || (err = device_create_file(dev,
ec3e5a16 2396 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2397 goto exit_remove;
ec3e5a16
GR		 2398 if (sio_data->kind != nct6776) {
2399 err = device_create_file(dev,
2400 &sda_fan_div[i].dev_attr);
2401 if (err)
2402 goto exit_remove;
2403 }
2404 if (data->has_fan_min & (1 << i)) {
2405 err = device_create_file(dev,
2406 &sda_fan_min[i].dev_attr);
2407 if (err)
2408 goto exit_remove;
2409 }
237c8d2f 2410 if (i < data->pwm_num &&
c18beb5b
DH		 2411 ((err = device_create_file(dev,
2412 &sda_pwm[i].dev_attr))
2413 || (err = device_create_file(dev,
2414 &sda_pwm_mode[i].dev_attr))
2415 || (err = device_create_file(dev,
2416 &sda_pwm_enable[i].dev_attr))
2417 || (err = device_create_file(dev,
2418 &sda_target_temp[i].dev_attr))
2419 || (err = device_create_file(dev,
2420 &sda_tolerance[i].dev_attr))))
2421 goto exit_remove;
08c79950 2422 }
08e7e278 2423 }
08c79950 2424
d36cf32c
GR		 2425 for (i = 0; i < NUM_REG_TEMP; i++) {
2426 if (!(data->have_temp & (1 << i)))
a157d06d 2427 continue;
d36cf32c
GR		 2428 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2429 if (err)
2430 goto exit_remove;
2431 if (data->temp_label) {
2432 err = device_create_file(dev,
2433 &sda_temp_label[i].dev_attr);
2434 if (err)
2435 goto exit_remove;
2436 }
eff7687d
JD		 2437 if (i == 2 && data->temp3_val_only)
2438 continue;
ec3e5a16
GR		 2439 if (data->reg_temp_over[i]) {
2440 err = device_create_file(dev,
2441 &sda_temp_max[i].dev_attr);
2442 if (err)
2443 goto exit_remove;
2444 }
2445 if (data->reg_temp_hyst[i]) {
2446 err = device_create_file(dev,
2447 &sda_temp_max_hyst[i].dev_attr);
2448 if (err)
2449 goto exit_remove;
2450 }
d36cf32c 2451 if (i > 2)
ec3e5a16
GR		 2452 continue;
2453 if ((err = device_create_file(dev,
a157d06d
GJ		 2454 &sda_temp_alarm[i].dev_attr))
2455 || (err = device_create_file(dev,
2456 &sda_temp_type[i].dev_attr)))
c18beb5b 2457 goto exit_remove;
a157d06d 2458 }
c18beb5b 2459
363a12a4
DA		 2460 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2461 if (err)
2462 goto exit_remove;
2463
2464 if (sio_data->kind == nct6776) {
2465 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2466 if (err)
2467 goto exit_remove;
2468 }
2469
1ea6dd38
DH		 2470 err = device_create_file(dev, &dev_attr_name);
2471 if (err)
2472 goto exit_remove;
2473
1beeffe4
TJ		 2474 data->hwmon_dev = hwmon_device_register(dev);
2475 if (IS_ERR(data->hwmon_dev)) {
2476 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2477 goto exit_remove;
2478 }
08e7e278
JD		 2479
2480 return 0;
2481
c18beb5b
DH		 2482exit_remove:
2483 w83627ehf_device_remove_files(dev);
08e7e278 2484 kfree(data);
1ea6dd38 2485 platform_set_drvdata(pdev, NULL);
08e7e278 2486exit_release:
1ea6dd38 2487 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2488exit:
2489 return err;
2490}
2491
1ea6dd38 2492static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 2493{
1ea6dd38 2494 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2495
1beeffe4 2496 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2497 w83627ehf_device_remove_files(&pdev->dev);
2498 release_region(data->addr, IOREGION_LENGTH);
2499 platform_set_drvdata(pdev, NULL);
943b0830 2500 kfree(data);
08e7e278
JD		 2501
2502 return 0;
2503}
2504
1ea6dd38 2505static struct platform_driver w83627ehf_driver = {
cdaf7934 2506 .driver = {
87218842 2507 .owner = THIS_MODULE,
1ea6dd38 2508 .name = DRVNAME,
cdaf7934 2509 },
1ea6dd38
DH		 2510 .probe = w83627ehf_probe,
2511 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 2512};
2513
1ea6dd38
DH		 2514/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2515static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2516 struct w83627ehf_sio_data *sio_data)
08e7e278 2517{
1ea6dd38
DH		 2518 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
2519 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
2520 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 2521 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
eff7687d 2522 static const char __initdata sio_name_W83627UHG[] = "W83627UHG";
237c8d2f 2523 static const char __initdata sio_name_W83667HG[] = "W83667HG";
c39aedaf 2524 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
ec3e5a16
GR		 2525 static const char __initdata sio_name_NCT6775[] = "NCT6775F";
2526 static const char __initdata sio_name_NCT6776[] = "NCT6776F";
1ea6dd38 2527
08e7e278 2528 u16 val;
1ea6dd38 2529 const char *sio_name;
08e7e278 2530
1ea6dd38 2531 superio_enter(sioaddr);
08e7e278 2532
67b671bc
JD		 2533 if (force_id)
2534 val = force_id;
2535 else
2536 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2537 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2538 switch (val & SIO_ID_MASK) {
657c93b1 2539 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2540 sio_data->kind = w83627ehf;
2541 sio_name = sio_name_W83627EHF;
2542 break;
657c93b1 2543 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2544 sio_data->kind = w83627ehf;
2545 sio_name = sio_name_W83627EHG;
2546 break;
2547 case SIO_W83627DHG_ID:
2548 sio_data->kind = w83627dhg;
2549 sio_name = sio_name_W83627DHG;
657c93b1 2550 break;
c1e48dce
JD		 2551 case SIO_W83627DHG_P_ID:
2552 sio_data->kind = w83627dhg_p;
2553 sio_name = sio_name_W83627DHG_P;
2554 break;
eff7687d
JD		 2555 case SIO_W83627UHG_ID:
2556 sio_data->kind = w83627uhg;
2557 sio_name = sio_name_W83627UHG;
2558 break;
237c8d2f
GJ		 2559 case SIO_W83667HG_ID:
2560 sio_data->kind = w83667hg;
2561 sio_name = sio_name_W83667HG;
2562 break;
c39aedaf
GR		 2563 case SIO_W83667HG_B_ID:
2564 sio_data->kind = w83667hg_b;
2565 sio_name = sio_name_W83667HG_B;
2566 break;
ec3e5a16
GR		 2567 case SIO_NCT6775_ID:
2568 sio_data->kind = nct6775;
2569 sio_name = sio_name_NCT6775;
2570 break;
2571 case SIO_NCT6776_ID:
2572 sio_data->kind = nct6776;
2573 sio_name = sio_name_NCT6776;
2574 break;
657c93b1 2575 default:
9f66036b 2576 if (val != 0xffff)
abdc6fd1 2577 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2578 superio_exit(sioaddr);
08e7e278
JD		 2579 return -ENODEV;
2580 }
2581
1ea6dd38
DH		 2582 /* We have a known chip, find the HWM I/O address */
2583 superio_select(sioaddr, W83627EHF_LD_HWM);
2584 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2585 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2586 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2587 if (*addr == 0) {
abdc6fd1 2588 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2589 superio_exit(sioaddr);
08e7e278
JD		 2590 return -ENODEV;
2591 }
2592
2593 /* Activate logical device if needed */
1ea6dd38 2594 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2595 if (!(val & 0x01)) {
e7e1ca6e
GR		 2596 pr_warn("Forcibly enabling Super-I/O. "
2597 "Sensor is probably unusable.\n");
1ea6dd38 2598 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2599 }
1ea6dd38
DH		 2600
2601 superio_exit(sioaddr);
abdc6fd1 2602 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2603 sio_data->sioreg = sioaddr;
08e7e278 2604
08e7e278
JD		 2605 return 0;
2606}
2607
1ea6dd38
DH		 2608/* when Super-I/O functions move to a separate file, the Super-I/O
2609 * bus will manage the lifetime of the device and this module will only keep
2610 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2611 * must keep track of the device */
2612static struct platform_device *pdev;
2613
08e7e278
JD		 2614static int __init sensors_w83627ehf_init(void)
2615{
1ea6dd38
DH		 2616 int err;
2617 unsigned short address;
2618 struct resource res;
2619 struct w83627ehf_sio_data sio_data;
2620
2621 /* initialize sio_data->kind and sio_data->sioreg.
2622 *
2623 * when Super-I/O functions move to a separate file, the Super-I/O
2624 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2625 * w83627ehf hardware monitor, and call probe() */
2626 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2627 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2628 return -ENODEV;
2629
1ea6dd38
DH		 2630 err = platform_driver_register(&w83627ehf_driver);
2631 if (err)
2632 goto exit;
2633
e7e1ca6e
GR		 2634 pdev = platform_device_alloc(DRVNAME, address);
2635 if (!pdev) {
1ea6dd38 2636 err = -ENOMEM;
abdc6fd1 2637 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2638 goto exit_unregister;
2639 }
2640
2641 err = platform_device_add_data(pdev, &sio_data,
2642 sizeof(struct w83627ehf_sio_data));
2643 if (err) {
abdc6fd1 2644 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2645 goto exit_device_put;
2646 }
2647
2648 memset(&res, 0, sizeof(res));
2649 res.name = DRVNAME;
2650 res.start = address + IOREGION_OFFSET;
2651 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2652 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2653
2654 err = acpi_check_resource_conflict(&res);
2655 if (err)
18632f84 2656 goto exit_device_put;
b9acb64a 2657
1ea6dd38
DH		 2658 err = platform_device_add_resources(pdev, &res, 1);
2659 if (err) {
abdc6fd1 2660 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2661 goto exit_device_put;
2662 }
2663
2664 /* platform_device_add calls probe() */
2665 err = platform_device_add(pdev);
2666 if (err) {
abdc6fd1 2667 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2668 goto exit_device_put;
2669 }
2670
2671 return 0;
2672
2673exit_device_put:
2674 platform_device_put(pdev);
2675exit_unregister:
2676 platform_driver_unregister(&w83627ehf_driver);
2677exit:
2678 return err;
08e7e278
JD		 2679}
2680
2681static void __exit sensors_w83627ehf_exit(void)
2682{
1ea6dd38
DH		 2683 platform_device_unregister(pdev);
2684 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2685}
2686
2687MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2688MODULE_DESCRIPTION("W83627EHF driver");
2689MODULE_LICENSE("GPL");
2690
2691module_init(sensors_w83627ehf_init);
2692module_exit(sensors_w83627ehf_exit);
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