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hwmon: (w83627hf) Don't touch nonexistent I2C address registers
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278 1/*
8969e84d
GR		 2 * w83627ehf - Driver for the hardware monitoring functionality of
3 * the Winbond W83627EHF Super-I/O chip
7e630bb5 4 * Copyright (C) 2005-2012 Jean Delvare <khali@linux-fr.org>
8969e84d
GR		 5 * Copyright (C) 2006 Yuan Mu (Winbond),
6 * Rudolf Marek <r.marek@assembler.cz>
7 * David Hubbard <david.c.hubbard@gmail.com>
8 * Daniel J Blueman <daniel.blueman@gmail.com>
9 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
10 *
11 * Shamelessly ripped from the w83627hf driver
12 * Copyright (C) 2003 Mark Studebaker
13 *
14 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 * in testing and debugging this driver.
16 *
17 * This driver also supports the W83627EHG, which is the lead-free
18 * version of the W83627EHF.
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 * Supports the following chips:
35 *
36 * Chip #vin #fan #pwm #temp chip IDs man ID
37 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
38 * 0x8860 0xa1
39 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
40 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
41 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
42 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
43 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
44 * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 * nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
46 */
08e7e278 47
abdc6fd1
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
08e7e278
JD		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
1ea6dd38
DH		 53#include <linux/jiffies.h>
54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
412fec82 56#include <linux/hwmon-sysfs.h>
fc18d6c0 57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
b9acb64a 60#include <linux/acpi.h>
6055fae8 61#include <linux/io.h>
08e7e278
JD		 62#include "lm75.h"
63
eff7687d
JD		 64enum kinds {
65 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
66 w83667hg, w83667hg_b, nct6775, nct6776,
67};
08e7e278 68
1ea6dd38 69/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 70static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 71 "w83627ehf",
72 "w83627dhg",
c1e48dce 73 "w83627dhg",
eff7687d 74 "w83627uhg",
237c8d2f 75 "w83667hg",
c39aedaf 76 "w83667hg",
ec3e5a16
GR		 77 "nct6775",
78 "nct6776",
1ea6dd38
DH		 79};
80
67b671bc
JD		 81static unsigned short force_id;
82module_param(force_id, ushort, 0);
83MODULE_PARM_DESC(force_id, "Override the detected device ID");
84
d42e869a
ID		 85static unsigned short fan_debounce;
86module_param(fan_debounce, ushort, 0);
87MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
88
1ea6dd38 89#define DRVNAME "w83627ehf"
08e7e278 90
657c93b1 91/*
1ea6dd38 92 * Super-I/O constants and functions
657c93b1 93 */
08e7e278
JD		 94
95#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 96#define W83667HG_LD_VID 0x0d
08e7e278
JD		 97
98#define SIO_REG_LDSEL 0x07 /* Logical device select */
99#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 100#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 101#define SIO_REG_ENABLE 0x30 /* Logical device enable */
102#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 103#define SIO_REG_VID_CTRL 0xF0 /* VID control */
104#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 105
657c93b1
DH		 106#define SIO_W83627EHF_ID 0x8850
107#define SIO_W83627EHG_ID 0x8860
108#define SIO_W83627DHG_ID 0xa020
c1e48dce 109#define SIO_W83627DHG_P_ID 0xb070
eff7687d 110#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 111#define SIO_W83667HG_ID 0xa510
c39aedaf 112#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 113#define SIO_NCT6775_ID 0xb470
114#define SIO_NCT6776_ID 0xc330
657c93b1 115#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 116
117static inline void
1ea6dd38 118superio_outb(int ioreg, int reg, int val)
08e7e278 119{
1ea6dd38
DH		 120 outb(reg, ioreg);
121 outb(val, ioreg + 1);
08e7e278
JD		 122}
123
124static inline int
1ea6dd38 125superio_inb(int ioreg, int reg)
08e7e278 126{
1ea6dd38
DH		 127 outb(reg, ioreg);
128 return inb(ioreg + 1);
08e7e278
JD		 129}
130
131static inline void
1ea6dd38 132superio_select(int ioreg, int ld)
08e7e278 133{
1ea6dd38
DH		 134 outb(SIO_REG_LDSEL, ioreg);
135 outb(ld, ioreg + 1);
08e7e278
JD		 136}
137
138static inline void
1ea6dd38 139superio_enter(int ioreg)
08e7e278 140{
1ea6dd38
DH		 141 outb(0x87, ioreg);
142 outb(0x87, ioreg);
08e7e278
JD		 143}
144
145static inline void
1ea6dd38 146superio_exit(int ioreg)
08e7e278 147{
022b75a3 148 outb(0xaa, ioreg);
1ea6dd38
DH		 149 outb(0x02, ioreg);
150 outb(0x02, ioreg + 1);
08e7e278
JD		 151}
152
153/*
154 * ISA constants
155 */
156
e7e1ca6e 157#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 158#define IOREGION_OFFSET 5
159#define IOREGION_LENGTH 2
1ea6dd38
DH		 160#define ADDR_REG_OFFSET 0
161#define DATA_REG_OFFSET 1
08e7e278
JD		 162
163#define W83627EHF_REG_BANK 0x4E
164#define W83627EHF_REG_CONFIG 0x40
657c93b1 165
8969e84d
GR		 166/*
167 * Not currently used:
657c93b1
DH		 168 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
169 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
170 * REG_MAN_ID is at port 0x4f
8969e84d
GR		 171 * REG_CHIP_ID is at port 0x58
172 */
08e7e278
JD		 173
174static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
175static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
176
cf0676fe
RM		 177/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
178#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
179 (0x554 + (((nr) - 7) * 2)))
180#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
181 (0x555 + (((nr) - 7) * 2)))
182#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
183 (0x550 + (nr) - 7))
184
d36cf32c
GR		 185static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
186static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
187static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
188static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 189
190/* Fan clock dividers are spread over the following five registers */
191#define W83627EHF_REG_FANDIV1 0x47
192#define W83627EHF_REG_FANDIV2 0x4B
193#define W83627EHF_REG_VBAT 0x5D
194#define W83627EHF_REG_DIODE 0x59
195#define W83627EHF_REG_SMI_OVT 0x4C
196
ec3e5a16
GR		 197/* NCT6775F has its own fan divider registers */
198#define NCT6775_REG_FANDIV1 0x506
199#define NCT6775_REG_FANDIV2 0x507
d42e869a 200#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 201
a4589dbb
JD		 202#define W83627EHF_REG_ALARM1 0x459
203#define W83627EHF_REG_ALARM2 0x45A
204#define W83627EHF_REG_ALARM3 0x45B
205
363a12a4
DA		 206#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
207#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
208
08c79950 209/* SmartFan registers */
41e9a062
DB		 210#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
211#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
212
08c79950
RM		 213/* DC or PWM output fan configuration */
214static const u8 W83627EHF_REG_PWM_ENABLE[] = {
215 0x04, /* SYS FAN0 output mode and PWM mode */
216 0x04, /* CPU FAN0 output mode and PWM mode */
217 0x12, /* AUX FAN mode */
41e9a062 218 0x62, /* CPU FAN1 mode */
08c79950
RM		 219};
220
221static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
222static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
223
224/* FAN Duty Cycle, be used to control */
279af1a9
GR		 225static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
226static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 227static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
228
08c79950 229/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 230static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
231static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
232static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 233
279af1a9 234static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 235 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 236static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 237 = { 0xff, 0x68, 0xff, 0x6a };
238
279af1a9
GR		 239static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
240static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
241 = { 0x68, 0x6a, 0x6c };
08c79950 242
840e191d
GR		 243static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
244
ec3e5a16
GR		 245static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
246static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
247static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
248static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
249static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
250static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
251static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
252static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 253static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 254static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
255
256static const u16 NCT6775_REG_TEMP[]
257 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
258static const u16 NCT6775_REG_TEMP_CONFIG[]
259 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
260static const u16 NCT6775_REG_TEMP_HYST[]
261 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
262static const u16 NCT6775_REG_TEMP_OVER[]
263 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
264static const u16 NCT6775_REG_TEMP_SOURCE[]
265 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
266
d36cf32c
GR		 267static const char *const w83667hg_b_temp_label[] = {
268 "SYSTIN",
269 "CPUTIN",
270 "AUXTIN",
271 "AMDTSI",
272 "PECI Agent 1",
273 "PECI Agent 2",
274 "PECI Agent 3",
275 "PECI Agent 4"
276};
277
ec3e5a16
GR		 278static const char *const nct6775_temp_label[] = {
279 "",
280 "SYSTIN",
281 "CPUTIN",
282 "AUXTIN",
283 "AMD SB-TSI",
284 "PECI Agent 0",
285 "PECI Agent 1",
286 "PECI Agent 2",
287 "PECI Agent 3",
288 "PECI Agent 4",
289 "PECI Agent 5",
290 "PECI Agent 6",
291 "PECI Agent 7",
292 "PCH_CHIP_CPU_MAX_TEMP",
293 "PCH_CHIP_TEMP",
294 "PCH_CPU_TEMP",
295 "PCH_MCH_TEMP",
296 "PCH_DIM0_TEMP",
297 "PCH_DIM1_TEMP",
298 "PCH_DIM2_TEMP",
299 "PCH_DIM3_TEMP"
300};
301
302static const char *const nct6776_temp_label[] = {
303 "",
304 "SYSTIN",
305 "CPUTIN",
306 "AUXTIN",
307 "SMBUSMASTER 0",
308 "SMBUSMASTER 1",
309 "SMBUSMASTER 2",
310 "SMBUSMASTER 3",
311 "SMBUSMASTER 4",
312 "SMBUSMASTER 5",
313 "SMBUSMASTER 6",
314 "SMBUSMASTER 7",
315 "PECI Agent 0",
316 "PECI Agent 1",
317 "PCH_CHIP_CPU_MAX_TEMP",
318 "PCH_CHIP_TEMP",
319 "PCH_CPU_TEMP",
320 "PCH_MCH_TEMP",
321 "PCH_DIM0_TEMP",
322 "PCH_DIM1_TEMP",
323 "PCH_DIM2_TEMP",
324 "PCH_DIM3_TEMP",
325 "BYTE_TEMP"
326};
327
328#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 329
17296feb 330static int is_word_sized(u16 reg)
bce26c58 331{
ec3e5a16 332 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 333 || (reg & 0xff00) == 0x200)
334 && ((reg & 0x00ff) == 0x50
335 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 336 || (reg & 0x00ff) == 0x55))
337 || (reg & 0xfff0) == 0x630
338 || reg == 0x640 || reg == 0x642
339 || ((reg & 0xfff0) == 0x650
340 && (reg & 0x000f) >= 0x06)
341 || reg == 0x73 || reg == 0x75 || reg == 0x77
342 );
bce26c58
GR		 343}
344
08e7e278
JD		 345/*
346 * Conversions
347 */
348
08c79950
RM		 349/* 1 is PWM mode, output in ms */
350static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
351{
352 return mode ? 100 * reg : 400 * reg;
353}
354
355static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
356{
357 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
358 (msec + 200) / 400), 1, 255);
359}
360
26bc440e 361static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 362{
26bc440e 363 if (reg == 0 || reg == 255)
08e7e278 364 return 0;
26bc440e
GR		 365 return 1350000U / (reg << divreg);
366}
367
368static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
369{
370 if ((reg & 0xff1f) == 0xff1f)
371 return 0;
372
373 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
374
375 if (reg == 0)
376 return 0;
377
378 return 1350000U / reg;
379}
380
381static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
382{
383 if (reg == 0 || reg == 0xffff)
384 return 0;
385
386 /*
387 * Even though the registers are 16 bit wide, the fan divisor
388 * still applies.
389 */
390 return 1350000U / (reg << divreg);
08e7e278
JD		 391}
392
393static inline unsigned int
394div_from_reg(u8 reg)
395{
396 return 1 << reg;
397}
398
8969e84d
GR		 399/*
400 * Some of the voltage inputs have internal scaling, the tables below
401 * contain 8 (the ADC LSB in mV) * scaling factor * 100
402 */
eff7687d
JD		 403static const u16 scale_in_common[10] = {
404 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
405};
406static const u16 scale_in_w83627uhg[9] = {
407 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
408};
cf0676fe 409
eff7687d 410static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 411{
eff7687d 412 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 413}
414
eff7687d 415static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 416{
eff7687d 417 return SENSORS_LIMIT(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0,
e7e1ca6e 418 255);
cf0676fe
RM		 419}
420
08e7e278
JD		 421/*
422 * Data structures and manipulation thereof
423 */
424
425struct w83627ehf_data {
1ea6dd38
DH		 426 int addr; /* IO base of hw monitor block */
427 const char *name;
428
1beeffe4 429 struct device *hwmon_dev;
9a61bf63 430 struct mutex lock;
08e7e278 431
ec3e5a16
GR		 432 u16 reg_temp[NUM_REG_TEMP];
433 u16 reg_temp_over[NUM_REG_TEMP];
434 u16 reg_temp_hyst[NUM_REG_TEMP];
435 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 436 u8 temp_src[NUM_REG_TEMP];
437 const char * const *temp_label;
438
279af1a9
GR		 439 const u16 *REG_PWM;
440 const u16 *REG_TARGET;
441 const u16 *REG_FAN;
442 const u16 *REG_FAN_MIN;
443 const u16 *REG_FAN_START_OUTPUT;
444 const u16 *REG_FAN_STOP_OUTPUT;
445 const u16 *REG_FAN_STOP_TIME;
446 const u16 *REG_FAN_MAX_OUTPUT;
447 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 448 const u16 *scale_in;
da2e0255 449
26bc440e
GR		 450 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
451 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
452
9a61bf63 453 struct mutex update_lock;
08e7e278
JD		 454 char valid; /* !=0 if following fields are valid */
455 unsigned long last_updated; /* In jiffies */
456
457 /* Register values */
83cc8985 458 u8 bank; /* current register bank */
1ea6dd38 459 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 460 u8 in[10]; /* Register value */
461 u8 in_max[10]; /* Register value */
462 u8 in_min[10]; /* Register value */
3382a918 463 unsigned int rpm[5];
ec3e5a16 464 u16 fan_min[5];
08e7e278
JD		 465 u8 fan_div[5];
466 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 467 u8 has_fan_min; /* some fans don't have min register */
26bc440e 468 bool has_fan_div;
da667365 469 u8 temp_type[3];
840e191d 470 s8 temp_offset[3];
ec3e5a16
GR		 471 s16 temp[9];
472 s16 temp_max[9];
473 s16 temp_max_hyst[9];
a4589dbb 474 u32 alarms;
363a12a4 475 u8 caseopen;
08c79950
RM		 476
477 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
478 u8 pwm_enable[4]; /* 1->manual
8969e84d
GR		 479 * 2->thermal cruise mode (also called SmartFan I)
480 * 3->fan speed cruise mode
481 * 4->variable thermal cruise (also called
482 * SmartFan III)
483 * 5->enhanced variable thermal cruise (also called
484 * SmartFan IV)
485 */
b84bb518 486 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 487 u8 pwm_num; /* number of pwm */
08c79950
RM		 488 u8 pwm[4];
489 u8 target_temp[4];
490 u8 tolerance[4];
491
41e9a062
DB		 492 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
493 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
494 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
495 u8 fan_max_output[4]; /* maximum fan speed */
496 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 497
498 u8 vid;
499 u8 vrm;
a157d06d 500
ec3e5a16 501 u16 have_temp;
840e191d 502 u16 have_temp_offset;
eff7687d
JD		 503 u8 in6_skip:1;
504 u8 temp3_val_only:1;
7e630bb5
JD		 505
506#ifdef CONFIG_PM
507 /* Remember extra register values over suspend/resume */
508 u8 vbat;
509 u8 fandiv1;
510 u8 fandiv2;
511#endif
08e7e278
JD		 512};
513
1ea6dd38
DH		 514struct w83627ehf_sio_data {
515 int sioreg;
516 enum kinds kind;
517};
518
83cc8985
GR		 519/*
520 * On older chips, only registers 0x50-0x5f are banked.
521 * On more recent chips, all registers are banked.
522 * Assume that is the case and set the bank number for each access.
523 * Cache the bank number so it only needs to be set if it changes.
524 */
1ea6dd38 525static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 526{
83cc8985
GR		 527 u8 bank = reg >> 8;
528 if (data->bank != bank) {
1ea6dd38 529 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 530 outb_p(bank, data->addr + DATA_REG_OFFSET);
531 data->bank = bank;
08e7e278
JD		 532 }
533}
534
1ea6dd38 535static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 536{
08e7e278
JD		 537 int res, word_sized = is_word_sized(reg);
538
9a61bf63 539 mutex_lock(&data->lock);
08e7e278 540
1ea6dd38
DH		 541 w83627ehf_set_bank(data, reg);
542 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
543 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 544 if (word_sized) {
545 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 546 data->addr + ADDR_REG_OFFSET);
547 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 548 }
08e7e278 549
9a61bf63 550 mutex_unlock(&data->lock);
08e7e278
JD		 551 return res;
552}
553
e7e1ca6e
GR		 554static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
555 u16 value)
08e7e278 556{
08e7e278
JD		 557 int word_sized = is_word_sized(reg);
558
9a61bf63 559 mutex_lock(&data->lock);
08e7e278 560
1ea6dd38
DH		 561 w83627ehf_set_bank(data, reg);
562 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 563 if (word_sized) {
1ea6dd38 564 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 565 outb_p((reg & 0xff) + 1,
1ea6dd38 566 data->addr + ADDR_REG_OFFSET);
08e7e278 567 }
1ea6dd38 568 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 569
9a61bf63 570 mutex_unlock(&data->lock);
08e7e278
JD		 571 return 0;
572}
573
c5794cfa
JD		 574/* We left-align 8-bit temperature values to make the code simpler */
575static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
576{
577 u16 res;
578
579 res = w83627ehf_read_value(data, reg);
580 if (!is_word_sized(reg))
581 res <<= 8;
582
583 return res;
584}
585
586static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
587 u16 value)
588{
589 if (!is_word_sized(reg))
590 value >>= 8;
591 return w83627ehf_write_value(data, reg, value);
592}
593
ec3e5a16
GR		 594/* This function assumes that the caller holds data->update_lock */
595static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
596{
597 u8 reg;
598
599 switch (nr) {
600 case 0:
601 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
602 | (data->fan_div[0] & 0x7);
603 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
604 break;
605 case 1:
606 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
607 | ((data->fan_div[1] << 4) & 0x70);
608 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
58c3667d 609 break;
ec3e5a16
GR		 610 case 2:
611 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
612 | (data->fan_div[2] & 0x7);
613 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
614 break;
615 case 3:
616 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
617 | ((data->fan_div[3] << 4) & 0x70);
618 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
619 break;
620 }
621}
622
08e7e278 623/* This function assumes that the caller holds data->update_lock */
1ea6dd38 624static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 625{
08e7e278
JD		 626 u8 reg;
627
628 switch (nr) {
629 case 0:
1ea6dd38 630 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 631 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 632 /* fan5 input control bit is write only, compute the value */
633 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 634 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
635 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 636 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 637 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 638 break;
639 case 1:
1ea6dd38 640 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 641 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 642 /* fan5 input control bit is write only, compute the value */
643 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 644 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
645 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 646 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 647 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 648 break;
649 case 2:
1ea6dd38 650 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 651 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 652 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
653 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 654 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 655 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 656 break;
657 case 3:
1ea6dd38 658 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 659 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 660 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
661 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 662 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 663 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 664 break;
665 case 4:
1ea6dd38 666 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 667 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 668 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 669 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 670 break;
671 }
672}
673
ec3e5a16
GR		 674static void w83627ehf_write_fan_div_common(struct device *dev,
675 struct w83627ehf_data *data, int nr)
676{
677 struct w83627ehf_sio_data *sio_data = dev->platform_data;
678
679 if (sio_data->kind == nct6776)
680 ; /* no dividers, do nothing */
681 else if (sio_data->kind == nct6775)
682 nct6775_write_fan_div(data, nr);
683 else
684 w83627ehf_write_fan_div(data, nr);
685}
686
687static void nct6775_update_fan_div(struct w83627ehf_data *data)
688{
689 u8 i;
690
691 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
692 data->fan_div[0] = i & 0x7;
693 data->fan_div[1] = (i & 0x70) >> 4;
694 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
695 data->fan_div[2] = i & 0x7;
696 if (data->has_fan & (1<<3))
697 data->fan_div[3] = (i & 0x70) >> 4;
698}
699
ea7be66c
MH		 700static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
701{
702 int i;
703
704 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
705 data->fan_div[0] = (i >> 4) & 0x03;
706 data->fan_div[1] = (i >> 6) & 0x03;
707 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
708 data->fan_div[2] = (i >> 6) & 0x03;
709 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
710 data->fan_div[0] |= (i >> 3) & 0x04;
711 data->fan_div[1] |= (i >> 4) & 0x04;
712 data->fan_div[2] |= (i >> 5) & 0x04;
713 if (data->has_fan & ((1 << 3) | (1 << 4))) {
714 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
715 data->fan_div[3] = i & 0x03;
716 data->fan_div[4] = ((i >> 2) & 0x03)
717 | ((i >> 5) & 0x04);
718 }
719 if (data->has_fan & (1 << 3)) {
720 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
721 data->fan_div[3] |= (i >> 5) & 0x04;
722 }
723}
724
ec3e5a16
GR		 725static void w83627ehf_update_fan_div_common(struct device *dev,
726 struct w83627ehf_data *data)
727{
728 struct w83627ehf_sio_data *sio_data = dev->platform_data;
729
730 if (sio_data->kind == nct6776)
731 ; /* no dividers, do nothing */
732 else if (sio_data->kind == nct6775)
733 nct6775_update_fan_div(data);
734 else
735 w83627ehf_update_fan_div(data);
736}
737
738static void nct6775_update_pwm(struct w83627ehf_data *data)
739{
740 int i;
741 int pwmcfg, fanmodecfg;
742
743 for (i = 0; i < data->pwm_num; i++) {
744 pwmcfg = w83627ehf_read_value(data,
745 W83627EHF_REG_PWM_ENABLE[i]);
746 fanmodecfg = w83627ehf_read_value(data,
747 NCT6775_REG_FAN_MODE[i]);
748 data->pwm_mode[i] =
749 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
750 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
751 data->tolerance[i] = fanmodecfg & 0x0f;
752 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
753 }
754}
755
756static void w83627ehf_update_pwm(struct w83627ehf_data *data)
757{
758 int i;
759 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
760
761 for (i = 0; i < data->pwm_num; i++) {
762 if (!(data->has_fan & (1 << i)))
763 continue;
764
765 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
766 if (i != 1) {
767 pwmcfg = w83627ehf_read_value(data,
768 W83627EHF_REG_PWM_ENABLE[i]);
769 tolerance = w83627ehf_read_value(data,
770 W83627EHF_REG_TOLERANCE[i]);
771 }
772 data->pwm_mode[i] =
773 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
774 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
775 & 3) + 1;
776 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
777
778 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
779 }
780}
781
782static void w83627ehf_update_pwm_common(struct device *dev,
783 struct w83627ehf_data *data)
784{
785 struct w83627ehf_sio_data *sio_data = dev->platform_data;
786
787 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
788 nct6775_update_pwm(data);
789 else
790 w83627ehf_update_pwm(data);
791}
792
08e7e278
JD		 793static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
794{
1ea6dd38 795 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16
GR		 796 struct w83627ehf_sio_data *sio_data = dev->platform_data;
797
08e7e278
JD		 798 int i;
799
9a61bf63 800 mutex_lock(&data->update_lock);
08e7e278 801
6b3e4645 802 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 803 || !data->valid) {
804 /* Fan clock dividers */
ec3e5a16 805 w83627ehf_update_fan_div_common(dev, data);
08e7e278 806
cf0676fe 807 /* Measured voltages and limits */
1ea6dd38 808 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 809 if ((i == 6) && data->in6_skip)
810 continue;
811
1ea6dd38 812 data->in[i] = w83627ehf_read_value(data,
cf0676fe 813 W83627EHF_REG_IN(i));
1ea6dd38 814 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 815 W83627EHF_REG_IN_MIN(i));
1ea6dd38 816 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 817 W83627EHF_REG_IN_MAX(i));
818 }
819
08e7e278
JD		 820 /* Measured fan speeds and limits */
821 for (i = 0; i < 5; i++) {
3382a918
GR		 822 u16 reg;
823
08e7e278
JD		 824 if (!(data->has_fan & (1 << i)))
825 continue;
826
3382a918
GR		 827 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
828 data->rpm[i] = data->fan_from_reg(reg,
829 data->fan_div[i]);
ec3e5a16
GR		 830
831 if (data->has_fan_min & (1 << i))
832 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 833 data->REG_FAN_MIN[i]);
08e7e278 834
8969e84d
GR		 835 /*
836 * If we failed to measure the fan speed and clock
837 * divider can be increased, let's try that for next
838 * time
839 */
26bc440e 840 if (data->has_fan_div
3382a918
GR		 841 && (reg >= 0xff || (sio_data->kind == nct6775
842 && reg == 0x00))
ec3e5a16 843 && data->fan_div[i] < 0x07) {
e7e1ca6e 844 dev_dbg(dev, "Increasing fan%d "
08e7e278 845 "clock divider from %u to %u\n",
33725ad3 846 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 847 div_from_reg(data->fan_div[i] + 1));
848 data->fan_div[i]++;
ec3e5a16 849 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 850 /* Preserve min limit if possible */
ec3e5a16
GR		 851 if ((data->has_fan_min & (1 << i))
852 && data->fan_min[i] >= 2
08e7e278 853 && data->fan_min[i] != 255)
1ea6dd38 854 w83627ehf_write_value(data,
279af1a9 855 data->REG_FAN_MIN[i],
08e7e278
JD		 856 (data->fan_min[i] /= 2));
857 }
858 }
859
ec3e5a16
GR		 860 w83627ehf_update_pwm_common(dev, data);
861
da2e0255
GR		 862 for (i = 0; i < data->pwm_num; i++) {
863 if (!(data->has_fan & (1 << i)))
864 continue;
865
ec3e5a16
GR		 866 data->fan_start_output[i] =
867 w83627ehf_read_value(data,
868 data->REG_FAN_START_OUTPUT[i]);
869 data->fan_stop_output[i] =
870 w83627ehf_read_value(data,
871 data->REG_FAN_STOP_OUTPUT[i]);
872 data->fan_stop_time[i] =
873 w83627ehf_read_value(data,
874 data->REG_FAN_STOP_TIME[i]);
875
876 if (data->REG_FAN_MAX_OUTPUT &&
877 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 878 data->fan_max_output[i] =
879 w83627ehf_read_value(data,
ec3e5a16 880 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 881
ec3e5a16
GR		 882 if (data->REG_FAN_STEP_OUTPUT &&
883 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 884 data->fan_step_output[i] =
885 w83627ehf_read_value(data,
ec3e5a16 886 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 887
08c79950 888 data->target_temp[i] =
1ea6dd38 889 w83627ehf_read_value(data,
279af1a9 890 data->REG_TARGET[i]) &
08c79950 891 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 892 }
893
08e7e278 894 /* Measured temperatures and limits */
d36cf32c
GR		 895 for (i = 0; i < NUM_REG_TEMP; i++) {
896 if (!(data->have_temp & (1 << i)))
897 continue;
c5794cfa 898 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 899 data->reg_temp[i]);
900 if (data->reg_temp_over[i])
901 data->temp_max[i]
c5794cfa 902 = w83627ehf_read_temp(data,
ec3e5a16
GR		 903 data->reg_temp_over[i]);
904 if (data->reg_temp_hyst[i])
905 data->temp_max_hyst[i]
c5794cfa 906 = w83627ehf_read_temp(data,
ec3e5a16 907 data->reg_temp_hyst[i]);
840e191d
GR		 908 if (data->have_temp_offset & (1 << i))
909 data->temp_offset[i]
910 = w83627ehf_read_value(data,
911 W83627EHF_REG_TEMP_OFFSET[i]);
08e7e278
JD		 912 }
913
1ea6dd38 914 data->alarms = w83627ehf_read_value(data,
a4589dbb 915 W83627EHF_REG_ALARM1) |
1ea6dd38 916 (w83627ehf_read_value(data,
a4589dbb 917 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 918 (w83627ehf_read_value(data,
a4589dbb
JD		 919 W83627EHF_REG_ALARM3) << 16);
920
363a12a4
DA		 921 data->caseopen = w83627ehf_read_value(data,
922 W83627EHF_REG_CASEOPEN_DET);
923
08e7e278
JD		 924 data->last_updated = jiffies;
925 data->valid = 1;
926 }
927
9a61bf63 928 mutex_unlock(&data->update_lock);
08e7e278
JD		 929 return data;
930}
931
932/*
933 * Sysfs callback functions
934 */
cf0676fe
RM		 935#define show_in_reg(reg) \
936static ssize_t \
937show_##reg(struct device *dev, struct device_attribute *attr, \
938 char *buf) \
939{ \
940 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 941 struct sensor_device_attribute *sensor_attr = \
942 to_sensor_dev_attr(attr); \
cf0676fe 943 int nr = sensor_attr->index; \
eff7687d
JD		 944 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
945 data->scale_in)); \
cf0676fe
RM		 946}
947show_in_reg(in)
948show_in_reg(in_min)
949show_in_reg(in_max)
950
951#define store_in_reg(REG, reg) \
952static ssize_t \
e7e1ca6e
GR		 953store_in_##reg(struct device *dev, struct device_attribute *attr, \
954 const char *buf, size_t count) \
cf0676fe 955{ \
1ea6dd38 956 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 957 struct sensor_device_attribute *sensor_attr = \
958 to_sensor_dev_attr(attr); \
cf0676fe 959 int nr = sensor_attr->index; \
bce26c58
GR		 960 unsigned long val; \
961 int err; \
179c4fdb 962 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 963 if (err < 0) \
964 return err; \
cf0676fe 965 mutex_lock(&data->update_lock); \
eff7687d 966 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
1ea6dd38 967 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 968 data->in_##reg[nr]); \
969 mutex_unlock(&data->update_lock); \
970 return count; \
971}
972
973store_in_reg(MIN, min)
974store_in_reg(MAX, max)
975
e7e1ca6e
GR		 976static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
977 char *buf)
a4589dbb
JD		 978{
979 struct w83627ehf_data *data = w83627ehf_update_device(dev);
980 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
981 int nr = sensor_attr->index;
982 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
983}
984
cf0676fe
RM		 985static struct sensor_device_attribute sda_in_input[] = {
986 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
987 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
988 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
989 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
990 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
991 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
992 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
993 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
994 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
995 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
996};
997
a4589dbb
JD		 998static struct sensor_device_attribute sda_in_alarm[] = {
999 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
1000 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
1001 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
1002 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
1003 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
1004 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
1005 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
1006 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
1007 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
1008 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
1009};
1010
cf0676fe 1011static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 1012 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
1013 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
1014 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
1015 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
1016 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
1017 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
1018 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
1019 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
1020 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
1021 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 1022};
1023
1024static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 1025 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1026 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1027 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1028 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1029 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1030 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1031 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1032 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1033 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1034 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 1035};
1036
ec3e5a16
GR		 1037static ssize_t
1038show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1039{
1040 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1041 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1042 int nr = sensor_attr->index;
3382a918 1043 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 1044}
1045
1046static ssize_t
1047show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1048{
1049 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1050 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1051 int nr = sensor_attr->index;
1052 return sprintf(buf, "%d\n",
26bc440e
GR		 1053 data->fan_from_reg_min(data->fan_min[nr],
1054 data->fan_div[nr]));
08e7e278 1055}
08e7e278
JD		 1056
1057static ssize_t
412fec82
YM		 1058show_fan_div(struct device *dev, struct device_attribute *attr,
1059 char *buf)
08e7e278
JD		 1060{
1061 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1062 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1063 int nr = sensor_attr->index;
1064 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1065}
1066
1067static ssize_t
412fec82
YM		 1068store_fan_min(struct device *dev, struct device_attribute *attr,
1069 const char *buf, size_t count)
08e7e278 1070{
1ea6dd38 1071 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1072 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1073 int nr = sensor_attr->index;
bce26c58
GR		 1074 unsigned long val;
1075 int err;
08e7e278
JD		 1076 unsigned int reg;
1077 u8 new_div;
1078
179c4fdb 1079 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1080 if (err < 0)
1081 return err;
1082
9a61bf63 1083 mutex_lock(&data->update_lock);
26bc440e
GR		 1084 if (!data->has_fan_div) {
1085 /*
1086 * Only NCT6776F for now, so we know that this is a 13 bit
1087 * register
1088 */
ec3e5a16
GR		 1089 if (!val) {
1090 val = 0xff1f;
1091 } else {
1092 if (val > 1350000U)
1093 val = 135000U;
1094 val = 1350000U / val;
1095 val = (val & 0x1f) | ((val << 3) & 0xff00);
1096 }
1097 data->fan_min[nr] = val;
1098 goto done; /* Leave fan divider alone */
1099 }
08e7e278
JD		 1100 if (!val) {
1101 /* No min limit, alarm disabled */
1102 data->fan_min[nr] = 255;
1103 new_div = data->fan_div[nr]; /* No change */
1104 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1105 } else if ((reg = 1350000U / val) >= 128 * 255) {
8969e84d
GR		 1106 /*
1107 * Speed below this value cannot possibly be represented,
1108 * even with the highest divider (128)
1109 */
08e7e278
JD		 1110 data->fan_min[nr] = 254;
1111 new_div = 7; /* 128 == (1 << 7) */
bce26c58 1112 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
ec3e5a16 1113 "minimum\n", nr + 1, val,
26bc440e 1114 data->fan_from_reg_min(254, 7));
08e7e278 1115 } else if (!reg) {
8969e84d
GR		 1116 /*
1117 * Speed above this value cannot possibly be represented,
1118 * even with the lowest divider (1)
1119 */
08e7e278
JD		 1120 data->fan_min[nr] = 1;
1121 new_div = 0; /* 1 == (1 << 0) */
bce26c58 1122 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
ec3e5a16 1123 "maximum\n", nr + 1, val,
26bc440e 1124 data->fan_from_reg_min(1, 0));
08e7e278 1125 } else {
8969e84d
GR		 1126 /*
1127 * Automatically pick the best divider, i.e. the one such
1128 * that the min limit will correspond to a register value
1129 * in the 96..192 range
1130 */
08e7e278
JD		 1131 new_div = 0;
1132 while (reg > 192 && new_div < 7) {
1133 reg >>= 1;
1134 new_div++;
1135 }
1136 data->fan_min[nr] = reg;
1137 }
1138
8969e84d
GR		 1139 /*
1140 * Write both the fan clock divider (if it changed) and the new
1141 * fan min (unconditionally)
1142 */
08e7e278 1143 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1144 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1145 nr + 1, div_from_reg(data->fan_div[nr]),
1146 div_from_reg(new_div));
1147 data->fan_div[nr] = new_div;
ec3e5a16 1148 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1149 /* Give the chip time to sample a new speed value */
1150 data->last_updated = jiffies;
08e7e278 1151 }
ec3e5a16 1152done:
279af1a9 1153 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1154 data->fan_min[nr]);
9a61bf63 1155 mutex_unlock(&data->update_lock);
08e7e278
JD		 1156
1157 return count;
1158}
1159
412fec82
YM		 1160static struct sensor_device_attribute sda_fan_input[] = {
1161 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1162 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1163 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1164 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1165 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1166};
08e7e278 1167
a4589dbb
JD		 1168static struct sensor_device_attribute sda_fan_alarm[] = {
1169 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1170 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1171 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1172 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1173 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1174};
1175
412fec82
YM		 1176static struct sensor_device_attribute sda_fan_min[] = {
1177 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1178 store_fan_min, 0),
1179 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1180 store_fan_min, 1),
1181 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1182 store_fan_min, 2),
1183 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1184 store_fan_min, 3),
1185 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1186 store_fan_min, 4),
1187};
08e7e278 1188
412fec82
YM		 1189static struct sensor_device_attribute sda_fan_div[] = {
1190 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1191 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1192 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1193 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1194 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1195};
1196
d36cf32c
GR		 1197static ssize_t
1198show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1199{
1200 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1201 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1202 int nr = sensor_attr->index;
1203 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1204}
1205
ec3e5a16 1206#define show_temp_reg(addr, reg) \
08e7e278 1207static ssize_t \
412fec82
YM		 1208show_##reg(struct device *dev, struct device_attribute *attr, \
1209 char *buf) \
08e7e278
JD		 1210{ \
1211 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1212 struct sensor_device_attribute *sensor_attr = \
1213 to_sensor_dev_attr(attr); \
412fec82 1214 int nr = sensor_attr->index; \
c5794cfa 1215 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
08e7e278 1216}
ec3e5a16
GR		 1217show_temp_reg(reg_temp, temp);
1218show_temp_reg(reg_temp_over, temp_max);
1219show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1220
ec3e5a16 1221#define store_temp_reg(addr, reg) \
08e7e278 1222static ssize_t \
412fec82
YM		 1223store_##reg(struct device *dev, struct device_attribute *attr, \
1224 const char *buf, size_t count) \
08e7e278 1225{ \
1ea6dd38 1226 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1227 struct sensor_device_attribute *sensor_attr = \
1228 to_sensor_dev_attr(attr); \
412fec82 1229 int nr = sensor_attr->index; \
bce26c58
GR		 1230 int err; \
1231 long val; \
179c4fdb 1232 err = kstrtol(buf, 10, &val); \
bce26c58
GR		 1233 if (err < 0) \
1234 return err; \
9a61bf63 1235 mutex_lock(&data->update_lock); \
c5794cfa
JD		 1236 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1237 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
9a61bf63 1238 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1239 return count; \
1240}
ec3e5a16
GR		 1241store_temp_reg(reg_temp_over, temp_max);
1242store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1243
840e191d
GR		 1244static ssize_t
1245show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
1246{
1247 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1248 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1249
1250 return sprintf(buf, "%d\n",
1251 data->temp_offset[sensor_attr->index] * 1000);
1252}
1253
1254static ssize_t
1255store_temp_offset(struct device *dev, struct device_attribute *attr,
1256 const char *buf, size_t count)
1257{
1258 struct w83627ehf_data *data = dev_get_drvdata(dev);
1259 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1260 int nr = sensor_attr->index;
1261 long val;
1262 int err;
1263
1264 err = kstrtol(buf, 10, &val);
1265 if (err < 0)
1266 return err;
1267
1268 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
1269
1270 mutex_lock(&data->update_lock);
1271 data->temp_offset[nr] = val;
1272 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[nr], val);
1273 mutex_unlock(&data->update_lock);
1274 return count;
1275}
1276
da667365
JD		 1277static ssize_t
1278show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1279{
1280 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1281 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1282 int nr = sensor_attr->index;
1283 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1284}
1285
a157d06d 1286static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1287 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1288 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1289 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1290 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1291 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1292 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1293 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1294 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1295 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1296};
1297
1298static struct sensor_device_attribute sda_temp_label[] = {
1299 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1300 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1301 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1302 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1303 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1304 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1305 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1306 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1307 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1308};
1309
1310static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1311 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1312 store_temp_max, 0),
bce26c58 1313 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1314 store_temp_max, 1),
bce26c58
GR		 1315 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1316 store_temp_max, 2),
ec3e5a16
GR		 1317 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1318 store_temp_max, 3),
1319 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1320 store_temp_max, 4),
1321 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1322 store_temp_max, 5),
1323 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1324 store_temp_max, 6),
1325 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1326 store_temp_max, 7),
1327 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1328 store_temp_max, 8),
a157d06d
GJ		 1329};
1330
1331static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1332 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1333 store_temp_max_hyst, 0),
bce26c58 1334 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1335 store_temp_max_hyst, 1),
bce26c58
GR		 1336 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1337 store_temp_max_hyst, 2),
ec3e5a16
GR		 1338 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1339 store_temp_max_hyst, 3),
1340 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1341 store_temp_max_hyst, 4),
1342 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1343 store_temp_max_hyst, 5),
1344 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1345 store_temp_max_hyst, 6),
1346 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1347 store_temp_max_hyst, 7),
1348 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1349 store_temp_max_hyst, 8),
a157d06d
GJ		 1350};
1351
1352static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1353 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1354 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1355 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1356};
1357
1358static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1359 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1360 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1361 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1362};
08e7e278 1363
840e191d
GR		 1364static struct sensor_device_attribute sda_temp_offset[] = {
1365 SENSOR_ATTR(temp1_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1366 store_temp_offset, 0),
1367 SENSOR_ATTR(temp2_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1368 store_temp_offset, 1),
1369 SENSOR_ATTR(temp3_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1370 store_temp_offset, 2),
1371};
1372
08c79950 1373#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1374static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1375 char *buf) \
08c79950
RM		 1376{ \
1377 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1378 struct sensor_device_attribute *sensor_attr = \
1379 to_sensor_dev_attr(attr); \
08c79950
RM		 1380 int nr = sensor_attr->index; \
1381 return sprintf(buf, "%d\n", data->reg[nr]); \
1382}
1383
1384show_pwm_reg(pwm_mode)
1385show_pwm_reg(pwm_enable)
1386show_pwm_reg(pwm)
1387
1388static ssize_t
1389store_pwm_mode(struct device *dev, struct device_attribute *attr,
1390 const char *buf, size_t count)
1391{
1ea6dd38 1392 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 1393 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
ad77c3e1 1394 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950 1395 int nr = sensor_attr->index;
bce26c58
GR		 1396 unsigned long val;
1397 int err;
08c79950
RM		 1398 u16 reg;
1399
179c4fdb 1400 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1401 if (err < 0)
1402 return err;
1403
08c79950
RM		 1404 if (val > 1)
1405 return -EINVAL;
ad77c3e1
GR		 1406
1407 /* On NCT67766F, DC mode is only supported for pwm1 */
1408 if (sio_data->kind == nct6776 && nr && val != 1)
1409 return -EINVAL;
1410
08c79950 1411 mutex_lock(&data->update_lock);
1ea6dd38 1412 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1413 data->pwm_mode[nr] = val;
1414 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1415 if (!val)
1416 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1417 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1418 mutex_unlock(&data->update_lock);
1419 return count;
1420}
1421
1422static ssize_t
1423store_pwm(struct device *dev, struct device_attribute *attr,
1424 const char *buf, size_t count)
1425{
1ea6dd38 1426 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1427 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1428 int nr = sensor_attr->index;
bce26c58
GR		 1429 unsigned long val;
1430 int err;
1431
179c4fdb 1432 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1433 if (err < 0)
1434 return err;
1435
1436 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 1437
1438 mutex_lock(&data->update_lock);
1439 data->pwm[nr] = val;
279af1a9 1440 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1441 mutex_unlock(&data->update_lock);
1442 return count;
1443}
1444
1445static ssize_t
1446store_pwm_enable(struct device *dev, struct device_attribute *attr,
1447 const char *buf, size_t count)
1448{
1ea6dd38 1449 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1450 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1451 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1452 int nr = sensor_attr->index;
bce26c58
GR		 1453 unsigned long val;
1454 int err;
08c79950
RM		 1455 u16 reg;
1456
179c4fdb 1457 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1458 if (err < 0)
1459 return err;
1460
b84bb518 1461 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1462 return -EINVAL;
ec3e5a16
GR		 1463 /* SmartFan III mode is not supported on NCT6776F */
1464 if (sio_data->kind == nct6776 && val == 4)
1465 return -EINVAL;
1466
08c79950 1467 mutex_lock(&data->update_lock);
08c79950 1468 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1469 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1470 reg = w83627ehf_read_value(data,
1471 NCT6775_REG_FAN_MODE[nr]);
1472 reg &= 0x0f;
1473 reg |= (val - 1) << 4;
1474 w83627ehf_write_value(data,
1475 NCT6775_REG_FAN_MODE[nr], reg);
1476 } else {
1477 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1478 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1479 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1480 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1481 }
08c79950
RM		 1482 mutex_unlock(&data->update_lock);
1483 return count;
1484}
1485
1486
1487#define show_tol_temp(reg) \
1488static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1489 char *buf) \
1490{ \
1491 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1492 struct sensor_device_attribute *sensor_attr = \
1493 to_sensor_dev_attr(attr); \
08c79950 1494 int nr = sensor_attr->index; \
bce26c58 1495 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1496}
1497
1498show_tol_temp(tolerance)
1499show_tol_temp(target_temp)
1500
1501static ssize_t
1502store_target_temp(struct device *dev, struct device_attribute *attr,
1503 const char *buf, size_t count)
1504{
1ea6dd38 1505 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1506 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1507 int nr = sensor_attr->index;
bce26c58
GR		 1508 long val;
1509 int err;
1510
179c4fdb 1511 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1512 if (err < 0)
1513 return err;
1514
1515 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1516
1517 mutex_lock(&data->update_lock);
1518 data->target_temp[nr] = val;
279af1a9 1519 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1520 mutex_unlock(&data->update_lock);
1521 return count;
1522}
1523
1524static ssize_t
1525store_tolerance(struct device *dev, struct device_attribute *attr,
1526 const char *buf, size_t count)
1527{
1ea6dd38 1528 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1529 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1530 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1531 int nr = sensor_attr->index;
1532 u16 reg;
bce26c58
GR		 1533 long val;
1534 int err;
1535
179c4fdb 1536 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1537 if (err < 0)
1538 return err;
1539
08c79950 1540 /* Limit the temp to 0C - 15C */
bce26c58 1541 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1542
1543 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1544 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1545 /* Limit tolerance further for NCT6776F */
1546 if (sio_data->kind == nct6776 && val > 7)
1547 val = 7;
1548 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1549 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1550 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1551 } else {
1552 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1553 if (nr == 1)
1554 reg = (reg & 0x0f) | (val << 4);
1555 else
1556 reg = (reg & 0xf0) | val;
1557 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1558 }
1559 data->tolerance[nr] = val;
08c79950
RM		 1560 mutex_unlock(&data->update_lock);
1561 return count;
1562}
1563
1564static struct sensor_device_attribute sda_pwm[] = {
1565 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1566 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1567 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1568 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1569};
1570
1571static struct sensor_device_attribute sda_pwm_mode[] = {
1572 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1573 store_pwm_mode, 0),
1574 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1575 store_pwm_mode, 1),
1576 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1577 store_pwm_mode, 2),
1578 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1579 store_pwm_mode, 3),
1580};
1581
1582static struct sensor_device_attribute sda_pwm_enable[] = {
1583 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1584 store_pwm_enable, 0),
1585 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1586 store_pwm_enable, 1),
1587 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1588 store_pwm_enable, 2),
1589 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1590 store_pwm_enable, 3),
1591};
1592
1593static struct sensor_device_attribute sda_target_temp[] = {
1594 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1595 store_target_temp, 0),
1596 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1597 store_target_temp, 1),
1598 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1599 store_target_temp, 2),
1600 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1601 store_target_temp, 3),
1602};
1603
1604static struct sensor_device_attribute sda_tolerance[] = {
1605 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1606 store_tolerance, 0),
1607 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1608 store_tolerance, 1),
1609 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1610 store_tolerance, 2),
1611 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1612 store_tolerance, 3),
1613};
1614
08c79950
RM		 1615/* Smart Fan registers */
1616
1617#define fan_functions(reg, REG) \
1618static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1619 char *buf) \
1620{ \
1621 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1622 struct sensor_device_attribute *sensor_attr = \
1623 to_sensor_dev_attr(attr); \
08c79950
RM		 1624 int nr = sensor_attr->index; \
1625 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1626} \
08c79950
RM		 1627static ssize_t \
1628store_##reg(struct device *dev, struct device_attribute *attr, \
1629 const char *buf, size_t count) \
e7e1ca6e 1630{ \
1ea6dd38 1631 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1632 struct sensor_device_attribute *sensor_attr = \
1633 to_sensor_dev_attr(attr); \
08c79950 1634 int nr = sensor_attr->index; \
bce26c58
GR		 1635 unsigned long val; \
1636 int err; \
179c4fdb 1637 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1638 if (err < 0) \
1639 return err; \
1640 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1641 mutex_lock(&data->update_lock); \
1642 data->reg[nr] = val; \
da2e0255 1643 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1644 mutex_unlock(&data->update_lock); \
1645 return count; \
1646}
1647
41e9a062
DB		 1648fan_functions(fan_start_output, FAN_START_OUTPUT)
1649fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1650fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1651fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1652
1653#define fan_time_functions(reg, REG) \
1654static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1655 char *buf) \
1656{ \
1657 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1658 struct sensor_device_attribute *sensor_attr = \
1659 to_sensor_dev_attr(attr); \
08c79950
RM		 1660 int nr = sensor_attr->index; \
1661 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1662 step_time_from_reg(data->reg[nr], \
1663 data->pwm_mode[nr])); \
08c79950
RM		 1664} \
1665\
1666static ssize_t \
1667store_##reg(struct device *dev, struct device_attribute *attr, \
1668 const char *buf, size_t count) \
1669{ \
1ea6dd38 1670 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1671 struct sensor_device_attribute *sensor_attr = \
1672 to_sensor_dev_attr(attr); \
08c79950 1673 int nr = sensor_attr->index; \
bce26c58
GR		 1674 unsigned long val; \
1675 int err; \
179c4fdb 1676 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1677 if (err < 0) \
1678 return err; \
1679 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1680 mutex_lock(&data->update_lock); \
1681 data->reg[nr] = val; \
33fa9b62 1682 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1683 mutex_unlock(&data->update_lock); \
1684 return count; \
1685} \
1686
1687fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1688
1ea6dd38
DH		 1689static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1690 char *buf)
1691{
1692 struct w83627ehf_data *data = dev_get_drvdata(dev);
1693
1694 return sprintf(buf, "%s\n", data->name);
1695}
1696static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1697
1698static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1699 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1700 store_fan_stop_time, 3),
41e9a062
DB		 1701 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1702 store_fan_start_output, 3),
1703 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1704 store_fan_stop_output, 3),
1705 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1706 store_fan_max_output, 3),
1707 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1708 store_fan_step_output, 3),
08c79950
RM		 1709};
1710
eff7687d
JD		 1711static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1712 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1713 store_fan_stop_time, 2),
1714 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1715 store_fan_start_output, 2),
1716 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1717 store_fan_stop_output, 2),
1718};
1719
08c79950
RM		 1720static struct sensor_device_attribute sda_sf3_arrays[] = {
1721 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1722 store_fan_stop_time, 0),
1723 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1724 store_fan_stop_time, 1),
41e9a062
DB		 1725 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1726 store_fan_start_output, 0),
1727 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1728 store_fan_start_output, 1),
41e9a062
DB		 1729 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1730 store_fan_stop_output, 0),
1731 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1732 store_fan_stop_output, 1),
da2e0255 1733};
41e9a062 1734
da2e0255
GR		 1735
1736/*
1737 * pwm1 and pwm3 don't support max and step settings on all chips.
1738 * Need to check support while generating/removing attribute files.
1739 */
1740static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1741 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1742 store_fan_max_output, 0),
1743 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1744 store_fan_step_output, 0),
41e9a062
DB		 1745 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1746 store_fan_max_output, 1),
1747 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1748 store_fan_step_output, 1),
da2e0255
GR		 1749 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1750 store_fan_max_output, 2),
1751 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1752 store_fan_step_output, 2),
08c79950
RM		 1753};
1754
fc18d6c0
JD		 1755static ssize_t
1756show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1757{
1758 struct w83627ehf_data *data = dev_get_drvdata(dev);
1759 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1760}
1761static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1762
363a12a4
DA		 1763
1764/* Case open detection */
1765
1766static ssize_t
1767show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1768{
1769 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1770
1771 return sprintf(buf, "%d\n",
1772 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1773}
1774
1775static ssize_t
1776clear_caseopen(struct device *dev, struct device_attribute *attr,
1777 const char *buf, size_t count)
1778{
1779 struct w83627ehf_data *data = dev_get_drvdata(dev);
1780 unsigned long val;
1781 u16 reg, mask;
1782
179c4fdb 1783 if (kstrtoul(buf, 10, &val) || val != 0)
363a12a4
DA		 1784 return -EINVAL;
1785
1786 mask = to_sensor_dev_attr_2(attr)->nr;
1787
1788 mutex_lock(&data->update_lock);
1789 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1790 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1791 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1792 data->valid = 0; /* Force cache refresh */
1793 mutex_unlock(&data->update_lock);
1794
1795 return count;
1796}
1797
1798static struct sensor_device_attribute_2 sda_caseopen[] = {
1799 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1800 clear_caseopen, 0x80, 0x10),
1801 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1802 clear_caseopen, 0x40, 0x40),
1803};
1804
08e7e278 1805/*
1ea6dd38 1806 * Driver and device management
08e7e278
JD		 1807 */
1808
c18beb5b
DH		 1809static void w83627ehf_device_remove_files(struct device *dev)
1810{
8969e84d
GR		 1811 /*
1812 * some entries in the following arrays may not have been used in
1813 * device_create_file(), but device_remove_file() will ignore them
1814 */
c18beb5b 1815 int i;
1ea6dd38 1816 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1817
1818 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1819 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1820 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1821 struct sensor_device_attribute *attr =
1822 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1823 if (data->REG_FAN_STEP_OUTPUT &&
1824 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1825 device_remove_file(dev, &attr->dev_attr);
1826 }
eff7687d
JD		 1827 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1828 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
c18beb5b
DH		 1829 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1830 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1831 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1832 if ((i == 6) && data->in6_skip)
1833 continue;
c18beb5b
DH		 1834 device_remove_file(dev, &sda_in_input[i].dev_attr);
1835 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1836 device_remove_file(dev, &sda_in_min[i].dev_attr);
1837 device_remove_file(dev, &sda_in_max[i].dev_attr);
1838 }
1839 for (i = 0; i < 5; i++) {
1840 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1841 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1842 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1843 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1844 }
237c8d2f 1845 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1846 device_remove_file(dev, &sda_pwm[i].dev_attr);
1847 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1848 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1849 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1850 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1851 }
d36cf32c
GR		 1852 for (i = 0; i < NUM_REG_TEMP; i++) {
1853 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1854 continue;
1855 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1856 device_remove_file(dev, &sda_temp_label[i].dev_attr);
eff7687d
JD		 1857 if (i == 2 && data->temp3_val_only)
1858 continue;
a157d06d
GJ		 1859 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1860 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1861 if (i > 2)
1862 continue;
a157d06d
GJ		 1863 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1864 device_remove_file(dev, &sda_temp_type[i].dev_attr);
840e191d 1865 device_remove_file(dev, &sda_temp_offset[i].dev_attr);
a157d06d 1866 }
c18beb5b 1867
363a12a4
DA		 1868 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1869 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1870
1ea6dd38 1871 device_remove_file(dev, &dev_attr_name);
cbe311f2 1872 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1873}
08e7e278 1874
1ea6dd38 1875/* Get the monitoring functions started */
6c931ae1 1876static inline void w83627ehf_init_device(struct w83627ehf_data *data,
bf164c58 1877 enum kinds kind)
08e7e278
JD		 1878{
1879 int i;
da667365 1880 u8 tmp, diode;
08e7e278
JD		 1881
1882 /* Start monitoring is needed */
1ea6dd38 1883 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1884 if (!(tmp & 0x01))
1ea6dd38 1885 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1886 tmp | 0x01);
1887
d36cf32c
GR		 1888 /* Enable temperature sensors if needed */
1889 for (i = 0; i < NUM_REG_TEMP; i++) {
1890 if (!(data->have_temp & (1 << i)))
1891 continue;
ec3e5a16 1892 if (!data->reg_temp_config[i])
d36cf32c 1893 continue;
1ea6dd38 1894 tmp = w83627ehf_read_value(data,
ec3e5a16 1895 data->reg_temp_config[i]);
08e7e278 1896 if (tmp & 0x01)
1ea6dd38 1897 w83627ehf_write_value(data,
ec3e5a16 1898 data->reg_temp_config[i],
08e7e278
JD		 1899 tmp & 0xfe);
1900 }
d3130f0e
JD		 1901
1902 /* Enable VBAT monitoring if needed */
1903 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1904 if (!(tmp & 0x01))
1905 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1906
1907 /* Get thermal sensor types */
bf164c58
JD		 1908 switch (kind) {
1909 case w83627ehf:
1910 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1911 break;
eff7687d
JD		 1912 case w83627uhg:
1913 diode = 0x00;
1914 break;
bf164c58
JD		 1915 default:
1916 diode = 0x70;
1917 }
da667365 1918 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1919 const char *label = NULL;
1920
1921 if (data->temp_label)
1922 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1923
1924 /* Digital source overrides analog type */
bfa02b0d 1925 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1926 data->temp_type[i] = 6;
bfa02b0d 1927 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1928 data->temp_type[i] = 5;
1929 else if ((tmp & (0x02 << i)))
bf164c58 1930 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1931 else
1932 data->temp_type[i] = 4; /* thermistor */
1933 }
08e7e278
JD		 1934}
1935
ec3e5a16
GR		 1936static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1937 int r1, int r2)
1938{
1939 u16 tmp;
1940
1941 tmp = data->temp_src[r1];
1942 data->temp_src[r1] = data->temp_src[r2];
1943 data->temp_src[r2] = tmp;
1944
1945 tmp = data->reg_temp[r1];
1946 data->reg_temp[r1] = data->reg_temp[r2];
1947 data->reg_temp[r2] = tmp;
1948
1949 tmp = data->reg_temp_over[r1];
1950 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1951 data->reg_temp_over[r2] = tmp;
1952
1953 tmp = data->reg_temp_hyst[r1];
1954 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1955 data->reg_temp_hyst[r2] = tmp;
1956
1957 tmp = data->reg_temp_config[r1];
1958 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1959 data->reg_temp_config[r2] = tmp;
1960}
1961
6c931ae1 1962static void
6ba71de5
JD		 1963w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1964{
1965 int i;
1966
1967 for (i = 0; i < n_temp; i++) {
1968 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1969 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1970 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1971 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1972 }
1973}
1974
6c931ae1 1975static void
03f5de2b
JD		 1976w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1977 struct w83627ehf_data *data)
1978{
1979 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1980
eff7687d
JD		 1981 /* The W83627UHG is simple, only two fan inputs, no config */
1982 if (sio_data->kind == w83627uhg) {
1983 data->has_fan = 0x03; /* fan1 and fan2 */
1984 data->has_fan_min = 0x03;
1985 return;
1986 }
1987
03f5de2b
JD		 1988 superio_enter(sio_data->sioreg);
1989
1990 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1991 if (sio_data->kind == nct6775) {
1992 /* On NCT6775, fan4 shares pins with the fdc interface */
1993 fan3pin = 1;
1994 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1995 fan4min = 0;
1996 fan5pin = 0;
1997 } else if (sio_data->kind == nct6776) {
585c0fd8
GR		 1998 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
1999
2000 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2001 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
2002
2003 if (regval & 0x80)
2004 fan3pin = gpok;
2005 else
2006 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2007
2008 if (regval & 0x40)
2009 fan4pin = gpok;
2010 else
2011 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2012
2013 if (regval & 0x20)
2014 fan5pin = gpok;
2015 else
2016 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2017
03f5de2b
JD		 2018 fan4min = fan4pin;
2019 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2020 fan3pin = 1;
2021 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
2022 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2023 fan4min = fan4pin;
2024 } else {
2025 fan3pin = 1;
2026 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2027 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2028 fan4min = fan4pin;
2029 }
2030
2031 superio_exit(sio_data->sioreg);
2032
2033 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2034 data->has_fan |= (fan3pin << 2);
2035 data->has_fan_min |= (fan3pin << 2);
2036
2037 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2038 /*
2039 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
2040 * register
2041 */
2042 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2043 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2044 } else {
2045 /*
2046 * It looks like fan4 and fan5 pins can be alternatively used
2047 * as fan on/off switches, but fan5 control is write only :/
2048 * We assume that if the serial interface is disabled, designers
2049 * connected fan5 as input unless they are emitting log 1, which
2050 * is not the default.
2051 */
2052 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2053 if ((regval & (1 << 2)) && fan4pin) {
2054 data->has_fan |= (1 << 3);
2055 data->has_fan_min |= (1 << 3);
2056 }
2057 if (!(regval & (1 << 1)) && fan5pin) {
2058 data->has_fan |= (1 << 4);
2059 data->has_fan_min |= (1 << 4);
2060 }
2061 }
2062}
2063
6c931ae1 2064static int w83627ehf_probe(struct platform_device *pdev)
08e7e278 2065{
1ea6dd38
DH		 2066 struct device *dev = &pdev->dev;
2067 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 2068 struct w83627ehf_data *data;
1ea6dd38 2069 struct resource *res;
03f5de2b 2070 u8 en_vrm10;
08e7e278
JD		 2071 int i, err = 0;
2072
1ea6dd38
DH		 2073 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2074 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 2075 err = -EBUSY;
1ea6dd38
DH		 2076 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2077 (unsigned long)res->start,
2078 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 2079 goto exit;
2080 }
2081
32260d94
GR		 2082 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2083 GFP_KERNEL);
e7e1ca6e 2084 if (!data) {
08e7e278
JD		 2085 err = -ENOMEM;
2086 goto exit_release;
2087 }
08e7e278 2088
1ea6dd38 2089 data->addr = res->start;
9a61bf63 2090 mutex_init(&data->lock);
9a61bf63 2091 mutex_init(&data->update_lock);
1ea6dd38 2092 data->name = w83627ehf_device_names[sio_data->kind];
3300fb4f 2093 data->bank = 0xff; /* Force initial bank selection */
1ea6dd38 2094 platform_set_drvdata(pdev, data);
08e7e278 2095
237c8d2f
GJ		 2096 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2097 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
eff7687d
JD		 2098 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2099 switch (sio_data->kind) {
2100 default:
2101 data->pwm_num = 4;
2102 break;
2103 case w83667hg:
2104 case w83667hg_b:
2105 case nct6775:
2106 case nct6776:
2107 data->pwm_num = 3;
2108 break;
2109 case w83627uhg:
2110 data->pwm_num = 2;
2111 break;
2112 }
08e7e278 2113
6ba71de5 2114 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 2115 data->have_temp = 0x07;
ec3e5a16
GR		 2116
2117 /* Deal with temperature register setup first. */
2118 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2119 int mask = 0;
2120
2121 /*
2122 * Display temperature sensor output only if it monitors
2123 * a source other than one already reported. Always display
2124 * first three temperature registers, though.
2125 */
2126 for (i = 0; i < NUM_REG_TEMP; i++) {
2127 u8 src;
2128
2129 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2130 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2131 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2132 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2133
2134 src = w83627ehf_read_value(data,
2135 NCT6775_REG_TEMP_SOURCE[i]);
2136 src &= 0x1f;
2137 if (src && !(mask & (1 << src))) {
2138 data->have_temp |= 1 << i;
2139 mask |= 1 << src;
2140 }
2141
2142 data->temp_src[i] = src;
2143
2144 /*
2145 * Now do some register swapping if index 0..2 don't
2146 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2147 * Idea is to have the first three attributes
2148 * report SYSTIN, CPUIN, and AUXIN if possible
2149 * without overriding the basic system configuration.
2150 */
2151 if (i > 0 && data->temp_src[0] != 1
2152 && data->temp_src[i] == 1)
2153 w82627ehf_swap_tempreg(data, 0, i);
2154 if (i > 1 && data->temp_src[1] != 2
2155 && data->temp_src[i] == 2)
2156 w82627ehf_swap_tempreg(data, 1, i);
2157 if (i > 2 && data->temp_src[2] != 3
2158 && data->temp_src[i] == 3)
2159 w82627ehf_swap_tempreg(data, 2, i);
2160 }
2161 if (sio_data->kind == nct6776) {
2162 /*
2163 * On NCT6776, AUXTIN and VIN3 pins are shared.
2164 * Only way to detect it is to check if AUXTIN is used
2165 * as a temperature source, and if that source is
2166 * enabled.
2167 *
2168 * If that is the case, disable in6, which reports VIN3.
2169 * Otherwise disable temp3.
2170 */
2171 if (data->temp_src[2] == 3) {
2172 u8 reg;
2173
2174 if (data->reg_temp_config[2])
2175 reg = w83627ehf_read_value(data,
2176 data->reg_temp_config[2]);
2177 else
2178 reg = 0; /* Assume AUXTIN is used */
2179
2180 if (reg & 0x01)
2181 data->have_temp &= ~(1 << 2);
2182 else
2183 data->in6_skip = 1;
2184 }
02309ad2
GR		 2185 data->temp_label = nct6776_temp_label;
2186 } else {
2187 data->temp_label = nct6775_temp_label;
ec3e5a16 2188 }
840e191d
GR		 2189 data->have_temp_offset = data->have_temp & 0x07;
2190 for (i = 0; i < 3; i++) {
2191 if (data->temp_src[i] > 3)
2192 data->have_temp_offset &= ~(1 << i);
2193 }
d36cf32c
GR		 2194 } else if (sio_data->kind == w83667hg_b) {
2195 u8 reg;
2196
6ba71de5
JD		 2197 w83627ehf_set_temp_reg_ehf(data, 4);
2198
ec3e5a16
GR		 2199 /*
2200 * Temperature sources are selected with bank 0, registers 0x49
2201 * and 0x4a.
2202 */
d36cf32c
GR		 2203 reg = w83627ehf_read_value(data, 0x4a);
2204 data->temp_src[0] = reg >> 5;
2205 reg = w83627ehf_read_value(data, 0x49);
2206 data->temp_src[1] = reg & 0x07;
ec3e5a16 2207 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 2208
2209 /*
2210 * W83667HG-B has another temperature register at 0x7e.
2211 * The temperature source is selected with register 0x7d.
2212 * Support it if the source differs from already reported
2213 * sources.
2214 */
2215 reg = w83627ehf_read_value(data, 0x7d);
2216 reg &= 0x07;
2217 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2218 && reg != data->temp_src[2]) {
2219 data->temp_src[3] = reg;
2220 data->have_temp |= 1 << 3;
2221 }
2222
2223 /*
2224 * Chip supports either AUXTIN or VIN3. Try to find out which
2225 * one.
2226 */
2227 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2228 if (data->temp_src[2] == 2 && (reg & 0x01))
2229 data->have_temp &= ~(1 << 2);
2230
2231 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2232 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2233 data->in6_skip = 1;
2234
eff7687d 2235 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2236 data->have_temp_offset = data->have_temp & 0x07;
2237 for (i = 0; i < 3; i++) {
2238 if (data->temp_src[i] > 2)
2239 data->have_temp_offset &= ~(1 << i);
2240 }
eff7687d
JD		 2241 } else if (sio_data->kind == w83627uhg) {
2242 u8 reg;
2243
2244 w83627ehf_set_temp_reg_ehf(data, 3);
2245
2246 /*
aacb6b00 2247 * Temperature sources for temp2 and temp3 are selected with
eff7687d
JD		 2248 * bank 0, registers 0x49 and 0x4a.
2249 */
2250 data->temp_src[0] = 0; /* SYSTIN */
2251 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2252 /* Adjust to have the same mapping as other source registers */
2253 if (reg == 0)
aacb6b00 2254 data->temp_src[1] = 1;
eff7687d 2255 else if (reg >= 2 && reg <= 5)
aacb6b00 2256 data->temp_src[1] = reg + 2;
eff7687d
JD		 2257 else /* should never happen */
2258 data->have_temp &= ~(1 << 1);
2259 reg = w83627ehf_read_value(data, 0x4a);
2260 data->temp_src[2] = reg >> 5;
2261
2262 /*
2263 * Skip temp3 if source is invalid or the same as temp1
2264 * or temp2.
2265 */
2266 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2267 data->temp_src[2] == data->temp_src[0] ||
2268 ((data->have_temp & (1 << 1)) &&
2269 data->temp_src[2] == data->temp_src[1]))
2270 data->have_temp &= ~(1 << 2);
2271 else
2272 data->temp3_val_only = 1; /* No limit regs */
2273
2274 data->in6_skip = 1; /* No VIN3 */
2275
d36cf32c 2276 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2277 data->have_temp_offset = data->have_temp & 0x03;
2278 for (i = 0; i < 3; i++) {
2279 if (data->temp_src[i] > 1)
2280 data->have_temp_offset &= ~(1 << i);
2281 }
ec3e5a16 2282 } else {
6ba71de5
JD		 2283 w83627ehf_set_temp_reg_ehf(data, 3);
2284
ec3e5a16 2285 /* Temperature sources are fixed */
6ba71de5
JD		 2286
2287 if (sio_data->kind == w83667hg) {
2288 u8 reg;
2289
2290 /*
2291 * Chip supports either AUXTIN or VIN3. Try to find
2292 * out which one.
2293 */
2294 reg = w83627ehf_read_value(data,
2295 W83627EHF_REG_TEMP_CONFIG[2]);
2296 if (reg & 0x01)
2297 data->have_temp &= ~(1 << 2);
2298 else
2299 data->in6_skip = 1;
ec3e5a16 2300 }
840e191d 2301 data->have_temp_offset = data->have_temp & 0x07;
a157d06d
GJ		 2302 }
2303
ec3e5a16 2304 if (sio_data->kind == nct6775) {
26bc440e
GR		 2305 data->has_fan_div = true;
2306 data->fan_from_reg = fan_from_reg16;
2307 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2308 data->REG_PWM = NCT6775_REG_PWM;
2309 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2310 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2311 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2312 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2313 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2314 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2315 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2316 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2317 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2318 data->has_fan_div = false;
2319 data->fan_from_reg = fan_from_reg13;
2320 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2321 data->REG_PWM = NCT6775_REG_PWM;
2322 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2323 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2324 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2325 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2326 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2327 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2328 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2329 data->has_fan_div = true;
2330 data->fan_from_reg = fan_from_reg8;
2331 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2332 data->REG_PWM = W83627EHF_REG_PWM;
2333 data->REG_TARGET = W83627EHF_REG_TARGET;
2334 data->REG_FAN = W83627EHF_REG_FAN;
2335 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2336 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2337 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2338 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2339 data->REG_FAN_MAX_OUTPUT =
2340 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2341 data->REG_FAN_STEP_OUTPUT =
2342 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2343 } else {
26bc440e
GR		 2344 data->has_fan_div = true;
2345 data->fan_from_reg = fan_from_reg8;
2346 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2347 data->REG_PWM = W83627EHF_REG_PWM;
2348 data->REG_TARGET = W83627EHF_REG_TARGET;
2349 data->REG_FAN = W83627EHF_REG_FAN;
2350 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2351 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2352 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2353 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2354 data->REG_FAN_MAX_OUTPUT =
2355 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2356 data->REG_FAN_STEP_OUTPUT =
2357 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2358 }
da2e0255 2359
eff7687d
JD		 2360 /* Setup input voltage scaling factors */
2361 if (sio_data->kind == w83627uhg)
2362 data->scale_in = scale_in_w83627uhg;
2363 else
2364 data->scale_in = scale_in_common;
2365
08e7e278 2366 /* Initialize the chip */
bf164c58 2367 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2368
fc18d6c0
JD		 2369 data->vrm = vid_which_vrm();
2370 superio_enter(sio_data->sioreg);
fc18d6c0 2371 /* Read VID value */
ec3e5a16
GR		 2372 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2373 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
8969e84d
GR		 2374 /*
2375 * W83667HG has different pins for VID input and output, so
2376 * we can get the VID input values directly at logical device D
2377 * 0xe3.
2378 */
237c8d2f
GJ		 2379 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2380 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2381 err = device_create_file(dev, &dev_attr_cpu0_vid);
2382 if (err)
2383 goto exit_release;
eff7687d 2384 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 2385 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2386 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
8969e84d
GR		 2387 /*
2388 * Set VID input sensibility if needed. In theory the
2389 * BIOS should have set it, but in practice it's not
2390 * always the case. We only do it for the W83627EHF/EHG
2391 * because the W83627DHG is more complex in this
2392 * respect.
2393 */
237c8d2f
GJ		 2394 if (sio_data->kind == w83627ehf) {
2395 en_vrm10 = superio_inb(sio_data->sioreg,
2396 SIO_REG_EN_VRM10);
2397 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2398 dev_warn(dev, "Setting VID input "
2399 "voltage to TTL\n");
2400 superio_outb(sio_data->sioreg,
2401 SIO_REG_EN_VRM10,
2402 en_vrm10 & ~0x08);
2403 } else if (!(en_vrm10 & 0x08)
2404 && data->vrm == 100) {
2405 dev_warn(dev, "Setting VID input "
2406 "voltage to VRM10\n");
2407 superio_outb(sio_data->sioreg,
2408 SIO_REG_EN_VRM10,
2409 en_vrm10 | 0x08);
2410 }
2411 }
2412
2413 data->vid = superio_inb(sio_data->sioreg,
2414 SIO_REG_VID_DATA);
2415 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2416 data->vid &= 0x3f;
2417
2418 err = device_create_file(dev, &dev_attr_cpu0_vid);
2419 if (err)
2420 goto exit_release;
2421 } else {
2422 dev_info(dev, "VID pins in output mode, CPU VID not "
2423 "available\n");
2424 }
fc18d6c0
JD		 2425 }
2426
d42e869a
ID		 2427 if (fan_debounce &&
2428 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2429 u8 tmp;
2430
2431 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2432 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2433 if (sio_data->kind == nct6776)
2434 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2435 0x3e | tmp);
2436 else
2437 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2438 0x1e | tmp);
2439 pr_info("Enabled fan debounce for chip %s\n", data->name);
2440 }
2441
1ea6dd38 2442 superio_exit(sio_data->sioreg);
08c79950 2443
03f5de2b 2444 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 2445
ea7be66c 2446 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2447 w83627ehf_update_fan_div_common(dev, data);
2448
b84bb518
GR		 2449 /* Read pwm data to save original values */
2450 w83627ehf_update_pwm_common(dev, data);
2451 for (i = 0; i < data->pwm_num; i++)
2452 data->pwm_enable_orig[i] = data->pwm_enable[i];
2453
08e7e278 2454 /* Register sysfs hooks */
e7e1ca6e
GR		 2455 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2456 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2457 if (err)
c18beb5b 2458 goto exit_remove;
e7e1ca6e 2459 }
08c79950 2460
da2e0255
GR		 2461 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2462 struct sensor_device_attribute *attr =
2463 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2464 if (data->REG_FAN_STEP_OUTPUT &&
2465 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2466 err = device_create_file(dev, &attr->dev_attr);
2467 if (err)
2468 goto exit_remove;
2469 }
2470 }
eff7687d
JD		 2471 /* if fan3 and fan4 are enabled create the sf3 files for them */
2472 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2473 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2474 err = device_create_file(dev,
2475 &sda_sf3_arrays_fan3[i].dev_attr);
2476 if (err)
2477 goto exit_remove;
2478 }
237c8d2f 2479 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2480 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2481 err = device_create_file(dev,
2482 &sda_sf3_arrays_fan4[i].dev_attr);
2483 if (err)
c18beb5b
DH		 2484 goto exit_remove;
2485 }
08c79950 2486
a157d06d
GJ		 2487 for (i = 0; i < data->in_num; i++) {
2488 if ((i == 6) && data->in6_skip)
2489 continue;
c18beb5b
DH		 2490 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2491 || (err = device_create_file(dev,
2492 &sda_in_alarm[i].dev_attr))
2493 || (err = device_create_file(dev,
2494 &sda_in_min[i].dev_attr))
2495 || (err = device_create_file(dev,
2496 &sda_in_max[i].dev_attr)))
2497 goto exit_remove;
a157d06d 2498 }
cf0676fe 2499
412fec82 2500 for (i = 0; i < 5; i++) {
08c79950 2501 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2502 if ((err = device_create_file(dev,
2503 &sda_fan_input[i].dev_attr))
2504 || (err = device_create_file(dev,
ec3e5a16 2505 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2506 goto exit_remove;
ec3e5a16
GR		 2507 if (sio_data->kind != nct6776) {
2508 err = device_create_file(dev,
2509 &sda_fan_div[i].dev_attr);
2510 if (err)
2511 goto exit_remove;
2512 }
2513 if (data->has_fan_min & (1 << i)) {
2514 err = device_create_file(dev,
2515 &sda_fan_min[i].dev_attr);
2516 if (err)
2517 goto exit_remove;
2518 }
237c8d2f 2519 if (i < data->pwm_num &&
c18beb5b
DH		 2520 ((err = device_create_file(dev,
2521 &sda_pwm[i].dev_attr))
2522 || (err = device_create_file(dev,
2523 &sda_pwm_mode[i].dev_attr))
2524 || (err = device_create_file(dev,
2525 &sda_pwm_enable[i].dev_attr))
2526 || (err = device_create_file(dev,
2527 &sda_target_temp[i].dev_attr))
2528 || (err = device_create_file(dev,
2529 &sda_tolerance[i].dev_attr))))
2530 goto exit_remove;
08c79950 2531 }
08e7e278 2532 }
08c79950 2533
d36cf32c
GR		 2534 for (i = 0; i < NUM_REG_TEMP; i++) {
2535 if (!(data->have_temp & (1 << i)))
a157d06d 2536 continue;
d36cf32c
GR		 2537 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2538 if (err)
2539 goto exit_remove;
2540 if (data->temp_label) {
2541 err = device_create_file(dev,
2542 &sda_temp_label[i].dev_attr);
2543 if (err)
2544 goto exit_remove;
2545 }
eff7687d
JD		 2546 if (i == 2 && data->temp3_val_only)
2547 continue;
ec3e5a16
GR		 2548 if (data->reg_temp_over[i]) {
2549 err = device_create_file(dev,
2550 &sda_temp_max[i].dev_attr);
2551 if (err)
2552 goto exit_remove;
2553 }
2554 if (data->reg_temp_hyst[i]) {
2555 err = device_create_file(dev,
2556 &sda_temp_max_hyst[i].dev_attr);
2557 if (err)
2558 goto exit_remove;
2559 }
d36cf32c 2560 if (i > 2)
ec3e5a16
GR		 2561 continue;
2562 if ((err = device_create_file(dev,
a157d06d
GJ		 2563 &sda_temp_alarm[i].dev_attr))
2564 || (err = device_create_file(dev,
2565 &sda_temp_type[i].dev_attr)))
c18beb5b 2566 goto exit_remove;
840e191d
GR		 2567 if (data->have_temp_offset & (1 << i)) {
2568 err = device_create_file(dev,
2569 &sda_temp_offset[i].dev_attr);
2570 if (err)
2571 goto exit_remove;
2572 }
a157d06d 2573 }
c18beb5b 2574
363a12a4
DA		 2575 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2576 if (err)
2577 goto exit_remove;
2578
2579 if (sio_data->kind == nct6776) {
2580 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2581 if (err)
2582 goto exit_remove;
2583 }
2584
1ea6dd38
DH		 2585 err = device_create_file(dev, &dev_attr_name);
2586 if (err)
2587 goto exit_remove;
2588
1beeffe4
TJ		 2589 data->hwmon_dev = hwmon_device_register(dev);
2590 if (IS_ERR(data->hwmon_dev)) {
2591 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2592 goto exit_remove;
2593 }
08e7e278
JD		 2594
2595 return 0;
2596
c18beb5b
DH		 2597exit_remove:
2598 w83627ehf_device_remove_files(dev);
08e7e278 2599exit_release:
32260d94 2600 platform_set_drvdata(pdev, NULL);
1ea6dd38 2601 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2602exit:
2603 return err;
2604}
2605
281dfd0b 2606static int w83627ehf_remove(struct platform_device *pdev)
08e7e278 2607{
1ea6dd38 2608 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2609
1beeffe4 2610 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2611 w83627ehf_device_remove_files(&pdev->dev);
2612 release_region(data->addr, IOREGION_LENGTH);
2613 platform_set_drvdata(pdev, NULL);
08e7e278
JD		 2614
2615 return 0;
2616}
2617
7e630bb5
JD		 2618#ifdef CONFIG_PM
2619static int w83627ehf_suspend(struct device *dev)
2620{
2621 struct w83627ehf_data *data = w83627ehf_update_device(dev);
2622 struct w83627ehf_sio_data *sio_data = dev->platform_data;
2623
2624 mutex_lock(&data->update_lock);
2625 data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
2626 if (sio_data->kind == nct6775) {
2627 data->fandiv1 = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
2628 data->fandiv2 = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
2629 }
2630 mutex_unlock(&data->update_lock);
2631
2632 return 0;
2633}
2634
2635static int w83627ehf_resume(struct device *dev)
2636{
2637 struct w83627ehf_data *data = dev_get_drvdata(dev);
2638 struct w83627ehf_sio_data *sio_data = dev->platform_data;
2639 int i;
2640
2641 mutex_lock(&data->update_lock);
2642 data->bank = 0xff; /* Force initial bank selection */
2643
2644 /* Restore limits */
2645 for (i = 0; i < data->in_num; i++) {
2646 if ((i == 6) && data->in6_skip)
2647 continue;
2648
2649 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
2650 data->in_min[i]);
2651 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2652 data->in_max[i]);
2653 }
2654
2655 for (i = 0; i < 5; i++) {
2656 if (!(data->has_fan_min & (1 << i)))
2657 continue;
2658
2659 w83627ehf_write_value(data, data->REG_FAN_MIN[i],
2660 data->fan_min[i]);
2661 }
2662
2663 for (i = 0; i < NUM_REG_TEMP; i++) {
2664 if (!(data->have_temp & (1 << i)))
2665 continue;
2666
2667 if (data->reg_temp_over[i])
2668 w83627ehf_write_temp(data, data->reg_temp_over[i],
2669 data->temp_max[i]);
2670 if (data->reg_temp_hyst[i])
2671 w83627ehf_write_temp(data, data->reg_temp_hyst[i],
2672 data->temp_max_hyst[i]);
2673 if (data->have_temp_offset & (1 << i))
2674 w83627ehf_write_value(data,
2675 W83627EHF_REG_TEMP_OFFSET[i],
2676 data->temp_offset[i]);
2677 }
2678
2679 /* Restore other settings */
2680 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
2681 if (sio_data->kind == nct6775) {
2682 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
2683 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
2684 }
2685
2686 /* Force re-reading all values */
2687 data->valid = 0;
2688 mutex_unlock(&data->update_lock);
2689
2690 return 0;
2691}
2692
2693static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
2694 .suspend = w83627ehf_suspend,
2695 .resume = w83627ehf_resume,
2696};
2697
2698#define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
2699#else
2700#define W83627EHF_DEV_PM_OPS NULL
2701#endif /* CONFIG_PM */
2702
1ea6dd38 2703static struct platform_driver w83627ehf_driver = {
cdaf7934 2704 .driver = {
87218842 2705 .owner = THIS_MODULE,
1ea6dd38 2706 .name = DRVNAME,
7e630bb5 2707 .pm = W83627EHF_DEV_PM_OPS,
cdaf7934 2708 },
1ea6dd38 2709 .probe = w83627ehf_probe,
9e5e9b7a 2710 .remove = w83627ehf_remove,
08e7e278
JD		 2711};
2712
1ea6dd38
DH		 2713/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2714static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2715 struct w83627ehf_sio_data *sio_data)
08e7e278 2716{
6f7805a8
UKK		 2717 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2718 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2719 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2720 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2721 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2722 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2723 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2724 static const char sio_name_NCT6775[] __initconst = "NCT6775F";
2725 static const char sio_name_NCT6776[] __initconst = "NCT6776F";
1ea6dd38 2726
08e7e278 2727 u16 val;
1ea6dd38 2728 const char *sio_name;
08e7e278 2729
1ea6dd38 2730 superio_enter(sioaddr);
08e7e278 2731
67b671bc
JD		 2732 if (force_id)
2733 val = force_id;
2734 else
2735 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2736 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2737 switch (val & SIO_ID_MASK) {
657c93b1 2738 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2739 sio_data->kind = w83627ehf;
2740 sio_name = sio_name_W83627EHF;
2741 break;
657c93b1 2742 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2743 sio_data->kind = w83627ehf;
2744 sio_name = sio_name_W83627EHG;
2745 break;
2746 case SIO_W83627DHG_ID:
2747 sio_data->kind = w83627dhg;
2748 sio_name = sio_name_W83627DHG;
657c93b1 2749 break;
c1e48dce
JD		 2750 case SIO_W83627DHG_P_ID:
2751 sio_data->kind = w83627dhg_p;
2752 sio_name = sio_name_W83627DHG_P;
2753 break;
eff7687d
JD		 2754 case SIO_W83627UHG_ID:
2755 sio_data->kind = w83627uhg;
2756 sio_name = sio_name_W83627UHG;
2757 break;
237c8d2f
GJ		 2758 case SIO_W83667HG_ID:
2759 sio_data->kind = w83667hg;
2760 sio_name = sio_name_W83667HG;
2761 break;
c39aedaf
GR		 2762 case SIO_W83667HG_B_ID:
2763 sio_data->kind = w83667hg_b;
2764 sio_name = sio_name_W83667HG_B;
2765 break;
ec3e5a16
GR		 2766 case SIO_NCT6775_ID:
2767 sio_data->kind = nct6775;
2768 sio_name = sio_name_NCT6775;
2769 break;
2770 case SIO_NCT6776_ID:
2771 sio_data->kind = nct6776;
2772 sio_name = sio_name_NCT6776;
2773 break;
657c93b1 2774 default:
9f66036b 2775 if (val != 0xffff)
abdc6fd1 2776 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2777 superio_exit(sioaddr);
08e7e278
JD		 2778 return -ENODEV;
2779 }
2780
1ea6dd38
DH		 2781 /* We have a known chip, find the HWM I/O address */
2782 superio_select(sioaddr, W83627EHF_LD_HWM);
2783 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2784 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2785 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2786 if (*addr == 0) {
abdc6fd1 2787 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2788 superio_exit(sioaddr);
08e7e278
JD		 2789 return -ENODEV;
2790 }
2791
2792 /* Activate logical device if needed */
1ea6dd38 2793 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2794 if (!(val & 0x01)) {
e7e1ca6e
GR		 2795 pr_warn("Forcibly enabling Super-I/O. "
2796 "Sensor is probably unusable.\n");
1ea6dd38 2797 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2798 }
1ea6dd38
DH		 2799
2800 superio_exit(sioaddr);
abdc6fd1 2801 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2802 sio_data->sioreg = sioaddr;
08e7e278 2803
08e7e278
JD		 2804 return 0;
2805}
2806
8969e84d
GR		 2807/*
2808 * when Super-I/O functions move to a separate file, the Super-I/O
1ea6dd38
DH		 2809 * bus will manage the lifetime of the device and this module will only keep
2810 * track of the w83627ehf driver. But since we platform_device_alloc(), we
8969e84d
GR		 2811 * must keep track of the device
2812 */
1ea6dd38
DH		 2813static struct platform_device *pdev;
2814
08e7e278
JD		 2815static int __init sensors_w83627ehf_init(void)
2816{
1ea6dd38
DH		 2817 int err;
2818 unsigned short address;
2819 struct resource res;
2820 struct w83627ehf_sio_data sio_data;
2821
8969e84d
GR		 2822 /*
2823 * initialize sio_data->kind and sio_data->sioreg.
1ea6dd38
DH		 2824 *
2825 * when Super-I/O functions move to a separate file, the Super-I/O
2826 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
8969e84d
GR		 2827 * w83627ehf hardware monitor, and call probe()
2828 */
1ea6dd38
DH		 2829 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2830 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2831 return -ENODEV;
2832
1ea6dd38
DH		 2833 err = platform_driver_register(&w83627ehf_driver);
2834 if (err)
2835 goto exit;
2836
e7e1ca6e
GR		 2837 pdev = platform_device_alloc(DRVNAME, address);
2838 if (!pdev) {
1ea6dd38 2839 err = -ENOMEM;
abdc6fd1 2840 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2841 goto exit_unregister;
2842 }
2843
2844 err = platform_device_add_data(pdev, &sio_data,
2845 sizeof(struct w83627ehf_sio_data));
2846 if (err) {
abdc6fd1 2847 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2848 goto exit_device_put;
2849 }
2850
2851 memset(&res, 0, sizeof(res));
2852 res.name = DRVNAME;
2853 res.start = address + IOREGION_OFFSET;
2854 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2855 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2856
2857 err = acpi_check_resource_conflict(&res);
2858 if (err)
18632f84 2859 goto exit_device_put;
b9acb64a 2860
1ea6dd38
DH		 2861 err = platform_device_add_resources(pdev, &res, 1);
2862 if (err) {
abdc6fd1 2863 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2864 goto exit_device_put;
2865 }
2866
2867 /* platform_device_add calls probe() */
2868 err = platform_device_add(pdev);
2869 if (err) {
abdc6fd1 2870 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2871 goto exit_device_put;
2872 }
2873
2874 return 0;
2875
2876exit_device_put:
2877 platform_device_put(pdev);
2878exit_unregister:
2879 platform_driver_unregister(&w83627ehf_driver);
2880exit:
2881 return err;
08e7e278
JD		 2882}
2883
2884static void __exit sensors_w83627ehf_exit(void)
2885{
1ea6dd38
DH		 2886 platform_device_unregister(pdev);
2887 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2888}
2889
2890MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2891MODULE_DESCRIPTION("W83627EHF driver");
2892MODULE_LICENSE("GPL");
2893
2894module_init(sensors_w83627ehf_init);
2895module_exit(sensors_w83627ehf_exit);
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