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74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
08e7e278 2/*
8969e84d
GR		 3 * w83627ehf - Driver for the hardware monitoring functionality of
4 * the Winbond W83627EHF Super-I/O chip
7c81c60f 5 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
8969e84d
GR		 6 * Copyright (C) 2006 Yuan Mu (Winbond),
7 * Rudolf Marek <r.marek@assembler.cz>
8 * David Hubbard <david.c.hubbard@gmail.com>
9 * Daniel J Blueman <daniel.blueman@gmail.com>
10 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
11 *
12 * Shamelessly ripped from the w83627hf driver
13 * Copyright (C) 2003 Mark Studebaker
14 *
15 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
16 * in testing and debugging this driver.
17 *
18 * This driver also supports the W83627EHG, which is the lead-free
19 * version of the W83627EHF.
20 *
8969e84d
GR		 21 * Supports the following chips:
22 *
23 * Chip #vin #fan #pwm #temp chip IDs man ID
24 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
25 * 0x8860 0xa1
26 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
27 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
28 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
29 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
30 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
31 * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
32 * nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
33 */
08e7e278 34
abdc6fd1
JP		 35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
08e7e278
JD		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/slab.h>
1ea6dd38
DH		 40#include <linux/jiffies.h>
41#include <linux/platform_device.h>
943b0830 42#include <linux/hwmon.h>
412fec82 43#include <linux/hwmon-sysfs.h>
fc18d6c0 44#include <linux/hwmon-vid.h>
943b0830 45#include <linux/err.h>
9a61bf63 46#include <linux/mutex.h>
b9acb64a 47#include <linux/acpi.h>
6055fae8 48#include <linux/io.h>
08e7e278
JD		 49#include "lm75.h"
50
eff7687d
JD		 51enum kinds {
52 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
53 w83667hg, w83667hg_b, nct6775, nct6776,
54};
08e7e278 55
1ea6dd38 56/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 57static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 58 "w83627ehf",
59 "w83627dhg",
c1e48dce 60 "w83627dhg",
eff7687d 61 "w83627uhg",
237c8d2f 62 "w83667hg",
c39aedaf 63 "w83667hg",
ec3e5a16
GR		 64 "nct6775",
65 "nct6776",
1ea6dd38
DH		 66};
67
67b671bc
JD		 68static unsigned short force_id;
69module_param(force_id, ushort, 0);
70MODULE_PARM_DESC(force_id, "Override the detected device ID");
71
d42e869a
ID		 72static unsigned short fan_debounce;
73module_param(fan_debounce, ushort, 0);
74MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
75
1ea6dd38 76#define DRVNAME "w83627ehf"
08e7e278 77
657c93b1 78/*
1ea6dd38 79 * Super-I/O constants and functions
657c93b1 80 */
08e7e278
JD		 81
82#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 83#define W83667HG_LD_VID 0x0d
08e7e278
JD		 84
85#define SIO_REG_LDSEL 0x07 /* Logical device select */
86#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 87#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 88#define SIO_REG_ENABLE 0x30 /* Logical device enable */
89#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 90#define SIO_REG_VID_CTRL 0xF0 /* VID control */
91#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 92
657c93b1
DH		 93#define SIO_W83627EHF_ID 0x8850
94#define SIO_W83627EHG_ID 0x8860
95#define SIO_W83627DHG_ID 0xa020
c1e48dce 96#define SIO_W83627DHG_P_ID 0xb070
eff7687d 97#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 98#define SIO_W83667HG_ID 0xa510
c39aedaf 99#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 100#define SIO_NCT6775_ID 0xb470
101#define SIO_NCT6776_ID 0xc330
657c93b1 102#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 103
104static inline void
1ea6dd38 105superio_outb(int ioreg, int reg, int val)
08e7e278 106{
1ea6dd38
DH		 107 outb(reg, ioreg);
108 outb(val, ioreg + 1);
08e7e278
JD		 109}
110
111static inline int
1ea6dd38 112superio_inb(int ioreg, int reg)
08e7e278 113{
1ea6dd38
DH		 114 outb(reg, ioreg);
115 return inb(ioreg + 1);
08e7e278
JD		 116}
117
118static inline void
1ea6dd38 119superio_select(int ioreg, int ld)
08e7e278 120{
1ea6dd38
DH		 121 outb(SIO_REG_LDSEL, ioreg);
122 outb(ld, ioreg + 1);
08e7e278
JD		 123}
124
0d023530 125static inline int
1ea6dd38 126superio_enter(int ioreg)
08e7e278 127{
0d023530
KS		 128 if (!request_muxed_region(ioreg, 2, DRVNAME))
129 return -EBUSY;
130
1ea6dd38
DH		 131 outb(0x87, ioreg);
132 outb(0x87, ioreg);
0d023530
KS		 133
134 return 0;
08e7e278
JD		 135}
136
137static inline void
1ea6dd38 138superio_exit(int ioreg)
08e7e278 139{
022b75a3 140 outb(0xaa, ioreg);
1ea6dd38
DH		 141 outb(0x02, ioreg);
142 outb(0x02, ioreg + 1);
0d023530 143 release_region(ioreg, 2);
08e7e278
JD		 144}
145
146/*
147 * ISA constants
148 */
149
e7e1ca6e 150#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 151#define IOREGION_OFFSET 5
152#define IOREGION_LENGTH 2
1ea6dd38
DH		 153#define ADDR_REG_OFFSET 0
154#define DATA_REG_OFFSET 1
08e7e278
JD		 155
156#define W83627EHF_REG_BANK 0x4E
157#define W83627EHF_REG_CONFIG 0x40
657c93b1 158
8969e84d
GR		 159/*
160 * Not currently used:
657c93b1
DH		 161 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
162 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
163 * REG_MAN_ID is at port 0x4f
8969e84d
GR		 164 * REG_CHIP_ID is at port 0x58
165 */
08e7e278
JD		 166
167static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
168static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
169
cf0676fe
RM		 170/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
171#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
172 (0x554 + (((nr) - 7) * 2)))
173#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
174 (0x555 + (((nr) - 7) * 2)))
175#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
176 (0x550 + (nr) - 7))
177
d36cf32c
GR		 178static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
179static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
180static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
181static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 182
183/* Fan clock dividers are spread over the following five registers */
184#define W83627EHF_REG_FANDIV1 0x47
185#define W83627EHF_REG_FANDIV2 0x4B
186#define W83627EHF_REG_VBAT 0x5D
187#define W83627EHF_REG_DIODE 0x59
188#define W83627EHF_REG_SMI_OVT 0x4C
189
ec3e5a16
GR		 190/* NCT6775F has its own fan divider registers */
191#define NCT6775_REG_FANDIV1 0x506
192#define NCT6775_REG_FANDIV2 0x507
d42e869a 193#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 194
a4589dbb
JD		 195#define W83627EHF_REG_ALARM1 0x459
196#define W83627EHF_REG_ALARM2 0x45A
197#define W83627EHF_REG_ALARM3 0x45B
198
363a12a4
DA		 199#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
200#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
201
08c79950 202/* SmartFan registers */
41e9a062
DB		 203#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
204#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
205
08c79950
RM		 206/* DC or PWM output fan configuration */
207static const u8 W83627EHF_REG_PWM_ENABLE[] = {
208 0x04, /* SYS FAN0 output mode and PWM mode */
209 0x04, /* CPU FAN0 output mode and PWM mode */
210 0x12, /* AUX FAN mode */
41e9a062 211 0x62, /* CPU FAN1 mode */
08c79950
RM		 212};
213
214static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
215static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
216
217/* FAN Duty Cycle, be used to control */
279af1a9
GR		 218static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
219static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 220static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
221
08c79950 222/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 223static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
224static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
225static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 226
279af1a9 227static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 228 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 229static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 230 = { 0xff, 0x68, 0xff, 0x6a };
231
279af1a9
GR		 232static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
233static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
234 = { 0x68, 0x6a, 0x6c };
08c79950 235
840e191d
GR		 236static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
237
ec3e5a16
GR		 238static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
239static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
240static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
241static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
242static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
243static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
244static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
245static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 246static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 247static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
248
249static const u16 NCT6775_REG_TEMP[]
250 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
251static const u16 NCT6775_REG_TEMP_CONFIG[]
252 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
253static const u16 NCT6775_REG_TEMP_HYST[]
254 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
255static const u16 NCT6775_REG_TEMP_OVER[]
256 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
257static const u16 NCT6775_REG_TEMP_SOURCE[]
258 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
259
d36cf32c
GR		 260static const char *const w83667hg_b_temp_label[] = {
261 "SYSTIN",
262 "CPUTIN",
263 "AUXTIN",
264 "AMDTSI",
265 "PECI Agent 1",
266 "PECI Agent 2",
267 "PECI Agent 3",
268 "PECI Agent 4"
269};
270
ec3e5a16
GR		 271static const char *const nct6775_temp_label[] = {
272 "",
273 "SYSTIN",
274 "CPUTIN",
275 "AUXTIN",
276 "AMD SB-TSI",
277 "PECI Agent 0",
278 "PECI Agent 1",
279 "PECI Agent 2",
280 "PECI Agent 3",
281 "PECI Agent 4",
282 "PECI Agent 5",
283 "PECI Agent 6",
284 "PECI Agent 7",
285 "PCH_CHIP_CPU_MAX_TEMP",
286 "PCH_CHIP_TEMP",
287 "PCH_CPU_TEMP",
288 "PCH_MCH_TEMP",
289 "PCH_DIM0_TEMP",
290 "PCH_DIM1_TEMP",
291 "PCH_DIM2_TEMP",
292 "PCH_DIM3_TEMP"
293};
294
295static const char *const nct6776_temp_label[] = {
296 "",
297 "SYSTIN",
298 "CPUTIN",
299 "AUXTIN",
300 "SMBUSMASTER 0",
301 "SMBUSMASTER 1",
302 "SMBUSMASTER 2",
303 "SMBUSMASTER 3",
304 "SMBUSMASTER 4",
305 "SMBUSMASTER 5",
306 "SMBUSMASTER 6",
307 "SMBUSMASTER 7",
308 "PECI Agent 0",
309 "PECI Agent 1",
310 "PCH_CHIP_CPU_MAX_TEMP",
311 "PCH_CHIP_TEMP",
312 "PCH_CPU_TEMP",
313 "PCH_MCH_TEMP",
314 "PCH_DIM0_TEMP",
315 "PCH_DIM1_TEMP",
316 "PCH_DIM2_TEMP",
317 "PCH_DIM3_TEMP",
318 "BYTE_TEMP"
319};
320
321#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 322
17296feb 323static int is_word_sized(u16 reg)
bce26c58 324{
ec3e5a16 325 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 326 || (reg & 0xff00) == 0x200)
327 && ((reg & 0x00ff) == 0x50
328 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 329 || (reg & 0x00ff) == 0x55))
330 || (reg & 0xfff0) == 0x630
331 || reg == 0x640 || reg == 0x642
332 || ((reg & 0xfff0) == 0x650
333 && (reg & 0x000f) >= 0x06)
334 || reg == 0x73 || reg == 0x75 || reg == 0x77
335 );
bce26c58
GR		 336}
337
08e7e278
JD		 338/*
339 * Conversions
340 */
341
08c79950
RM		 342/* 1 is PWM mode, output in ms */
343static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
344{
345 return mode ? 100 * reg : 400 * reg;
346}
347
348static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
349{
2a844c14
GR		 350 return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
351 1, 255);
08c79950
RM		 352}
353
26bc440e 354static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 355{
26bc440e 356 if (reg == 0 || reg == 255)
08e7e278 357 return 0;
26bc440e
GR		 358 return 1350000U / (reg << divreg);
359}
360
361static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
362{
363 if ((reg & 0xff1f) == 0xff1f)
364 return 0;
365
366 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
367
368 if (reg == 0)
369 return 0;
370
371 return 1350000U / reg;
372}
373
374static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
375{
376 if (reg == 0 || reg == 0xffff)
377 return 0;
378
379 /*
380 * Even though the registers are 16 bit wide, the fan divisor
381 * still applies.
382 */
383 return 1350000U / (reg << divreg);
08e7e278
JD		 384}
385
386static inline unsigned int
387div_from_reg(u8 reg)
388{
389 return 1 << reg;
390}
391
8969e84d
GR		 392/*
393 * Some of the voltage inputs have internal scaling, the tables below
394 * contain 8 (the ADC LSB in mV) * scaling factor * 100
395 */
eff7687d
JD		 396static const u16 scale_in_common[10] = {
397 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
398};
399static const u16 scale_in_w83627uhg[9] = {
400 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
401};
cf0676fe 402
eff7687d 403static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 404{
eff7687d 405 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 406}
407
eff7687d 408static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 409{
2a844c14 410 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
cf0676fe
RM		 411}
412
08e7e278
JD		 413/*
414 * Data structures and manipulation thereof
415 */
416
417struct w83627ehf_data {
1ea6dd38
DH		 418 int addr; /* IO base of hw monitor block */
419 const char *name;
266cd583 420 enum kinds kind; /* Convenience copy of sio_data->kind */
1ea6dd38 421
9a61bf63 422 struct mutex lock;
08e7e278 423
ec3e5a16
GR		 424 u16 reg_temp[NUM_REG_TEMP];
425 u16 reg_temp_over[NUM_REG_TEMP];
426 u16 reg_temp_hyst[NUM_REG_TEMP];
427 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 428 u8 temp_src[NUM_REG_TEMP];
429 const char * const *temp_label;
430
279af1a9
GR		 431 const u16 *REG_PWM;
432 const u16 *REG_TARGET;
433 const u16 *REG_FAN;
434 const u16 *REG_FAN_MIN;
435 const u16 *REG_FAN_START_OUTPUT;
436 const u16 *REG_FAN_STOP_OUTPUT;
437 const u16 *REG_FAN_STOP_TIME;
438 const u16 *REG_FAN_MAX_OUTPUT;
439 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 440 const u16 *scale_in;
da2e0255 441
26bc440e
GR		 442 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
443 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
444
9a61bf63 445 struct mutex update_lock;
08e7e278
JD		 446 char valid; /* !=0 if following fields are valid */
447 unsigned long last_updated; /* In jiffies */
448
449 /* Register values */
83cc8985 450 u8 bank; /* current register bank */
1ea6dd38 451 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 452 u8 in[10]; /* Register value */
453 u8 in_max[10]; /* Register value */
454 u8 in_min[10]; /* Register value */
3382a918 455 unsigned int rpm[5];
ec3e5a16 456 u16 fan_min[5];
08e7e278
JD		 457 u8 fan_div[5];
458 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 459 u8 has_fan_min; /* some fans don't have min register */
26bc440e 460 bool has_fan_div;
da667365 461 u8 temp_type[3];
840e191d 462 s8 temp_offset[3];
ec3e5a16
GR		 463 s16 temp[9];
464 s16 temp_max[9];
465 s16 temp_max_hyst[9];
a4589dbb 466 u32 alarms;
363a12a4 467 u8 caseopen;
08c79950
RM		 468
469 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
470 u8 pwm_enable[4]; /* 1->manual
8969e84d
GR		 471 * 2->thermal cruise mode (also called SmartFan I)
472 * 3->fan speed cruise mode
473 * 4->variable thermal cruise (also called
474 * SmartFan III)
475 * 5->enhanced variable thermal cruise (also called
476 * SmartFan IV)
477 */
b84bb518 478 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 479 u8 pwm_num; /* number of pwm */
08c79950
RM		 480 u8 pwm[4];
481 u8 target_temp[4];
482 u8 tolerance[4];
483
41e9a062
DB		 484 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
485 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
486 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
487 u8 fan_max_output[4]; /* maximum fan speed */
488 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 489
490 u8 vid;
491 u8 vrm;
a157d06d 492
ec3e5a16 493 u16 have_temp;
840e191d 494 u16 have_temp_offset;
eff7687d
JD		 495 u8 in6_skip:1;
496 u8 temp3_val_only:1;
266cd583 497 u8 have_vid:1;
7e630bb5
JD		 498
499#ifdef CONFIG_PM
500 /* Remember extra register values over suspend/resume */
501 u8 vbat;
502 u8 fandiv1;
503 u8 fandiv2;
504#endif
08e7e278
JD		 505};
506
1ea6dd38
DH		 507struct w83627ehf_sio_data {
508 int sioreg;
509 enum kinds kind;
510};
511
83cc8985
GR		 512/*
513 * On older chips, only registers 0x50-0x5f are banked.
514 * On more recent chips, all registers are banked.
515 * Assume that is the case and set the bank number for each access.
516 * Cache the bank number so it only needs to be set if it changes.
517 */
1ea6dd38 518static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 519{
83cc8985
GR		 520 u8 bank = reg >> 8;
521 if (data->bank != bank) {
1ea6dd38 522 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 523 outb_p(bank, data->addr + DATA_REG_OFFSET);
524 data->bank = bank;
08e7e278
JD		 525 }
526}
527
1ea6dd38 528static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 529{
08e7e278
JD		 530 int res, word_sized = is_word_sized(reg);
531
9a61bf63 532 mutex_lock(&data->lock);
08e7e278 533
1ea6dd38
DH		 534 w83627ehf_set_bank(data, reg);
535 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
536 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 537 if (word_sized) {
538 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 539 data->addr + ADDR_REG_OFFSET);
540 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 541 }
08e7e278 542
9a61bf63 543 mutex_unlock(&data->lock);
08e7e278
JD		 544 return res;
545}
546
e7e1ca6e
GR		 547static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
548 u16 value)
08e7e278 549{
08e7e278
JD		 550 int word_sized = is_word_sized(reg);
551
9a61bf63 552 mutex_lock(&data->lock);
08e7e278 553
1ea6dd38
DH		 554 w83627ehf_set_bank(data, reg);
555 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 556 if (word_sized) {
1ea6dd38 557 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 558 outb_p((reg & 0xff) + 1,
1ea6dd38 559 data->addr + ADDR_REG_OFFSET);
08e7e278 560 }
1ea6dd38 561 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 562
9a61bf63 563 mutex_unlock(&data->lock);
08e7e278
JD		 564 return 0;
565}
566
c5794cfa
JD		 567/* We left-align 8-bit temperature values to make the code simpler */
568static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
569{
570 u16 res;
571
572 res = w83627ehf_read_value(data, reg);
573 if (!is_word_sized(reg))
574 res <<= 8;
575
576 return res;
577}
578
579static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
580 u16 value)
581{
582 if (!is_word_sized(reg))
583 value >>= 8;
584 return w83627ehf_write_value(data, reg, value);
585}
586
ec3e5a16
GR		 587/* This function assumes that the caller holds data->update_lock */
588static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
589{
590 u8 reg;
591
592 switch (nr) {
593 case 0:
594 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
595 | (data->fan_div[0] & 0x7);
596 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
597 break;
598 case 1:
599 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
600 | ((data->fan_div[1] << 4) & 0x70);
601 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
58c3667d 602 break;
ec3e5a16
GR		 603 case 2:
604 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
605 | (data->fan_div[2] & 0x7);
606 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
607 break;
608 case 3:
609 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
610 | ((data->fan_div[3] << 4) & 0x70);
611 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
612 break;
613 }
614}
615
08e7e278 616/* This function assumes that the caller holds data->update_lock */
1ea6dd38 617static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 618{
08e7e278
JD		 619 u8 reg;
620
621 switch (nr) {
622 case 0:
1ea6dd38 623 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 624 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 625 /* fan5 input control bit is write only, compute the value */
626 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 627 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
628 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 629 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 630 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 631 break;
632 case 1:
1ea6dd38 633 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 634 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 635 /* fan5 input control bit is write only, compute the value */
636 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 637 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
638 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 639 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 640 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 641 break;
642 case 2:
1ea6dd38 643 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 644 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 645 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
646 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 647 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 648 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 649 break;
650 case 3:
1ea6dd38 651 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 652 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 653 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
654 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 655 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 656 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 657 break;
658 case 4:
1ea6dd38 659 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 660 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 661 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 662 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 663 break;
664 }
665}
666
ec3e5a16
GR		 667static void w83627ehf_write_fan_div_common(struct device *dev,
668 struct w83627ehf_data *data, int nr)
669{
266cd583 670 if (data->kind == nct6776)
ec3e5a16 671 ; /* no dividers, do nothing */
266cd583 672 else if (data->kind == nct6775)
ec3e5a16
GR		 673 nct6775_write_fan_div(data, nr);
674 else
675 w83627ehf_write_fan_div(data, nr);
676}
677
678static void nct6775_update_fan_div(struct w83627ehf_data *data)
679{
680 u8 i;
681
682 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
683 data->fan_div[0] = i & 0x7;
684 data->fan_div[1] = (i & 0x70) >> 4;
685 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
686 data->fan_div[2] = i & 0x7;
687 if (data->has_fan & (1<<3))
688 data->fan_div[3] = (i & 0x70) >> 4;
689}
690
ea7be66c
MH		 691static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
692{
693 int i;
694
695 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
696 data->fan_div[0] = (i >> 4) & 0x03;
697 data->fan_div[1] = (i >> 6) & 0x03;
698 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
699 data->fan_div[2] = (i >> 6) & 0x03;
700 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
701 data->fan_div[0] |= (i >> 3) & 0x04;
702 data->fan_div[1] |= (i >> 4) & 0x04;
703 data->fan_div[2] |= (i >> 5) & 0x04;
704 if (data->has_fan & ((1 << 3) | (1 << 4))) {
705 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
706 data->fan_div[3] = i & 0x03;
707 data->fan_div[4] = ((i >> 2) & 0x03)
708 | ((i >> 5) & 0x04);
709 }
710 if (data->has_fan & (1 << 3)) {
711 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
712 data->fan_div[3] |= (i >> 5) & 0x04;
713 }
714}
715
ec3e5a16
GR		 716static void w83627ehf_update_fan_div_common(struct device *dev,
717 struct w83627ehf_data *data)
718{
266cd583 719 if (data->kind == nct6776)
ec3e5a16 720 ; /* no dividers, do nothing */
266cd583 721 else if (data->kind == nct6775)
ec3e5a16
GR		 722 nct6775_update_fan_div(data);
723 else
724 w83627ehf_update_fan_div(data);
725}
726
727static void nct6775_update_pwm(struct w83627ehf_data *data)
728{
729 int i;
730 int pwmcfg, fanmodecfg;
731
732 for (i = 0; i < data->pwm_num; i++) {
733 pwmcfg = w83627ehf_read_value(data,
734 W83627EHF_REG_PWM_ENABLE[i]);
735 fanmodecfg = w83627ehf_read_value(data,
736 NCT6775_REG_FAN_MODE[i]);
737 data->pwm_mode[i] =
738 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
739 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
740 data->tolerance[i] = fanmodecfg & 0x0f;
741 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
742 }
743}
744
745static void w83627ehf_update_pwm(struct w83627ehf_data *data)
746{
747 int i;
748 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
749
750 for (i = 0; i < data->pwm_num; i++) {
751 if (!(data->has_fan & (1 << i)))
752 continue;
753
754 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
755 if (i != 1) {
756 pwmcfg = w83627ehf_read_value(data,
757 W83627EHF_REG_PWM_ENABLE[i]);
758 tolerance = w83627ehf_read_value(data,
759 W83627EHF_REG_TOLERANCE[i]);
760 }
761 data->pwm_mode[i] =
762 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
763 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
764 & 3) + 1;
765 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
766
767 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
768 }
769}
770
771static void w83627ehf_update_pwm_common(struct device *dev,
772 struct w83627ehf_data *data)
773{
a8b3a3a5 774 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 775
776 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
777 nct6775_update_pwm(data);
778 else
779 w83627ehf_update_pwm(data);
780}
781
08e7e278
JD		 782static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
783{
1ea6dd38 784 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 785 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08e7e278
JD		 786 int i;
787
9a61bf63 788 mutex_lock(&data->update_lock);
08e7e278 789
6b3e4645 790 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 791 || !data->valid) {
792 /* Fan clock dividers */
ec3e5a16 793 w83627ehf_update_fan_div_common(dev, data);
08e7e278 794
cf0676fe 795 /* Measured voltages and limits */
1ea6dd38 796 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 797 if ((i == 6) && data->in6_skip)
798 continue;
799
1ea6dd38 800 data->in[i] = w83627ehf_read_value(data,
cf0676fe 801 W83627EHF_REG_IN(i));
1ea6dd38 802 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 803 W83627EHF_REG_IN_MIN(i));
1ea6dd38 804 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 805 W83627EHF_REG_IN_MAX(i));
806 }
807
08e7e278
JD		 808 /* Measured fan speeds and limits */
809 for (i = 0; i < 5; i++) {
3382a918
GR		 810 u16 reg;
811
08e7e278
JD		 812 if (!(data->has_fan & (1 << i)))
813 continue;
814
3382a918
GR		 815 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
816 data->rpm[i] = data->fan_from_reg(reg,
817 data->fan_div[i]);
ec3e5a16
GR		 818
819 if (data->has_fan_min & (1 << i))
820 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 821 data->REG_FAN_MIN[i]);
08e7e278 822
8969e84d
GR		 823 /*
824 * If we failed to measure the fan speed and clock
825 * divider can be increased, let's try that for next
826 * time
827 */
26bc440e 828 if (data->has_fan_div
3382a918
GR		 829 && (reg >= 0xff || (sio_data->kind == nct6775
830 && reg == 0x00))
ec3e5a16 831 && data->fan_div[i] < 0x07) {
b55f3757
GR		 832 dev_dbg(dev,
833 "Increasing fan%d clock divider from %u to %u\n",
33725ad3 834 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 835 div_from_reg(data->fan_div[i] + 1));
836 data->fan_div[i]++;
ec3e5a16 837 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 838 /* Preserve min limit if possible */
ec3e5a16
GR		 839 if ((data->has_fan_min & (1 << i))
840 && data->fan_min[i] >= 2
08e7e278 841 && data->fan_min[i] != 255)
1ea6dd38 842 w83627ehf_write_value(data,
279af1a9 843 data->REG_FAN_MIN[i],
08e7e278
JD		 844 (data->fan_min[i] /= 2));
845 }
846 }
847
ec3e5a16
GR		 848 w83627ehf_update_pwm_common(dev, data);
849
da2e0255
GR		 850 for (i = 0; i < data->pwm_num; i++) {
851 if (!(data->has_fan & (1 << i)))
852 continue;
853
ec3e5a16
GR		 854 data->fan_start_output[i] =
855 w83627ehf_read_value(data,
856 data->REG_FAN_START_OUTPUT[i]);
857 data->fan_stop_output[i] =
858 w83627ehf_read_value(data,
859 data->REG_FAN_STOP_OUTPUT[i]);
860 data->fan_stop_time[i] =
861 w83627ehf_read_value(data,
862 data->REG_FAN_STOP_TIME[i]);
863
864 if (data->REG_FAN_MAX_OUTPUT &&
865 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 866 data->fan_max_output[i] =
867 w83627ehf_read_value(data,
ec3e5a16 868 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 869
ec3e5a16
GR		 870 if (data->REG_FAN_STEP_OUTPUT &&
871 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 872 data->fan_step_output[i] =
873 w83627ehf_read_value(data,
ec3e5a16 874 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 875
08c79950 876 data->target_temp[i] =
1ea6dd38 877 w83627ehf_read_value(data,
279af1a9 878 data->REG_TARGET[i]) &
08c79950 879 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 880 }
881
08e7e278 882 /* Measured temperatures and limits */
d36cf32c
GR		 883 for (i = 0; i < NUM_REG_TEMP; i++) {
884 if (!(data->have_temp & (1 << i)))
885 continue;
c5794cfa 886 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 887 data->reg_temp[i]);
888 if (data->reg_temp_over[i])
889 data->temp_max[i]
c5794cfa 890 = w83627ehf_read_temp(data,
ec3e5a16
GR		 891 data->reg_temp_over[i]);
892 if (data->reg_temp_hyst[i])
893 data->temp_max_hyst[i]
c5794cfa 894 = w83627ehf_read_temp(data,
ec3e5a16 895 data->reg_temp_hyst[i]);
45633fb3
JD		 896 if (i > 2)
897 continue;
840e191d
GR		 898 if (data->have_temp_offset & (1 << i))
899 data->temp_offset[i]
900 = w83627ehf_read_value(data,
901 W83627EHF_REG_TEMP_OFFSET[i]);
08e7e278
JD		 902 }
903
1ea6dd38 904 data->alarms = w83627ehf_read_value(data,
a4589dbb 905 W83627EHF_REG_ALARM1) |
1ea6dd38 906 (w83627ehf_read_value(data,
a4589dbb 907 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 908 (w83627ehf_read_value(data,
a4589dbb
JD		 909 W83627EHF_REG_ALARM3) << 16);
910
363a12a4
DA		 911 data->caseopen = w83627ehf_read_value(data,
912 W83627EHF_REG_CASEOPEN_DET);
913
08e7e278
JD		 914 data->last_updated = jiffies;
915 data->valid = 1;
916 }
917
9a61bf63 918 mutex_unlock(&data->update_lock);
08e7e278
JD		 919 return data;
920}
921
cf0676fe 922#define store_in_reg(REG, reg) \
266cd583
DDAG		 923static int \
924store_in_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
925 long val) \
cf0676fe 926{ \
266cd583
DDAG		 927 if (val < 0) \
928 return -EINVAL; \
cf0676fe 929 mutex_lock(&data->update_lock); \
266cd583
DDAG		 930 data->in_##reg[channel] = in_to_reg(val, channel, data->scale_in); \
931 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
932 data->in_##reg[channel]); \
cf0676fe 933 mutex_unlock(&data->update_lock); \
266cd583 934 return 0; \
cf0676fe
RM		 935}
936
937store_in_reg(MIN, min)
938store_in_reg(MAX, max)
939
266cd583
DDAG		 940static int
941store_fan_min(struct device *dev, struct w83627ehf_data *data, int channel,
942 long val)
08e7e278 943{
08e7e278
JD		 944 unsigned int reg;
945 u8 new_div;
946
266cd583
DDAG		 947 if (val < 0)
948 return -EINVAL;
bce26c58 949
9a61bf63 950 mutex_lock(&data->update_lock);
26bc440e
GR		 951 if (!data->has_fan_div) {
952 /*
953 * Only NCT6776F for now, so we know that this is a 13 bit
954 * register
955 */
ec3e5a16
GR		 956 if (!val) {
957 val = 0xff1f;
958 } else {
959 if (val > 1350000U)
960 val = 135000U;
961 val = 1350000U / val;
962 val = (val & 0x1f) | ((val << 3) & 0xff00);
963 }
266cd583 964 data->fan_min[channel] = val;
ec3e5a16
GR		 965 goto done; /* Leave fan divider alone */
966 }
08e7e278
JD		 967 if (!val) {
968 /* No min limit, alarm disabled */
266cd583
DDAG		 969 data->fan_min[channel] = 255;
970 new_div = data->fan_div[channel]; /* No change */
971 dev_info(dev, "fan%u low limit and alarm disabled\n",
972 channel + 1);
08e7e278 973 } else if ((reg = 1350000U / val) >= 128 * 255) {
8969e84d
GR		 974 /*
975 * Speed below this value cannot possibly be represented,
976 * even with the highest divider (128)
977 */
266cd583 978 data->fan_min[channel] = 254;
08e7e278 979 new_div = 7; /* 128 == (1 << 7) */
b55f3757
GR		 980 dev_warn(dev,
981 "fan%u low limit %lu below minimum %u, set to minimum\n",
266cd583 982 channel + 1, val, data->fan_from_reg_min(254, 7));
08e7e278 983 } else if (!reg) {
8969e84d
GR		 984 /*
985 * Speed above this value cannot possibly be represented,
986 * even with the lowest divider (1)
987 */
266cd583 988 data->fan_min[channel] = 1;
08e7e278 989 new_div = 0; /* 1 == (1 << 0) */
b55f3757
GR		 990 dev_warn(dev,
991 "fan%u low limit %lu above maximum %u, set to maximum\n",
266cd583 992 channel + 1, val, data->fan_from_reg_min(1, 0));
08e7e278 993 } else {
8969e84d
GR		 994 /*
995 * Automatically pick the best divider, i.e. the one such
996 * that the min limit will correspond to a register value
997 * in the 96..192 range
998 */
08e7e278
JD		 999 new_div = 0;
1000 while (reg > 192 && new_div < 7) {
1001 reg >>= 1;
1002 new_div++;
1003 }
266cd583 1004 data->fan_min[channel] = reg;
08e7e278
JD		 1005 }
1006
8969e84d
GR		 1007 /*
1008 * Write both the fan clock divider (if it changed) and the new
1009 * fan min (unconditionally)
1010 */
266cd583 1011 if (new_div != data->fan_div[channel]) {
08e7e278 1012 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
266cd583 1013 channel + 1, div_from_reg(data->fan_div[channel]),
08e7e278 1014 div_from_reg(new_div));
266cd583
DDAG		 1015 data->fan_div[channel] = new_div;
1016 w83627ehf_write_fan_div_common(dev, data, channel);
6b3e4645
JD		 1017 /* Give the chip time to sample a new speed value */
1018 data->last_updated = jiffies;
08e7e278 1019 }
ec3e5a16 1020done:
266cd583
DDAG		 1021 w83627ehf_write_value(data, data->REG_FAN_MIN[channel],
1022 data->fan_min[channel]);
9a61bf63 1023 mutex_unlock(&data->update_lock);
08e7e278 1024
266cd583 1025 return 0;
08e7e278 1026}
08e7e278 1027
ec3e5a16 1028#define store_temp_reg(addr, reg) \
266cd583
DDAG		 1029static int \
1030store_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
1031 long val) \
08e7e278 1032{ \
9a61bf63 1033 mutex_lock(&data->update_lock); \
266cd583
DDAG		 1034 data->reg[channel] = LM75_TEMP_TO_REG(val); \
1035 w83627ehf_write_temp(data, data->addr[channel], data->reg[channel]); \
9a61bf63 1036 mutex_unlock(&data->update_lock); \
266cd583 1037 return 0; \
08e7e278 1038}
ec3e5a16
GR		 1039store_temp_reg(reg_temp_over, temp_max);
1040store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1041
266cd583
DDAG		 1042static int
1043store_temp_offset(struct device *dev, struct w83627ehf_data *data, int channel,
1044 long val)
840e191d 1045{
2a844c14 1046 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
840e191d
GR		 1047
1048 mutex_lock(&data->update_lock);
266cd583
DDAG		 1049 data->temp_offset[channel] = val;
1050 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
840e191d 1051 mutex_unlock(&data->update_lock);
266cd583 1052 return 0;
08c79950
RM		 1053}
1054
266cd583
DDAG		 1055static int
1056store_pwm_mode(struct device *dev, struct w83627ehf_data *data, int channel,
1057 long val)
08c79950 1058{
08c79950
RM		 1059 u16 reg;
1060
266cd583 1061 if (val < 0 || val > 1)
08c79950 1062 return -EINVAL;
ad77c3e1
GR		 1063
1064 /* On NCT67766F, DC mode is only supported for pwm1 */
266cd583 1065 if (data->kind == nct6776 && channel && val != 1)
ad77c3e1
GR		 1066 return -EINVAL;
1067
08c79950 1068 mutex_lock(&data->update_lock);
266cd583
DDAG		 1069 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[channel]);
1070 data->pwm_mode[channel] = val;
1071 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[channel]);
08c79950 1072 if (!val)
266cd583
DDAG		 1073 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[channel];
1074 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
08c79950 1075 mutex_unlock(&data->update_lock);
266cd583 1076 return 0;
08c79950
RM		 1077}
1078
266cd583
DDAG		 1079static int
1080store_pwm(struct device *dev, struct w83627ehf_data *data, int channel,
1081 long val)
08c79950 1082{
2a844c14 1083 val = clamp_val(val, 0, 255);
08c79950
RM		 1084
1085 mutex_lock(&data->update_lock);
266cd583
DDAG		 1086 data->pwm[channel] = val;
1087 w83627ehf_write_value(data, data->REG_PWM[channel], val);
08c79950 1088 mutex_unlock(&data->update_lock);
266cd583 1089 return 0;
08c79950
RM		 1090}
1091
266cd583
DDAG		 1092static int
1093store_pwm_enable(struct device *dev, struct w83627ehf_data *data, int channel,
1094 long val)
08c79950 1095{
08c79950
RM		 1096 u16 reg;
1097
266cd583
DDAG		 1098 if (!val || val < 0 ||
1099 (val > 4 && val != data->pwm_enable_orig[channel]))
08c79950 1100 return -EINVAL;
ec3e5a16 1101 /* SmartFan III mode is not supported on NCT6776F */
266cd583 1102 if (data->kind == nct6776 && val == 4)
ec3e5a16
GR		 1103 return -EINVAL;
1104
08c79950 1105 mutex_lock(&data->update_lock);
266cd583
DDAG		 1106 data->pwm_enable[channel] = val;
1107 if (data->kind == nct6775 || data->kind == nct6776) {
ec3e5a16 1108 reg = w83627ehf_read_value(data,
266cd583 1109 NCT6775_REG_FAN_MODE[channel]);
ec3e5a16
GR		 1110 reg &= 0x0f;
1111 reg |= (val - 1) << 4;
1112 w83627ehf_write_value(data,
266cd583 1113 NCT6775_REG_FAN_MODE[channel], reg);
ec3e5a16 1114 } else {
266cd583
DDAG		 1115 reg = w83627ehf_read_value(data,
1116 W83627EHF_REG_PWM_ENABLE[channel]);
1117 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]);
1118 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[channel];
1119 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
1120 reg);
ec3e5a16 1121 }
08c79950 1122 mutex_unlock(&data->update_lock);
266cd583 1123 return 0;
08c79950
RM		 1124}
1125
08c79950
RM		 1126#define show_tol_temp(reg) \
1127static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1128 char *buf) \
1129{ \
266cd583 1130 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
e7e1ca6e
GR		 1131 struct sensor_device_attribute *sensor_attr = \
1132 to_sensor_dev_attr(attr); \
08c79950 1133 int nr = sensor_attr->index; \
bce26c58 1134 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1135}
1136
1137show_tol_temp(tolerance)
1138show_tol_temp(target_temp)
1139
1140static ssize_t
1141store_target_temp(struct device *dev, struct device_attribute *attr,
1142 const char *buf, size_t count)
1143{
1ea6dd38 1144 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1145 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1146 int nr = sensor_attr->index;
bce26c58
GR		 1147 long val;
1148 int err;
1149
179c4fdb 1150 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1151 if (err < 0)
1152 return err;
1153
2a844c14 1154 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1155
1156 mutex_lock(&data->update_lock);
1157 data->target_temp[nr] = val;
279af1a9 1158 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1159 mutex_unlock(&data->update_lock);
1160 return count;
1161}
1162
1163static ssize_t
1164store_tolerance(struct device *dev, struct device_attribute *attr,
1165 const char *buf, size_t count)
1166{
1ea6dd38 1167 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1168 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1169 int nr = sensor_attr->index;
1170 u16 reg;
bce26c58
GR		 1171 long val;
1172 int err;
1173
179c4fdb 1174 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1175 if (err < 0)
1176 return err;
1177
08c79950 1178 /* Limit the temp to 0C - 15C */
2a844c14 1179 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1180
1181 mutex_lock(&data->update_lock);
266cd583 1182 if (data->kind == nct6775 || data->kind == nct6776) {
ec3e5a16 1183 /* Limit tolerance further for NCT6776F */
266cd583 1184 if (data->kind == nct6776 && val > 7)
ec3e5a16
GR		 1185 val = 7;
1186 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1187 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1188 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1189 } else {
1190 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1191 if (nr == 1)
1192 reg = (reg & 0x0f) | (val << 4);
1193 else
1194 reg = (reg & 0xf0) | val;
1195 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1196 }
1197 data->tolerance[nr] = val;
08c79950
RM		 1198 mutex_unlock(&data->update_lock);
1199 return count;
1200}
1201
266cd583
DDAG		 1202SENSOR_DEVICE_ATTR(pwm1_target, 0644, show_target_temp,
1203 store_target_temp, 0);
1204SENSOR_DEVICE_ATTR(pwm2_target, 0644, show_target_temp,
1205 store_target_temp, 1);
1206SENSOR_DEVICE_ATTR(pwm3_target, 0644, show_target_temp,
1207 store_target_temp, 2);
1208SENSOR_DEVICE_ATTR(pwm4_target, 0644, show_target_temp,
1209 store_target_temp, 3);
1210
1211SENSOR_DEVICE_ATTR(pwm1_tolerance, 0644, show_tolerance,
1212 store_tolerance, 0);
1213SENSOR_DEVICE_ATTR(pwm2_tolerance, 0644, show_tolerance,
1214 store_tolerance, 1);
1215SENSOR_DEVICE_ATTR(pwm3_tolerance, 0644, show_tolerance,
1216 store_tolerance, 2);
1217SENSOR_DEVICE_ATTR(pwm4_tolerance, 0644, show_tolerance,
1218 store_tolerance, 3);
08c79950 1219
08c79950
RM		 1220/* Smart Fan registers */
1221
1222#define fan_functions(reg, REG) \
1223static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1224 char *buf) \
1225{ \
266cd583 1226 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
e7e1ca6e
GR		 1227 struct sensor_device_attribute *sensor_attr = \
1228 to_sensor_dev_attr(attr); \
08c79950
RM		 1229 int nr = sensor_attr->index; \
1230 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1231} \
08c79950
RM		 1232static ssize_t \
1233store_##reg(struct device *dev, struct device_attribute *attr, \
1234 const char *buf, size_t count) \
e7e1ca6e 1235{ \
1ea6dd38 1236 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1237 struct sensor_device_attribute *sensor_attr = \
1238 to_sensor_dev_attr(attr); \
08c79950 1239 int nr = sensor_attr->index; \
bce26c58
GR		 1240 unsigned long val; \
1241 int err; \
179c4fdb 1242 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1243 if (err < 0) \
1244 return err; \
2a844c14 1245 val = clamp_val(val, 1, 255); \
08c79950
RM		 1246 mutex_lock(&data->update_lock); \
1247 data->reg[nr] = val; \
da2e0255 1248 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1249 mutex_unlock(&data->update_lock); \
1250 return count; \
1251}
1252
41e9a062
DB		 1253fan_functions(fan_start_output, FAN_START_OUTPUT)
1254fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1255fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1256fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1257
1258#define fan_time_functions(reg, REG) \
1259static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1260 char *buf) \
1261{ \
266cd583 1262 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
e7e1ca6e
GR		 1263 struct sensor_device_attribute *sensor_attr = \
1264 to_sensor_dev_attr(attr); \
08c79950
RM		 1265 int nr = sensor_attr->index; \
1266 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1267 step_time_from_reg(data->reg[nr], \
1268 data->pwm_mode[nr])); \
08c79950
RM		 1269} \
1270\
1271static ssize_t \
1272store_##reg(struct device *dev, struct device_attribute *attr, \
1273 const char *buf, size_t count) \
1274{ \
1ea6dd38 1275 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1276 struct sensor_device_attribute *sensor_attr = \
1277 to_sensor_dev_attr(attr); \
08c79950 1278 int nr = sensor_attr->index; \
bce26c58
GR		 1279 unsigned long val; \
1280 int err; \
179c4fdb 1281 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1282 if (err < 0) \
1283 return err; \
1284 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1285 mutex_lock(&data->update_lock); \
1286 data->reg[nr] = val; \
33fa9b62 1287 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1288 mutex_unlock(&data->update_lock); \
1289 return count; \
1290} \
1291
1292fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1293
266cd583
DDAG		 1294SENSOR_DEVICE_ATTR(pwm4_stop_time, 0644, show_fan_stop_time,
1295 store_fan_stop_time, 3);
1296SENSOR_DEVICE_ATTR(pwm4_start_output, 0644, show_fan_start_output,
1297 store_fan_start_output, 3);
1298SENSOR_DEVICE_ATTR(pwm4_stop_output, 0644, show_fan_stop_output,
1299 store_fan_stop_output, 3);
1300SENSOR_DEVICE_ATTR(pwm4_max_output, 0644, show_fan_max_output,
1301 store_fan_max_output, 3);
1302SENSOR_DEVICE_ATTR(pwm4_step_output, 0644, show_fan_step_output,
1303 store_fan_step_output, 3);
1304
1305SENSOR_DEVICE_ATTR(pwm3_stop_time, 0644, show_fan_stop_time,
1306 store_fan_stop_time, 2);
1307SENSOR_DEVICE_ATTR(pwm3_start_output, 0644, show_fan_start_output,
1308 store_fan_start_output, 2);
1309SENSOR_DEVICE_ATTR(pwm3_stop_output, 0644, show_fan_stop_output,
1310 store_fan_stop_output, 2);
1311
1312SENSOR_DEVICE_ATTR(pwm1_stop_time, 0644, show_fan_stop_time,
1313 store_fan_stop_time, 0);
1314SENSOR_DEVICE_ATTR(pwm2_stop_time, 0644, show_fan_stop_time,
1315 store_fan_stop_time, 1);
1316SENSOR_DEVICE_ATTR(pwm1_start_output, 0644, show_fan_start_output,
1317 store_fan_start_output, 0);
1318SENSOR_DEVICE_ATTR(pwm2_start_output, 0644, show_fan_start_output,
1319 store_fan_start_output, 1);
1320SENSOR_DEVICE_ATTR(pwm1_stop_output, 0644, show_fan_stop_output,
1321 store_fan_stop_output, 0);
1322SENSOR_DEVICE_ATTR(pwm2_stop_output, 0644, show_fan_stop_output,
1323 store_fan_stop_output, 1);
41e9a062 1324
da2e0255
GR		 1325
1326/*
1327 * pwm1 and pwm3 don't support max and step settings on all chips.
1328 * Need to check support while generating/removing attribute files.
1329 */
266cd583
DDAG		 1330SENSOR_DEVICE_ATTR(pwm1_max_output, 0644, show_fan_max_output,
1331 store_fan_max_output, 0);
1332SENSOR_DEVICE_ATTR(pwm1_step_output, 0644, show_fan_step_output,
1333 store_fan_step_output, 0);
1334SENSOR_DEVICE_ATTR(pwm2_max_output, 0644, show_fan_max_output,
1335 store_fan_max_output, 1);
1336SENSOR_DEVICE_ATTR(pwm2_step_output, 0644, show_fan_step_output,
1337 store_fan_step_output, 1);
1338SENSOR_DEVICE_ATTR(pwm3_max_output, 0644, show_fan_max_output,
1339 store_fan_max_output, 2);
1340SENSOR_DEVICE_ATTR(pwm3_step_output, 0644, show_fan_step_output,
1341 store_fan_step_output, 2);
08c79950 1342
fc18d6c0 1343static ssize_t
9bbacbfe 1344cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
fc18d6c0
JD		 1345{
1346 struct w83627ehf_data *data = dev_get_drvdata(dev);
1347 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1348}
266cd583 1349DEVICE_ATTR_RO(cpu0_vid);
fc18d6c0 1350
363a12a4
DA		 1351
1352/* Case open detection */
266cd583
DDAG		 1353static int
1354clear_caseopen(struct device *dev, struct w83627ehf_data *data, int channel,
1355 long val)
363a12a4 1356{
266cd583 1357 u16 masks[] = { 0x80, 0x40 };
363a12a4
DA		 1358 u16 reg, mask;
1359
266cd583 1360 if (val != 0 || channel > 1)
363a12a4
DA		 1361 return -EINVAL;
1362
266cd583 1363 mask = masks[channel];
363a12a4
DA		 1364
1365 mutex_lock(&data->update_lock);
1366 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1367 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1368 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1369 data->valid = 0; /* Force cache refresh */
1370 mutex_unlock(&data->update_lock);
1371
266cd583 1372 return 0;
363a12a4
DA		 1373}
1374
266cd583
DDAG		 1375static umode_t w83627ehf_attrs_visible(struct kobject *kobj,
1376 struct attribute *a, int n)
c18beb5b 1377{
266cd583 1378 struct device *dev = container_of(kobj, struct device, kobj);
1ea6dd38 1379 struct w83627ehf_data *data = dev_get_drvdata(dev);
266cd583
DDAG		 1380 struct device_attribute *devattr;
1381 struct sensor_device_attribute *sda;
1382
1383 devattr = container_of(a, struct device_attribute, attr);
1384
1385 /* Not sensor */
1386 if (devattr->show == cpu0_vid_show && data->have_vid)
1387 return a->mode;
1388
1389 sda = (struct sensor_device_attribute *)devattr;
1390
1391 if (sda->index < 2 &&
1392 (devattr->show == show_fan_stop_time ||
1393 devattr->show == show_fan_start_output ||
1394 devattr->show == show_fan_stop_output))
1395 return a->mode;
1396
1397 if (sda->index < 3 &&
1398 (devattr->show == show_fan_max_output ||
1399 devattr->show == show_fan_step_output) &&
1400 data->REG_FAN_STEP_OUTPUT &&
1401 data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff)
1402 return a->mode;
1403
1404 /* if fan3 and fan4 are enabled create the files for them */
1405 if (sda->index == 2 &&
1406 (data->has_fan & (1 << 2)) && data->pwm_num >= 3 &&
1407 (devattr->show == show_fan_stop_time ||
1408 devattr->show == show_fan_start_output ||
1409 devattr->show == show_fan_stop_output))
1410 return a->mode;
1411
1412 if (sda->index == 3 &&
1413 (data->has_fan & (1 << 3)) && data->pwm_num >= 4 &&
1414 (devattr->show == show_fan_stop_time ||
1415 devattr->show == show_fan_start_output ||
1416 devattr->show == show_fan_stop_output ||
1417 devattr->show == show_fan_max_output ||
1418 devattr->show == show_fan_step_output))
1419 return a->mode;
1420
1421 if ((devattr->show == show_target_temp ||
1422 devattr->show == show_tolerance) &&
1423 (data->has_fan & (1 << sda->index)) &&
1424 sda->index < data->pwm_num)
1425 return a->mode;
c18beb5b 1426
266cd583
DDAG		 1427 return 0;
1428}
c18beb5b 1429
266cd583
DDAG		 1430/* These groups handle non-standard attributes used in this device */
1431static struct attribute *w83627ehf_attrs[] = {
1432
1433 &sensor_dev_attr_pwm1_stop_time.dev_attr.attr,
1434 &sensor_dev_attr_pwm1_start_output.dev_attr.attr,
1435 &sensor_dev_attr_pwm1_stop_output.dev_attr.attr,
1436 &sensor_dev_attr_pwm1_max_output.dev_attr.attr,
1437 &sensor_dev_attr_pwm1_step_output.dev_attr.attr,
1438 &sensor_dev_attr_pwm1_target.dev_attr.attr,
1439 &sensor_dev_attr_pwm1_tolerance.dev_attr.attr,
1440
1441 &sensor_dev_attr_pwm2_stop_time.dev_attr.attr,
1442 &sensor_dev_attr_pwm2_start_output.dev_attr.attr,
1443 &sensor_dev_attr_pwm2_stop_output.dev_attr.attr,
1444 &sensor_dev_attr_pwm2_max_output.dev_attr.attr,
1445 &sensor_dev_attr_pwm2_step_output.dev_attr.attr,
1446 &sensor_dev_attr_pwm2_target.dev_attr.attr,
1447 &sensor_dev_attr_pwm2_tolerance.dev_attr.attr,
1448
1449 &sensor_dev_attr_pwm3_stop_time.dev_attr.attr,
1450 &sensor_dev_attr_pwm3_start_output.dev_attr.attr,
1451 &sensor_dev_attr_pwm3_stop_output.dev_attr.attr,
1452 &sensor_dev_attr_pwm3_max_output.dev_attr.attr,
1453 &sensor_dev_attr_pwm3_step_output.dev_attr.attr,
1454 &sensor_dev_attr_pwm3_target.dev_attr.attr,
1455 &sensor_dev_attr_pwm3_tolerance.dev_attr.attr,
1456
1457 &sensor_dev_attr_pwm4_stop_time.dev_attr.attr,
1458 &sensor_dev_attr_pwm4_start_output.dev_attr.attr,
1459 &sensor_dev_attr_pwm4_stop_output.dev_attr.attr,
1460 &sensor_dev_attr_pwm4_max_output.dev_attr.attr,
1461 &sensor_dev_attr_pwm4_step_output.dev_attr.attr,
1462 &sensor_dev_attr_pwm4_target.dev_attr.attr,
1463 &sensor_dev_attr_pwm4_tolerance.dev_attr.attr,
1464
1465 &dev_attr_cpu0_vid.attr,
1466 NULL
1467};
363a12a4 1468
266cd583
DDAG		 1469static const struct attribute_group w83627ehf_group = {
1470 .attrs = w83627ehf_attrs,
1471 .is_visible = w83627ehf_attrs_visible,
1472};
1473
1474static const struct attribute_group *w83627ehf_groups[] = {
1475 &w83627ehf_group,
1476 NULL
1477};
1478
1479/*
1480 * Driver and device management
1481 */
08e7e278 1482
1ea6dd38 1483/* Get the monitoring functions started */
6c931ae1 1484static inline void w83627ehf_init_device(struct w83627ehf_data *data,
bf164c58 1485 enum kinds kind)
08e7e278
JD		 1486{
1487 int i;
da667365 1488 u8 tmp, diode;
08e7e278
JD		 1489
1490 /* Start monitoring is needed */
1ea6dd38 1491 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1492 if (!(tmp & 0x01))
1ea6dd38 1493 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1494 tmp | 0x01);
1495
d36cf32c
GR		 1496 /* Enable temperature sensors if needed */
1497 for (i = 0; i < NUM_REG_TEMP; i++) {
1498 if (!(data->have_temp & (1 << i)))
1499 continue;
ec3e5a16 1500 if (!data->reg_temp_config[i])
d36cf32c 1501 continue;
1ea6dd38 1502 tmp = w83627ehf_read_value(data,
ec3e5a16 1503 data->reg_temp_config[i]);
08e7e278 1504 if (tmp & 0x01)
1ea6dd38 1505 w83627ehf_write_value(data,
ec3e5a16 1506 data->reg_temp_config[i],
08e7e278
JD		 1507 tmp & 0xfe);
1508 }
d3130f0e
JD		 1509
1510 /* Enable VBAT monitoring if needed */
1511 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1512 if (!(tmp & 0x01))
1513 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1514
1515 /* Get thermal sensor types */
bf164c58
JD		 1516 switch (kind) {
1517 case w83627ehf:
1518 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1519 break;
eff7687d
JD		 1520 case w83627uhg:
1521 diode = 0x00;
1522 break;
bf164c58
JD		 1523 default:
1524 diode = 0x70;
1525 }
da667365 1526 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1527 const char *label = NULL;
1528
1529 if (data->temp_label)
1530 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1531
1532 /* Digital source overrides analog type */
bfa02b0d 1533 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1534 data->temp_type[i] = 6;
bfa02b0d 1535 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1536 data->temp_type[i] = 5;
1537 else if ((tmp & (0x02 << i)))
bf164c58 1538 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1539 else
1540 data->temp_type[i] = 4; /* thermistor */
1541 }
08e7e278
JD		 1542}
1543
ec3e5a16
GR		 1544static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1545 int r1, int r2)
1546{
ffe3df53
FF		 1547 swap(data->temp_src[r1], data->temp_src[r2]);
1548 swap(data->reg_temp[r1], data->reg_temp[r2]);
1549 swap(data->reg_temp_over[r1], data->reg_temp_over[r2]);
1550 swap(data->reg_temp_hyst[r1], data->reg_temp_hyst[r2]);
1551 swap(data->reg_temp_config[r1], data->reg_temp_config[r2]);
ec3e5a16
GR		 1552}
1553
6c931ae1 1554static void
6ba71de5
JD		 1555w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1556{
1557 int i;
1558
1559 for (i = 0; i < n_temp; i++) {
1560 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1561 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1562 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1563 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1564 }
1565}
1566
6c931ae1 1567static void
03f5de2b
JD		 1568w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1569 struct w83627ehf_data *data)
1570{
1571 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1572
eff7687d
JD		 1573 /* The W83627UHG is simple, only two fan inputs, no config */
1574 if (sio_data->kind == w83627uhg) {
1575 data->has_fan = 0x03; /* fan1 and fan2 */
1576 data->has_fan_min = 0x03;
1577 return;
1578 }
1579
03f5de2b
JD		 1580 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1581 if (sio_data->kind == nct6775) {
1582 /* On NCT6775, fan4 shares pins with the fdc interface */
1583 fan3pin = 1;
1584 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1585 fan4min = 0;
1586 fan5pin = 0;
1587 } else if (sio_data->kind == nct6776) {
585c0fd8
GR		 1588 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
1589
1590 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1591 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
1592
1593 if (regval & 0x80)
1594 fan3pin = gpok;
1595 else
1596 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
1597
1598 if (regval & 0x40)
1599 fan4pin = gpok;
1600 else
1601 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
1602
1603 if (regval & 0x20)
1604 fan5pin = gpok;
1605 else
1606 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
1607
03f5de2b
JD		 1608 fan4min = fan4pin;
1609 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
1610 fan3pin = 1;
1611 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1612 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1613 fan4min = fan4pin;
1614 } else {
1615 fan3pin = 1;
1616 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1617 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1618 fan4min = fan4pin;
1619 }
1620
03f5de2b
JD		 1621 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
1622 data->has_fan |= (fan3pin << 2);
1623 data->has_fan_min |= (fan3pin << 2);
1624
1625 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1626 /*
1627 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
1628 * register
1629 */
1630 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
1631 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
1632 } else {
1633 /*
1634 * It looks like fan4 and fan5 pins can be alternatively used
1635 * as fan on/off switches, but fan5 control is write only :/
1636 * We assume that if the serial interface is disabled, designers
1637 * connected fan5 as input unless they are emitting log 1, which
1638 * is not the default.
1639 */
1640 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1641 if ((regval & (1 << 2)) && fan4pin) {
1642 data->has_fan |= (1 << 3);
1643 data->has_fan_min |= (1 << 3);
1644 }
1645 if (!(regval & (1 << 1)) && fan5pin) {
1646 data->has_fan |= (1 << 4);
1647 data->has_fan_min |= (1 << 4);
1648 }
1649 }
1650}
1651
266cd583
DDAG		 1652static umode_t
1653w83627ehf_is_visible(const void *drvdata, enum hwmon_sensor_types type,
1654 u32 attr, int channel)
1655{
1656 const struct w83627ehf_data *data = drvdata;
1657
1658 switch (type) {
1659 case hwmon_temp:
1660 /* channel 0.., name 1.. */
1661 if (!(data->have_temp & (1 << channel)))
1662 return 0;
1663 if (attr == hwmon_temp_input || attr == hwmon_temp_label)
1664 return 0444;
1665 if (channel == 2 && data->temp3_val_only)
1666 return 0;
1667 if (attr == hwmon_temp_max) {
1668 if (data->reg_temp_over[channel])
1669 return 0644;
1670 else
1671 return 0;
1672 }
1673 if (attr == hwmon_temp_max_hyst) {
1674 if (data->reg_temp_hyst[channel])
1675 return 0644;
1676 else
1677 return 0;
1678 }
1679 if (channel > 2)
1680 return 0;
1681 if (attr == hwmon_temp_alarm || attr == hwmon_temp_type)
1682 return 0444;
1683 if (attr == hwmon_temp_offset) {
1684 if (data->have_temp_offset & (1 << channel))
1685 return 0644;
1686 else
1687 return 0;
1688 }
1689 break;
1690
1691 case hwmon_fan:
1692 /* channel 0.., name 1.. */
1693 if (!(data->has_fan & (1 << channel)))
1694 return 0;
1695 if (attr == hwmon_fan_input || attr == hwmon_fan_alarm)
1696 return 0444;
1697 if (attr == hwmon_fan_div) {
1698 if (data->kind != nct6776)
1699 return 0444;
1700 else
1701 return 0;
1702 }
1703 if (attr == hwmon_fan_min) {
1704 if (data->has_fan_min & (1 << channel))
1705 return 0644;
1706 else
1707 return 0;
1708 }
1709 break;
1710
1711 case hwmon_in:
1712 /* channel 0.., name 0.. */
1713 if (channel >= data->in_num)
1714 return 0;
1715 if (channel == 6 && data->in6_skip)
1716 return 0;
1717 if (attr == hwmon_in_alarm || attr == hwmon_in_input)
1718 return 0444;
1719 if (attr == hwmon_in_min || attr == hwmon_in_max)
1720 return 0644;
1721 break;
1722
1723 case hwmon_pwm:
1724 /* channel 0.., name 1.. */
1725 if (!(data->has_fan & (1 << channel)) ||
1726 channel >= data->pwm_num)
1727 return 0;
1728 if (attr == hwmon_pwm_mode || attr == hwmon_pwm_enable ||
1729 attr == hwmon_pwm_input)
1730 return 0644;
1731 break;
1732
1733 case hwmon_intrusion:
1734 if (channel == 0 ||
1735 (channel == 1 && data->kind == nct6776))
1736 return 0644;
1737 return 0;
1738
1739 default: /* Shouldn't happen */
1740 return 0;
1741 }
1742
1743 return 0; /* Shouldn't happen */
1744}
1745
1746static int
1747w83627ehf_do_read_temp(struct w83627ehf_data *data, u32 attr,
1748 int channel, long *val)
1749{
1750 switch (attr) {
1751 case hwmon_temp_input:
1752 *val = LM75_TEMP_FROM_REG(data->temp[channel]);
1753 return 0;
1754 case hwmon_temp_max:
1755 *val = LM75_TEMP_FROM_REG(data->temp_max[channel]);
1756 return 0;
1757 case hwmon_temp_max_hyst:
1758 *val = LM75_TEMP_FROM_REG(data->temp_max_hyst[channel]);
1759 return 0;
1760 case hwmon_temp_offset:
1761 *val = data->temp_offset[channel] * 1000;
1762 return 0;
1763 case hwmon_temp_type:
1764 *val = (int)data->temp_type[channel];
1765 return 0;
1766 case hwmon_temp_alarm:
1767 if (channel < 3) {
1768 int bit[] = { 4, 5, 13 };
1769 *val = (data->alarms >> bit[channel]) & 1;
1770 return 0;
1771 }
1772 break;
1773
1774 default:
1775 break;
1776 }
1777
1778 return -EOPNOTSUPP;
1779}
1780
1781static int
1782w83627ehf_do_read_in(struct w83627ehf_data *data, u32 attr,
1783 int channel, long *val)
1784{
1785 switch (attr) {
1786 case hwmon_in_input:
1787 *val = in_from_reg(data->in[channel], channel, data->scale_in);
1788 return 0;
1789 case hwmon_in_min:
1790 *val = in_from_reg(data->in_min[channel], channel,
1791 data->scale_in);
1792 return 0;
1793 case hwmon_in_max:
1794 *val = in_from_reg(data->in_max[channel], channel,
1795 data->scale_in);
1796 return 0;
1797 case hwmon_in_alarm:
1798 if (channel < 10) {
1799 int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 };
1800 *val = (data->alarms >> bit[channel]) & 1;
1801 return 0;
1802 }
1803 break;
1804 default:
1805 break;
1806 }
1807 return -EOPNOTSUPP;
1808}
1809
1810static int
1811w83627ehf_do_read_fan(struct w83627ehf_data *data, u32 attr,
1812 int channel, long *val)
1813{
1814 switch (attr) {
1815 case hwmon_fan_input:
1816 *val = data->rpm[channel];
1817 return 0;
1818 case hwmon_fan_min:
1819 *val = data->fan_from_reg_min(data->fan_min[channel],
1820 data->fan_div[channel]);
1821 return 0;
1822 case hwmon_fan_div:
1823 *val = div_from_reg(data->fan_div[channel]);
1824 return 0;
1825 case hwmon_fan_alarm:
1826 if (channel < 5) {
1827 int bit[] = { 6, 7, 11, 10, 23 };
1828 *val = (data->alarms >> bit[channel]) & 1;
1829 return 0;
1830 }
1831 break;
1832 default:
1833 break;
1834 }
1835 return -EOPNOTSUPP;
1836}
1837
1838static int
1839w83627ehf_do_read_pwm(struct w83627ehf_data *data, u32 attr,
1840 int channel, long *val)
1841{
1842 switch (attr) {
1843 case hwmon_pwm_input:
1844 *val = data->pwm[channel];
1845 return 0;
1846 case hwmon_pwm_enable:
1847 *val = data->pwm_enable[channel];
1848 return 0;
1849 case hwmon_pwm_mode:
1850 *val = data->pwm_enable[channel];
1851 return 0;
1852 default:
1853 break;
1854 }
1855 return -EOPNOTSUPP;
1856}
1857
1858static int
1859w83627ehf_do_read_intrusion(struct w83627ehf_data *data, u32 attr,
1860 int channel, long *val)
1861{
1862 unsigned int masks[] = { 0x10, 0x40 };
1863
1864 if (attr != hwmon_intrusion_alarm || channel > 1)
1865 return -EOPNOTSUPP; /* shouldn't happen */
1866
1867 *val = !!(data->caseopen & masks[channel]);
1868 return 0;
1869}
1870
1871static int
1872w83627ehf_read(struct device *dev, enum hwmon_sensor_types type,
1873 u32 attr, int channel, long *val)
1874{
1875 struct w83627ehf_data *data = w83627ehf_update_device(dev->parent);
1876
1877 switch (type) {
1878 case hwmon_fan:
1879 return w83627ehf_do_read_fan(data, attr, channel, val);
1880
1881 case hwmon_in:
1882 return w83627ehf_do_read_in(data, attr, channel, val);
1883
1884 case hwmon_pwm:
1885 return w83627ehf_do_read_pwm(data, attr, channel, val);
1886
1887 case hwmon_temp:
1888 return w83627ehf_do_read_temp(data, attr, channel, val);
1889
1890 case hwmon_intrusion:
1891 return w83627ehf_do_read_intrusion(data, attr, channel, val);
1892
1893 default:
1894 break;
1895 }
1896
1897 return -EOPNOTSUPP;
1898}
1899
1900static int
1901w83627ehf_read_string(struct device *dev, enum hwmon_sensor_types type,
1902 u32 attr, int channel, const char **str)
1903{
1904 struct w83627ehf_data *data = dev_get_drvdata(dev);
1905
1906 switch (type) {
1907 case hwmon_temp:
1908 if (attr == hwmon_temp_label) {
1909 *str = data->temp_label[data->temp_src[channel]];
1910 return 0;
1911 }
1912 break;
1913
1914 default:
1915 break;
1916 }
1917 /* Nothing else should be read as a string */
1918 return -EOPNOTSUPP;
1919}
1920
1921static int
1922w83627ehf_write(struct device *dev, enum hwmon_sensor_types type,
1923 u32 attr, int channel, long val)
1924{
1925 struct w83627ehf_data *data = dev_get_drvdata(dev);
1926
1927 if (type == hwmon_in && attr == hwmon_in_min)
1928 return store_in_min(dev, data, channel, val);
1929 if (type == hwmon_in && attr == hwmon_in_max)
1930 return store_in_max(dev, data, channel, val);
1931
1932 if (type == hwmon_fan && attr == hwmon_fan_min)
1933 return store_fan_min(dev, data, channel, val);
1934
1935 if (type == hwmon_temp && attr == hwmon_temp_max)
1936 return store_temp_max(dev, data, channel, val);
1937 if (type == hwmon_temp && attr == hwmon_temp_max_hyst)
1938 return store_temp_max_hyst(dev, data, channel, val);
1939 if (type == hwmon_temp && attr == hwmon_temp_offset)
1940 return store_temp_offset(dev, data, channel, val);
1941
1942 if (type == hwmon_pwm && attr == hwmon_pwm_mode)
1943 return store_pwm_mode(dev, data, channel, val);
1944 if (type == hwmon_pwm && attr == hwmon_pwm_enable)
1945 return store_pwm_enable(dev, data, channel, val);
1946 if (type == hwmon_pwm && attr == hwmon_pwm_input)
1947 return store_pwm(dev, data, channel, val);
1948
1949 if (type == hwmon_intrusion && attr == hwmon_intrusion_alarm)
1950 return clear_caseopen(dev, data, channel, val);
1951
1952 return -EOPNOTSUPP;
1953}
1954
1955static const struct hwmon_ops w83627ehf_ops = {
1956 .is_visible = w83627ehf_is_visible,
1957 .read = w83627ehf_read,
1958 .read_string = w83627ehf_read_string,
1959 .write = w83627ehf_write,
1960};
1961
1962static const struct hwmon_channel_info *w83627ehf_info[] = {
1963 HWMON_CHANNEL_INFO(fan,
1964 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1965 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1966 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1967 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1968 HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN),
1969 HWMON_CHANNEL_INFO(in,
1970 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1971 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1972 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1973 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1974 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1975 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1976 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1977 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1978 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1979 HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN),
1980 HWMON_CHANNEL_INFO(pwm,
1981 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1982 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1983 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1984 HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE),
1985 HWMON_CHANNEL_INFO(temp,
1986 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1987 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1988 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1989 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1990 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1991 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1992 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1993 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1994 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1995 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1996 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1997 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1998 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1999 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
2000 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
2001 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
2002 HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
2003 HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE),
2004 HWMON_CHANNEL_INFO(intrusion,
2005 HWMON_INTRUSION_ALARM,
2006 HWMON_INTRUSION_ALARM),
2007 NULL
2008};
2009
2010static const struct hwmon_chip_info w83627ehf_chip_info = {
2011 .ops = &w83627ehf_ops,
2012 .info = w83627ehf_info,
2013};
2014
6c931ae1 2015static int w83627ehf_probe(struct platform_device *pdev)
08e7e278 2016{
1ea6dd38 2017 struct device *dev = &pdev->dev;
a8b3a3a5 2018 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08e7e278 2019 struct w83627ehf_data *data;
1ea6dd38 2020 struct resource *res;
03f5de2b 2021 u8 en_vrm10;
08e7e278 2022 int i, err = 0;
266cd583 2023 struct device *hwmon_dev;
08e7e278 2024
1ea6dd38
DH		 2025 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2026 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 2027 err = -EBUSY;
1ea6dd38
DH		 2028 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2029 (unsigned long)res->start,
2030 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 2031 goto exit;
2032 }
2033
32260d94
GR		 2034 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2035 GFP_KERNEL);
e7e1ca6e 2036 if (!data) {
08e7e278
JD		 2037 err = -ENOMEM;
2038 goto exit_release;
2039 }
08e7e278 2040
1ea6dd38 2041 data->addr = res->start;
9a61bf63 2042 mutex_init(&data->lock);
9a61bf63 2043 mutex_init(&data->update_lock);
1ea6dd38 2044 data->name = w83627ehf_device_names[sio_data->kind];
266cd583 2045 data->kind = sio_data->kind;
3300fb4f 2046 data->bank = 0xff; /* Force initial bank selection */
1ea6dd38 2047 platform_set_drvdata(pdev, data);
08e7e278 2048
237c8d2f
GJ		 2049 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2050 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
eff7687d
JD		 2051 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2052 switch (sio_data->kind) {
2053 default:
2054 data->pwm_num = 4;
2055 break;
2056 case w83667hg:
2057 case w83667hg_b:
2058 case nct6775:
2059 case nct6776:
2060 data->pwm_num = 3;
2061 break;
2062 case w83627uhg:
2063 data->pwm_num = 2;
2064 break;
2065 }
08e7e278 2066
6ba71de5 2067 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 2068 data->have_temp = 0x07;
ec3e5a16
GR		 2069
2070 /* Deal with temperature register setup first. */
2071 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2072 int mask = 0;
2073
2074 /*
2075 * Display temperature sensor output only if it monitors
2076 * a source other than one already reported. Always display
2077 * first three temperature registers, though.
2078 */
2079 for (i = 0; i < NUM_REG_TEMP; i++) {
2080 u8 src;
2081
2082 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2083 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2084 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2085 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2086
2087 src = w83627ehf_read_value(data,
2088 NCT6775_REG_TEMP_SOURCE[i]);
2089 src &= 0x1f;
2090 if (src && !(mask & (1 << src))) {
2091 data->have_temp |= 1 << i;
2092 mask |= 1 << src;
2093 }
2094
2095 data->temp_src[i] = src;
2096
2097 /*
2098 * Now do some register swapping if index 0..2 don't
2099 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2100 * Idea is to have the first three attributes
2101 * report SYSTIN, CPUIN, and AUXIN if possible
2102 * without overriding the basic system configuration.
2103 */
2104 if (i > 0 && data->temp_src[0] != 1
2105 && data->temp_src[i] == 1)
2106 w82627ehf_swap_tempreg(data, 0, i);
2107 if (i > 1 && data->temp_src[1] != 2
2108 && data->temp_src[i] == 2)
2109 w82627ehf_swap_tempreg(data, 1, i);
2110 if (i > 2 && data->temp_src[2] != 3
2111 && data->temp_src[i] == 3)
2112 w82627ehf_swap_tempreg(data, 2, i);
2113 }
2114 if (sio_data->kind == nct6776) {
2115 /*
2116 * On NCT6776, AUXTIN and VIN3 pins are shared.
2117 * Only way to detect it is to check if AUXTIN is used
2118 * as a temperature source, and if that source is
2119 * enabled.
2120 *
2121 * If that is the case, disable in6, which reports VIN3.
2122 * Otherwise disable temp3.
2123 */
2124 if (data->temp_src[2] == 3) {
2125 u8 reg;
2126
2127 if (data->reg_temp_config[2])
2128 reg = w83627ehf_read_value(data,
2129 data->reg_temp_config[2]);
2130 else
2131 reg = 0; /* Assume AUXTIN is used */
2132
2133 if (reg & 0x01)
2134 data->have_temp &= ~(1 << 2);
2135 else
2136 data->in6_skip = 1;
2137 }
02309ad2
GR		 2138 data->temp_label = nct6776_temp_label;
2139 } else {
2140 data->temp_label = nct6775_temp_label;
ec3e5a16 2141 }
840e191d
GR		 2142 data->have_temp_offset = data->have_temp & 0x07;
2143 for (i = 0; i < 3; i++) {
2144 if (data->temp_src[i] > 3)
2145 data->have_temp_offset &= ~(1 << i);
2146 }
d36cf32c
GR		 2147 } else if (sio_data->kind == w83667hg_b) {
2148 u8 reg;
2149
6ba71de5
JD		 2150 w83627ehf_set_temp_reg_ehf(data, 4);
2151
ec3e5a16
GR		 2152 /*
2153 * Temperature sources are selected with bank 0, registers 0x49
2154 * and 0x4a.
2155 */
d36cf32c
GR		 2156 reg = w83627ehf_read_value(data, 0x4a);
2157 data->temp_src[0] = reg >> 5;
2158 reg = w83627ehf_read_value(data, 0x49);
2159 data->temp_src[1] = reg & 0x07;
ec3e5a16 2160 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 2161
2162 /*
2163 * W83667HG-B has another temperature register at 0x7e.
2164 * The temperature source is selected with register 0x7d.
2165 * Support it if the source differs from already reported
2166 * sources.
2167 */
2168 reg = w83627ehf_read_value(data, 0x7d);
2169 reg &= 0x07;
2170 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2171 && reg != data->temp_src[2]) {
2172 data->temp_src[3] = reg;
2173 data->have_temp |= 1 << 3;
2174 }
2175
2176 /*
2177 * Chip supports either AUXTIN or VIN3. Try to find out which
2178 * one.
2179 */
2180 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2181 if (data->temp_src[2] == 2 && (reg & 0x01))
2182 data->have_temp &= ~(1 << 2);
2183
2184 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2185 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2186 data->in6_skip = 1;
2187
eff7687d 2188 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2189 data->have_temp_offset = data->have_temp & 0x07;
2190 for (i = 0; i < 3; i++) {
2191 if (data->temp_src[i] > 2)
2192 data->have_temp_offset &= ~(1 << i);
2193 }
eff7687d
JD		 2194 } else if (sio_data->kind == w83627uhg) {
2195 u8 reg;
2196
2197 w83627ehf_set_temp_reg_ehf(data, 3);
2198
2199 /*
aacb6b00 2200 * Temperature sources for temp2 and temp3 are selected with
eff7687d
JD		 2201 * bank 0, registers 0x49 and 0x4a.
2202 */
2203 data->temp_src[0] = 0; /* SYSTIN */
2204 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2205 /* Adjust to have the same mapping as other source registers */
2206 if (reg == 0)
aacb6b00 2207 data->temp_src[1] = 1;
eff7687d 2208 else if (reg >= 2 && reg <= 5)
aacb6b00 2209 data->temp_src[1] = reg + 2;
eff7687d
JD		 2210 else /* should never happen */
2211 data->have_temp &= ~(1 << 1);
2212 reg = w83627ehf_read_value(data, 0x4a);
2213 data->temp_src[2] = reg >> 5;
2214
2215 /*
2216 * Skip temp3 if source is invalid or the same as temp1
2217 * or temp2.
2218 */
2219 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2220 data->temp_src[2] == data->temp_src[0] ||
2221 ((data->have_temp & (1 << 1)) &&
2222 data->temp_src[2] == data->temp_src[1]))
2223 data->have_temp &= ~(1 << 2);
2224 else
2225 data->temp3_val_only = 1; /* No limit regs */
2226
2227 data->in6_skip = 1; /* No VIN3 */
2228
d36cf32c 2229 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2230 data->have_temp_offset = data->have_temp & 0x03;
2231 for (i = 0; i < 3; i++) {
2232 if (data->temp_src[i] > 1)
2233 data->have_temp_offset &= ~(1 << i);
2234 }
ec3e5a16 2235 } else {
6ba71de5
JD		 2236 w83627ehf_set_temp_reg_ehf(data, 3);
2237
ec3e5a16 2238 /* Temperature sources are fixed */
6ba71de5
JD		 2239
2240 if (sio_data->kind == w83667hg) {
2241 u8 reg;
2242
2243 /*
2244 * Chip supports either AUXTIN or VIN3. Try to find
2245 * out which one.
2246 */
2247 reg = w83627ehf_read_value(data,
2248 W83627EHF_REG_TEMP_CONFIG[2]);
2249 if (reg & 0x01)
2250 data->have_temp &= ~(1 << 2);
2251 else
2252 data->in6_skip = 1;
ec3e5a16 2253 }
840e191d 2254 data->have_temp_offset = data->have_temp & 0x07;
a157d06d
GJ		 2255 }
2256
ec3e5a16 2257 if (sio_data->kind == nct6775) {
26bc440e
GR		 2258 data->has_fan_div = true;
2259 data->fan_from_reg = fan_from_reg16;
2260 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2261 data->REG_PWM = NCT6775_REG_PWM;
2262 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2263 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2264 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2265 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2266 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2267 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2268 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2269 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2270 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2271 data->has_fan_div = false;
2272 data->fan_from_reg = fan_from_reg13;
2273 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2274 data->REG_PWM = NCT6775_REG_PWM;
2275 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2276 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2277 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2278 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2279 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2280 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2281 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2282 data->has_fan_div = true;
2283 data->fan_from_reg = fan_from_reg8;
2284 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2285 data->REG_PWM = W83627EHF_REG_PWM;
2286 data->REG_TARGET = W83627EHF_REG_TARGET;
2287 data->REG_FAN = W83627EHF_REG_FAN;
2288 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2289 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2290 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2291 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2292 data->REG_FAN_MAX_OUTPUT =
2293 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2294 data->REG_FAN_STEP_OUTPUT =
2295 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2296 } else {
26bc440e
GR		 2297 data->has_fan_div = true;
2298 data->fan_from_reg = fan_from_reg8;
2299 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2300 data->REG_PWM = W83627EHF_REG_PWM;
2301 data->REG_TARGET = W83627EHF_REG_TARGET;
2302 data->REG_FAN = W83627EHF_REG_FAN;
2303 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2304 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2305 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2306 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2307 data->REG_FAN_MAX_OUTPUT =
2308 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2309 data->REG_FAN_STEP_OUTPUT =
2310 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2311 }
da2e0255 2312
eff7687d
JD		 2313 /* Setup input voltage scaling factors */
2314 if (sio_data->kind == w83627uhg)
2315 data->scale_in = scale_in_w83627uhg;
2316 else
2317 data->scale_in = scale_in_common;
2318
08e7e278 2319 /* Initialize the chip */
bf164c58 2320 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2321
fc18d6c0 2322 data->vrm = vid_which_vrm();
0d023530
KS		 2323
2324 err = superio_enter(sio_data->sioreg);
2325 if (err)
2326 goto exit_release;
2327
fc18d6c0 2328 /* Read VID value */
ec3e5a16
GR		 2329 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2330 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
8969e84d
GR		 2331 /*
2332 * W83667HG has different pins for VID input and output, so
2333 * we can get the VID input values directly at logical device D
2334 * 0xe3.
2335 */
237c8d2f
GJ		 2336 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2337 data->vid = superio_inb(sio_data->sioreg, 0xe3);
266cd583 2338 data->have_vid = true;
eff7687d 2339 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 2340 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2341 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
8969e84d
GR		 2342 /*
2343 * Set VID input sensibility if needed. In theory the
2344 * BIOS should have set it, but in practice it's not
2345 * always the case. We only do it for the W83627EHF/EHG
2346 * because the W83627DHG is more complex in this
2347 * respect.
2348 */
237c8d2f
GJ		 2349 if (sio_data->kind == w83627ehf) {
2350 en_vrm10 = superio_inb(sio_data->sioreg,
2351 SIO_REG_EN_VRM10);
2352 if ((en_vrm10 & 0x08) && data->vrm == 90) {
b55f3757
GR		 2353 dev_warn(dev,
2354 "Setting VID input voltage to TTL\n");
237c8d2f
GJ		 2355 superio_outb(sio_data->sioreg,
2356 SIO_REG_EN_VRM10,
2357 en_vrm10 & ~0x08);
2358 } else if (!(en_vrm10 & 0x08)
2359 && data->vrm == 100) {
b55f3757
GR		 2360 dev_warn(dev,
2361 "Setting VID input voltage to VRM10\n");
237c8d2f
GJ		 2362 superio_outb(sio_data->sioreg,
2363 SIO_REG_EN_VRM10,
2364 en_vrm10 | 0x08);
2365 }
2366 }
2367
2368 data->vid = superio_inb(sio_data->sioreg,
2369 SIO_REG_VID_DATA);
2370 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2371 data->vid &= 0x3f;
266cd583 2372 data->have_vid = true;
237c8d2f 2373 } else {
b55f3757
GR		 2374 dev_info(dev,
2375 "VID pins in output mode, CPU VID not available\n");
237c8d2f 2376 }
fc18d6c0
JD		 2377 }
2378
d42e869a
ID		 2379 if (fan_debounce &&
2380 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2381 u8 tmp;
2382
2383 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2384 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2385 if (sio_data->kind == nct6776)
2386 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2387 0x3e | tmp);
2388 else
2389 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2390 0x1e | tmp);
2391 pr_info("Enabled fan debounce for chip %s\n", data->name);
2392 }
2393
03f5de2b 2394 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 2395
0d023530
KS		 2396 superio_exit(sio_data->sioreg);
2397
ea7be66c 2398 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2399 w83627ehf_update_fan_div_common(dev, data);
2400
b84bb518
GR		 2401 /* Read pwm data to save original values */
2402 w83627ehf_update_pwm_common(dev, data);
2403 for (i = 0; i < data->pwm_num; i++)
2404 data->pwm_enable_orig[i] = data->pwm_enable[i];
2405
266cd583
DDAG		 2406 hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
2407 data->name,
2408 data,
2409 &w83627ehf_chip_info,
2410 w83627ehf_groups);
cf0676fe 2411
266cd583 2412 return PTR_ERR_OR_ZERO(hwmon_dev);
08e7e278 2413
08e7e278 2414exit_release:
1ea6dd38 2415 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2416exit:
2417 return err;
2418}
2419
281dfd0b 2420static int w83627ehf_remove(struct platform_device *pdev)
08e7e278 2421{
1ea6dd38 2422 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2423
1ea6dd38 2424 release_region(data->addr, IOREGION_LENGTH);
08e7e278
JD		 2425
2426 return 0;
2427}
2428
7e630bb5
JD		 2429#ifdef CONFIG_PM
2430static int w83627ehf_suspend(struct device *dev)
2431{
2432 struct w83627ehf_data *data = w83627ehf_update_device(dev);
a8b3a3a5 2433 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
7e630bb5
JD		 2434
2435 mutex_lock(&data->update_lock);
2436 data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
2437 if (sio_data->kind == nct6775) {
2438 data->fandiv1 = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
2439 data->fandiv2 = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
2440 }
2441 mutex_unlock(&data->update_lock);
2442
2443 return 0;
2444}
2445
2446static int w83627ehf_resume(struct device *dev)
2447{
2448 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 2449 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
7e630bb5
JD		 2450 int i;
2451
2452 mutex_lock(&data->update_lock);
2453 data->bank = 0xff; /* Force initial bank selection */
2454
2455 /* Restore limits */
2456 for (i = 0; i < data->in_num; i++) {
2457 if ((i == 6) && data->in6_skip)
2458 continue;
2459
2460 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
2461 data->in_min[i]);
2462 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2463 data->in_max[i]);
2464 }
2465
2466 for (i = 0; i < 5; i++) {
2467 if (!(data->has_fan_min & (1 << i)))
2468 continue;
2469
2470 w83627ehf_write_value(data, data->REG_FAN_MIN[i],
2471 data->fan_min[i]);
2472 }
2473
2474 for (i = 0; i < NUM_REG_TEMP; i++) {
2475 if (!(data->have_temp & (1 << i)))
2476 continue;
2477
2478 if (data->reg_temp_over[i])
2479 w83627ehf_write_temp(data, data->reg_temp_over[i],
2480 data->temp_max[i]);
2481 if (data->reg_temp_hyst[i])
2482 w83627ehf_write_temp(data, data->reg_temp_hyst[i],
2483 data->temp_max_hyst[i]);
45633fb3
JD		 2484 if (i > 2)
2485 continue;
7e630bb5
JD		 2486 if (data->have_temp_offset & (1 << i))
2487 w83627ehf_write_value(data,
2488 W83627EHF_REG_TEMP_OFFSET[i],
2489 data->temp_offset[i]);
2490 }
2491
2492 /* Restore other settings */
2493 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
2494 if (sio_data->kind == nct6775) {
2495 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
2496 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
2497 }
2498
2499 /* Force re-reading all values */
2500 data->valid = 0;
2501 mutex_unlock(&data->update_lock);
2502
2503 return 0;
2504}
2505
2506static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
2507 .suspend = w83627ehf_suspend,
2508 .resume = w83627ehf_resume,
e3b20b3f
HJ		 2509 .freeze = w83627ehf_suspend,
2510 .restore = w83627ehf_resume,
7e630bb5
JD		 2511};
2512
2513#define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
2514#else
2515#define W83627EHF_DEV_PM_OPS NULL
2516#endif /* CONFIG_PM */
2517
1ea6dd38 2518static struct platform_driver w83627ehf_driver = {
cdaf7934 2519 .driver = {
1ea6dd38 2520 .name = DRVNAME,
7e630bb5 2521 .pm = W83627EHF_DEV_PM_OPS,
cdaf7934 2522 },
1ea6dd38 2523 .probe = w83627ehf_probe,
9e5e9b7a 2524 .remove = w83627ehf_remove,
08e7e278
JD		 2525};
2526
1ea6dd38
DH		 2527/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2528static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2529 struct w83627ehf_sio_data *sio_data)
08e7e278 2530{
6f7805a8
UKK		 2531 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2532 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2533 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2534 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2535 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2536 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2537 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2538 static const char sio_name_NCT6775[] __initconst = "NCT6775F";
2539 static const char sio_name_NCT6776[] __initconst = "NCT6776F";
1ea6dd38 2540
08e7e278 2541 u16 val;
1ea6dd38 2542 const char *sio_name;
0d023530 2543 int err;
08e7e278 2544
0d023530
KS		 2545 err = superio_enter(sioaddr);
2546 if (err)
2547 return err;
08e7e278 2548
67b671bc
JD		 2549 if (force_id)
2550 val = force_id;
2551 else
2552 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2553 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2554 switch (val & SIO_ID_MASK) {
657c93b1 2555 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2556 sio_data->kind = w83627ehf;
2557 sio_name = sio_name_W83627EHF;
2558 break;
657c93b1 2559 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2560 sio_data->kind = w83627ehf;
2561 sio_name = sio_name_W83627EHG;
2562 break;
2563 case SIO_W83627DHG_ID:
2564 sio_data->kind = w83627dhg;
2565 sio_name = sio_name_W83627DHG;
657c93b1 2566 break;
c1e48dce
JD		 2567 case SIO_W83627DHG_P_ID:
2568 sio_data->kind = w83627dhg_p;
2569 sio_name = sio_name_W83627DHG_P;
2570 break;
eff7687d
JD		 2571 case SIO_W83627UHG_ID:
2572 sio_data->kind = w83627uhg;
2573 sio_name = sio_name_W83627UHG;
2574 break;
237c8d2f
GJ		 2575 case SIO_W83667HG_ID:
2576 sio_data->kind = w83667hg;
2577 sio_name = sio_name_W83667HG;
2578 break;
c39aedaf
GR		 2579 case SIO_W83667HG_B_ID:
2580 sio_data->kind = w83667hg_b;
2581 sio_name = sio_name_W83667HG_B;
2582 break;
ec3e5a16
GR		 2583 case SIO_NCT6775_ID:
2584 sio_data->kind = nct6775;
2585 sio_name = sio_name_NCT6775;
2586 break;
2587 case SIO_NCT6776_ID:
2588 sio_data->kind = nct6776;
2589 sio_name = sio_name_NCT6776;
2590 break;
657c93b1 2591 default:
9f66036b 2592 if (val != 0xffff)
abdc6fd1 2593 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2594 superio_exit(sioaddr);
08e7e278
JD		 2595 return -ENODEV;
2596 }
2597
1ea6dd38
DH		 2598 /* We have a known chip, find the HWM I/O address */
2599 superio_select(sioaddr, W83627EHF_LD_HWM);
2600 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2601 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2602 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2603 if (*addr == 0) {
abdc6fd1 2604 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2605 superio_exit(sioaddr);
08e7e278
JD		 2606 return -ENODEV;
2607 }
2608
2609 /* Activate logical device if needed */
1ea6dd38 2610 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2611 if (!(val & 0x01)) {
b55f3757 2612 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
1ea6dd38 2613 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2614 }
1ea6dd38
DH		 2615
2616 superio_exit(sioaddr);
abdc6fd1 2617 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2618 sio_data->sioreg = sioaddr;
08e7e278 2619
08e7e278
JD		 2620 return 0;
2621}
2622
8969e84d
GR		 2623/*
2624 * when Super-I/O functions move to a separate file, the Super-I/O
1ea6dd38
DH		 2625 * bus will manage the lifetime of the device and this module will only keep
2626 * track of the w83627ehf driver. But since we platform_device_alloc(), we
8969e84d
GR		 2627 * must keep track of the device
2628 */
1ea6dd38
DH		 2629static struct platform_device *pdev;
2630
08e7e278
JD		 2631static int __init sensors_w83627ehf_init(void)
2632{
1ea6dd38
DH		 2633 int err;
2634 unsigned short address;
2635 struct resource res;
2636 struct w83627ehf_sio_data sio_data;
2637
8969e84d
GR		 2638 /*
2639 * initialize sio_data->kind and sio_data->sioreg.
1ea6dd38
DH		 2640 *
2641 * when Super-I/O functions move to a separate file, the Super-I/O
2642 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
8969e84d
GR		 2643 * w83627ehf hardware monitor, and call probe()
2644 */
1ea6dd38
DH		 2645 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2646 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2647 return -ENODEV;
2648
1ea6dd38
DH		 2649 err = platform_driver_register(&w83627ehf_driver);
2650 if (err)
2651 goto exit;
2652
e7e1ca6e
GR		 2653 pdev = platform_device_alloc(DRVNAME, address);
2654 if (!pdev) {
1ea6dd38 2655 err = -ENOMEM;
abdc6fd1 2656 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2657 goto exit_unregister;
2658 }
2659
2660 err = platform_device_add_data(pdev, &sio_data,
2661 sizeof(struct w83627ehf_sio_data));
2662 if (err) {
abdc6fd1 2663 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2664 goto exit_device_put;
2665 }
2666
2667 memset(&res, 0, sizeof(res));
2668 res.name = DRVNAME;
2669 res.start = address + IOREGION_OFFSET;
2670 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2671 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2672
2673 err = acpi_check_resource_conflict(&res);
2674 if (err)
18632f84 2675 goto exit_device_put;
b9acb64a 2676
1ea6dd38
DH		 2677 err = platform_device_add_resources(pdev, &res, 1);
2678 if (err) {
abdc6fd1 2679 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2680 goto exit_device_put;
2681 }
2682
2683 /* platform_device_add calls probe() */
2684 err = platform_device_add(pdev);
2685 if (err) {
abdc6fd1 2686 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2687 goto exit_device_put;
2688 }
2689
2690 return 0;
2691
2692exit_device_put:
2693 platform_device_put(pdev);
2694exit_unregister:
2695 platform_driver_unregister(&w83627ehf_driver);
2696exit:
2697 return err;
08e7e278
JD		 2698}
2699
2700static void __exit sensors_w83627ehf_exit(void)
2701{
1ea6dd38
DH		 2702 platform_device_unregister(pdev);
2703 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2704}
2705
7c81c60f 2706MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
08e7e278
JD		 2707MODULE_DESCRIPTION("W83627EHF driver");
2708MODULE_LICENSE("GPL");
2709
2710module_init(sensors_w83627ehf_init);
2711module_exit(sensors_w83627ehf_exit);
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