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hwmon: (it87) Print proper names for the IT8771E and IT8772E
[mirror_ubuntu-artful-kernel.git] / drivers / hwmon / w83627ehf.c
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08e7e278 1/*
8969e84d
GR		 2 * w83627ehf - Driver for the hardware monitoring functionality of
3 * the Winbond W83627EHF Super-I/O chip
7e630bb5 4 * Copyright (C) 2005-2012 Jean Delvare <khali@linux-fr.org>
8969e84d
GR		 5 * Copyright (C) 2006 Yuan Mu (Winbond),
6 * Rudolf Marek <r.marek@assembler.cz>
7 * David Hubbard <david.c.hubbard@gmail.com>
8 * Daniel J Blueman <daniel.blueman@gmail.com>
9 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
10 *
11 * Shamelessly ripped from the w83627hf driver
12 * Copyright (C) 2003 Mark Studebaker
13 *
14 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 * in testing and debugging this driver.
16 *
17 * This driver also supports the W83627EHG, which is the lead-free
18 * version of the W83627EHF.
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 * Supports the following chips:
35 *
36 * Chip #vin #fan #pwm #temp chip IDs man ID
37 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
38 * 0x8860 0xa1
39 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
40 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
41 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
42 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
43 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
44 * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 * nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
46 */
08e7e278 47
abdc6fd1
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
08e7e278
JD		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
1ea6dd38
DH		 53#include <linux/jiffies.h>
54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
412fec82 56#include <linux/hwmon-sysfs.h>
fc18d6c0 57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
b9acb64a 60#include <linux/acpi.h>
6055fae8 61#include <linux/io.h>
08e7e278
JD		 62#include "lm75.h"
63
eff7687d
JD		 64enum kinds {
65 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
66 w83667hg, w83667hg_b, nct6775, nct6776,
67};
08e7e278 68
1ea6dd38 69/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 70static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 71 "w83627ehf",
72 "w83627dhg",
c1e48dce 73 "w83627dhg",
eff7687d 74 "w83627uhg",
237c8d2f 75 "w83667hg",
c39aedaf 76 "w83667hg",
ec3e5a16
GR		 77 "nct6775",
78 "nct6776",
1ea6dd38
DH		 79};
80
67b671bc
JD		 81static unsigned short force_id;
82module_param(force_id, ushort, 0);
83MODULE_PARM_DESC(force_id, "Override the detected device ID");
84
d42e869a
ID		 85static unsigned short fan_debounce;
86module_param(fan_debounce, ushort, 0);
87MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
88
1ea6dd38 89#define DRVNAME "w83627ehf"
08e7e278 90
657c93b1 91/*
1ea6dd38 92 * Super-I/O constants and functions
657c93b1 93 */
08e7e278
JD		 94
95#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 96#define W83667HG_LD_VID 0x0d
08e7e278
JD		 97
98#define SIO_REG_LDSEL 0x07 /* Logical device select */
99#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 100#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 101#define SIO_REG_ENABLE 0x30 /* Logical device enable */
102#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 103#define SIO_REG_VID_CTRL 0xF0 /* VID control */
104#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 105
657c93b1
DH		 106#define SIO_W83627EHF_ID 0x8850
107#define SIO_W83627EHG_ID 0x8860
108#define SIO_W83627DHG_ID 0xa020
c1e48dce 109#define SIO_W83627DHG_P_ID 0xb070
eff7687d 110#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 111#define SIO_W83667HG_ID 0xa510
c39aedaf 112#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 113#define SIO_NCT6775_ID 0xb470
114#define SIO_NCT6776_ID 0xc330
657c93b1 115#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 116
117static inline void
1ea6dd38 118superio_outb(int ioreg, int reg, int val)
08e7e278 119{
1ea6dd38
DH		 120 outb(reg, ioreg);
121 outb(val, ioreg + 1);
08e7e278
JD		 122}
123
124static inline int
1ea6dd38 125superio_inb(int ioreg, int reg)
08e7e278 126{
1ea6dd38
DH		 127 outb(reg, ioreg);
128 return inb(ioreg + 1);
08e7e278
JD		 129}
130
131static inline void
1ea6dd38 132superio_select(int ioreg, int ld)
08e7e278 133{
1ea6dd38
DH		 134 outb(SIO_REG_LDSEL, ioreg);
135 outb(ld, ioreg + 1);
08e7e278
JD		 136}
137
138static inline void
1ea6dd38 139superio_enter(int ioreg)
08e7e278 140{
1ea6dd38
DH		 141 outb(0x87, ioreg);
142 outb(0x87, ioreg);
08e7e278
JD		 143}
144
145static inline void
1ea6dd38 146superio_exit(int ioreg)
08e7e278 147{
022b75a3 148 outb(0xaa, ioreg);
1ea6dd38
DH		 149 outb(0x02, ioreg);
150 outb(0x02, ioreg + 1);
08e7e278
JD		 151}
152
153/*
154 * ISA constants
155 */
156
e7e1ca6e 157#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 158#define IOREGION_OFFSET 5
159#define IOREGION_LENGTH 2
1ea6dd38
DH		 160#define ADDR_REG_OFFSET 0
161#define DATA_REG_OFFSET 1
08e7e278
JD		 162
163#define W83627EHF_REG_BANK 0x4E
164#define W83627EHF_REG_CONFIG 0x40
657c93b1 165
8969e84d
GR		 166/*
167 * Not currently used:
657c93b1
DH		 168 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
169 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
170 * REG_MAN_ID is at port 0x4f
8969e84d
GR		 171 * REG_CHIP_ID is at port 0x58
172 */
08e7e278
JD		 173
174static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
175static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
176
cf0676fe
RM		 177/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
178#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
179 (0x554 + (((nr) - 7) * 2)))
180#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
181 (0x555 + (((nr) - 7) * 2)))
182#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
183 (0x550 + (nr) - 7))
184
d36cf32c
GR		 185static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
186static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
187static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
188static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 189
190/* Fan clock dividers are spread over the following five registers */
191#define W83627EHF_REG_FANDIV1 0x47
192#define W83627EHF_REG_FANDIV2 0x4B
193#define W83627EHF_REG_VBAT 0x5D
194#define W83627EHF_REG_DIODE 0x59
195#define W83627EHF_REG_SMI_OVT 0x4C
196
ec3e5a16
GR		 197/* NCT6775F has its own fan divider registers */
198#define NCT6775_REG_FANDIV1 0x506
199#define NCT6775_REG_FANDIV2 0x507
d42e869a 200#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 201
a4589dbb
JD		 202#define W83627EHF_REG_ALARM1 0x459
203#define W83627EHF_REG_ALARM2 0x45A
204#define W83627EHF_REG_ALARM3 0x45B
205
363a12a4
DA		 206#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
207#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
208
08c79950 209/* SmartFan registers */
41e9a062
DB		 210#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
211#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
212
08c79950
RM		 213/* DC or PWM output fan configuration */
214static const u8 W83627EHF_REG_PWM_ENABLE[] = {
215 0x04, /* SYS FAN0 output mode and PWM mode */
216 0x04, /* CPU FAN0 output mode and PWM mode */
217 0x12, /* AUX FAN mode */
41e9a062 218 0x62, /* CPU FAN1 mode */
08c79950
RM		 219};
220
221static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
222static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
223
224/* FAN Duty Cycle, be used to control */
279af1a9
GR		 225static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
226static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 227static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
228
08c79950 229/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 230static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
231static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
232static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 233
279af1a9 234static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 235 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 236static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 237 = { 0xff, 0x68, 0xff, 0x6a };
238
279af1a9
GR		 239static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
240static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
241 = { 0x68, 0x6a, 0x6c };
08c79950 242
840e191d
GR		 243static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
244
ec3e5a16
GR		 245static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
246static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
247static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
248static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
249static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
250static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
251static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
252static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 253static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 254static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
255
256static const u16 NCT6775_REG_TEMP[]
257 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
258static const u16 NCT6775_REG_TEMP_CONFIG[]
259 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
260static const u16 NCT6775_REG_TEMP_HYST[]
261 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
262static const u16 NCT6775_REG_TEMP_OVER[]
263 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
264static const u16 NCT6775_REG_TEMP_SOURCE[]
265 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
266
d36cf32c
GR		 267static const char *const w83667hg_b_temp_label[] = {
268 "SYSTIN",
269 "CPUTIN",
270 "AUXTIN",
271 "AMDTSI",
272 "PECI Agent 1",
273 "PECI Agent 2",
274 "PECI Agent 3",
275 "PECI Agent 4"
276};
277
ec3e5a16
GR		 278static const char *const nct6775_temp_label[] = {
279 "",
280 "SYSTIN",
281 "CPUTIN",
282 "AUXTIN",
283 "AMD SB-TSI",
284 "PECI Agent 0",
285 "PECI Agent 1",
286 "PECI Agent 2",
287 "PECI Agent 3",
288 "PECI Agent 4",
289 "PECI Agent 5",
290 "PECI Agent 6",
291 "PECI Agent 7",
292 "PCH_CHIP_CPU_MAX_TEMP",
293 "PCH_CHIP_TEMP",
294 "PCH_CPU_TEMP",
295 "PCH_MCH_TEMP",
296 "PCH_DIM0_TEMP",
297 "PCH_DIM1_TEMP",
298 "PCH_DIM2_TEMP",
299 "PCH_DIM3_TEMP"
300};
301
302static const char *const nct6776_temp_label[] = {
303 "",
304 "SYSTIN",
305 "CPUTIN",
306 "AUXTIN",
307 "SMBUSMASTER 0",
308 "SMBUSMASTER 1",
309 "SMBUSMASTER 2",
310 "SMBUSMASTER 3",
311 "SMBUSMASTER 4",
312 "SMBUSMASTER 5",
313 "SMBUSMASTER 6",
314 "SMBUSMASTER 7",
315 "PECI Agent 0",
316 "PECI Agent 1",
317 "PCH_CHIP_CPU_MAX_TEMP",
318 "PCH_CHIP_TEMP",
319 "PCH_CPU_TEMP",
320 "PCH_MCH_TEMP",
321 "PCH_DIM0_TEMP",
322 "PCH_DIM1_TEMP",
323 "PCH_DIM2_TEMP",
324 "PCH_DIM3_TEMP",
325 "BYTE_TEMP"
326};
327
328#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 329
17296feb 330static int is_word_sized(u16 reg)
bce26c58 331{
ec3e5a16 332 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 333 || (reg & 0xff00) == 0x200)
334 && ((reg & 0x00ff) == 0x50
335 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 336 || (reg & 0x00ff) == 0x55))
337 || (reg & 0xfff0) == 0x630
338 || reg == 0x640 || reg == 0x642
339 || ((reg & 0xfff0) == 0x650
340 && (reg & 0x000f) >= 0x06)
341 || reg == 0x73 || reg == 0x75 || reg == 0x77
342 );
bce26c58
GR		 343}
344
08e7e278
JD		 345/*
346 * Conversions
347 */
348
08c79950
RM		 349/* 1 is PWM mode, output in ms */
350static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
351{
352 return mode ? 100 * reg : 400 * reg;
353}
354
355static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
356{
2a844c14
GR		 357 return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
358 1, 255);
08c79950
RM		 359}
360
26bc440e 361static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 362{
26bc440e 363 if (reg == 0 || reg == 255)
08e7e278 364 return 0;
26bc440e
GR		 365 return 1350000U / (reg << divreg);
366}
367
368static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
369{
370 if ((reg & 0xff1f) == 0xff1f)
371 return 0;
372
373 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
374
375 if (reg == 0)
376 return 0;
377
378 return 1350000U / reg;
379}
380
381static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
382{
383 if (reg == 0 || reg == 0xffff)
384 return 0;
385
386 /*
387 * Even though the registers are 16 bit wide, the fan divisor
388 * still applies.
389 */
390 return 1350000U / (reg << divreg);
08e7e278
JD		 391}
392
393static inline unsigned int
394div_from_reg(u8 reg)
395{
396 return 1 << reg;
397}
398
8969e84d
GR		 399/*
400 * Some of the voltage inputs have internal scaling, the tables below
401 * contain 8 (the ADC LSB in mV) * scaling factor * 100
402 */
eff7687d
JD		 403static const u16 scale_in_common[10] = {
404 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
405};
406static const u16 scale_in_w83627uhg[9] = {
407 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
408};
cf0676fe 409
eff7687d 410static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 411{
eff7687d 412 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 413}
414
eff7687d 415static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 416{
2a844c14 417 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
cf0676fe
RM		 418}
419
08e7e278
JD		 420/*
421 * Data structures and manipulation thereof
422 */
423
424struct w83627ehf_data {
1ea6dd38
DH		 425 int addr; /* IO base of hw monitor block */
426 const char *name;
427
1beeffe4 428 struct device *hwmon_dev;
9a61bf63 429 struct mutex lock;
08e7e278 430
ec3e5a16
GR		 431 u16 reg_temp[NUM_REG_TEMP];
432 u16 reg_temp_over[NUM_REG_TEMP];
433 u16 reg_temp_hyst[NUM_REG_TEMP];
434 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 435 u8 temp_src[NUM_REG_TEMP];
436 const char * const *temp_label;
437
279af1a9
GR		 438 const u16 *REG_PWM;
439 const u16 *REG_TARGET;
440 const u16 *REG_FAN;
441 const u16 *REG_FAN_MIN;
442 const u16 *REG_FAN_START_OUTPUT;
443 const u16 *REG_FAN_STOP_OUTPUT;
444 const u16 *REG_FAN_STOP_TIME;
445 const u16 *REG_FAN_MAX_OUTPUT;
446 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 447 const u16 *scale_in;
da2e0255 448
26bc440e
GR		 449 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
450 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
451
9a61bf63 452 struct mutex update_lock;
08e7e278
JD		 453 char valid; /* !=0 if following fields are valid */
454 unsigned long last_updated; /* In jiffies */
455
456 /* Register values */
83cc8985 457 u8 bank; /* current register bank */
1ea6dd38 458 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 459 u8 in[10]; /* Register value */
460 u8 in_max[10]; /* Register value */
461 u8 in_min[10]; /* Register value */
3382a918 462 unsigned int rpm[5];
ec3e5a16 463 u16 fan_min[5];
08e7e278
JD		 464 u8 fan_div[5];
465 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 466 u8 has_fan_min; /* some fans don't have min register */
26bc440e 467 bool has_fan_div;
da667365 468 u8 temp_type[3];
840e191d 469 s8 temp_offset[3];
ec3e5a16
GR		 470 s16 temp[9];
471 s16 temp_max[9];
472 s16 temp_max_hyst[9];
a4589dbb 473 u32 alarms;
363a12a4 474 u8 caseopen;
08c79950
RM		 475
476 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
477 u8 pwm_enable[4]; /* 1->manual
8969e84d
GR		 478 * 2->thermal cruise mode (also called SmartFan I)
479 * 3->fan speed cruise mode
480 * 4->variable thermal cruise (also called
481 * SmartFan III)
482 * 5->enhanced variable thermal cruise (also called
483 * SmartFan IV)
484 */
b84bb518 485 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 486 u8 pwm_num; /* number of pwm */
08c79950
RM		 487 u8 pwm[4];
488 u8 target_temp[4];
489 u8 tolerance[4];
490
41e9a062
DB		 491 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
492 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
493 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
494 u8 fan_max_output[4]; /* maximum fan speed */
495 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 496
497 u8 vid;
498 u8 vrm;
a157d06d 499
ec3e5a16 500 u16 have_temp;
840e191d 501 u16 have_temp_offset;
eff7687d
JD		 502 u8 in6_skip:1;
503 u8 temp3_val_only:1;
7e630bb5
JD		 504
505#ifdef CONFIG_PM
506 /* Remember extra register values over suspend/resume */
507 u8 vbat;
508 u8 fandiv1;
509 u8 fandiv2;
510#endif
08e7e278
JD		 511};
512
1ea6dd38
DH		 513struct w83627ehf_sio_data {
514 int sioreg;
515 enum kinds kind;
516};
517
83cc8985
GR		 518/*
519 * On older chips, only registers 0x50-0x5f are banked.
520 * On more recent chips, all registers are banked.
521 * Assume that is the case and set the bank number for each access.
522 * Cache the bank number so it only needs to be set if it changes.
523 */
1ea6dd38 524static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 525{
83cc8985
GR		 526 u8 bank = reg >> 8;
527 if (data->bank != bank) {
1ea6dd38 528 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 529 outb_p(bank, data->addr + DATA_REG_OFFSET);
530 data->bank = bank;
08e7e278
JD		 531 }
532}
533
1ea6dd38 534static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 535{
08e7e278
JD		 536 int res, word_sized = is_word_sized(reg);
537
9a61bf63 538 mutex_lock(&data->lock);
08e7e278 539
1ea6dd38
DH		 540 w83627ehf_set_bank(data, reg);
541 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
542 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 543 if (word_sized) {
544 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 545 data->addr + ADDR_REG_OFFSET);
546 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 547 }
08e7e278 548
9a61bf63 549 mutex_unlock(&data->lock);
08e7e278
JD		 550 return res;
551}
552
e7e1ca6e
GR		 553static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
554 u16 value)
08e7e278 555{
08e7e278
JD		 556 int word_sized = is_word_sized(reg);
557
9a61bf63 558 mutex_lock(&data->lock);
08e7e278 559
1ea6dd38
DH		 560 w83627ehf_set_bank(data, reg);
561 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 562 if (word_sized) {
1ea6dd38 563 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 564 outb_p((reg & 0xff) + 1,
1ea6dd38 565 data->addr + ADDR_REG_OFFSET);
08e7e278 566 }
1ea6dd38 567 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 568
9a61bf63 569 mutex_unlock(&data->lock);
08e7e278
JD		 570 return 0;
571}
572
c5794cfa
JD		 573/* We left-align 8-bit temperature values to make the code simpler */
574static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
575{
576 u16 res;
577
578 res = w83627ehf_read_value(data, reg);
579 if (!is_word_sized(reg))
580 res <<= 8;
581
582 return res;
583}
584
585static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
586 u16 value)
587{
588 if (!is_word_sized(reg))
589 value >>= 8;
590 return w83627ehf_write_value(data, reg, value);
591}
592
ec3e5a16
GR		 593/* This function assumes that the caller holds data->update_lock */
594static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
595{
596 u8 reg;
597
598 switch (nr) {
599 case 0:
600 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
601 | (data->fan_div[0] & 0x7);
602 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
603 break;
604 case 1:
605 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
606 | ((data->fan_div[1] << 4) & 0x70);
607 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
58c3667d 608 break;
ec3e5a16
GR		 609 case 2:
610 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
611 | (data->fan_div[2] & 0x7);
612 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
613 break;
614 case 3:
615 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
616 | ((data->fan_div[3] << 4) & 0x70);
617 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
618 break;
619 }
620}
621
08e7e278 622/* This function assumes that the caller holds data->update_lock */
1ea6dd38 623static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 624{
08e7e278
JD		 625 u8 reg;
626
627 switch (nr) {
628 case 0:
1ea6dd38 629 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 630 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 631 /* fan5 input control bit is write only, compute the value */
632 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 633 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
634 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 635 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 636 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 637 break;
638 case 1:
1ea6dd38 639 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 640 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 641 /* fan5 input control bit is write only, compute the value */
642 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 643 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
644 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 645 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 646 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 647 break;
648 case 2:
1ea6dd38 649 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 650 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 651 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
652 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 653 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 654 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 655 break;
656 case 3:
1ea6dd38 657 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 658 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 659 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
660 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 661 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 662 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 663 break;
664 case 4:
1ea6dd38 665 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 666 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 667 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 668 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 669 break;
670 }
671}
672
ec3e5a16
GR		 673static void w83627ehf_write_fan_div_common(struct device *dev,
674 struct w83627ehf_data *data, int nr)
675{
a8b3a3a5 676 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 677
678 if (sio_data->kind == nct6776)
679 ; /* no dividers, do nothing */
680 else if (sio_data->kind == nct6775)
681 nct6775_write_fan_div(data, nr);
682 else
683 w83627ehf_write_fan_div(data, nr);
684}
685
686static void nct6775_update_fan_div(struct w83627ehf_data *data)
687{
688 u8 i;
689
690 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
691 data->fan_div[0] = i & 0x7;
692 data->fan_div[1] = (i & 0x70) >> 4;
693 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
694 data->fan_div[2] = i & 0x7;
695 if (data->has_fan & (1<<3))
696 data->fan_div[3] = (i & 0x70) >> 4;
697}
698
ea7be66c
MH		 699static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
700{
701 int i;
702
703 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
704 data->fan_div[0] = (i >> 4) & 0x03;
705 data->fan_div[1] = (i >> 6) & 0x03;
706 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
707 data->fan_div[2] = (i >> 6) & 0x03;
708 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
709 data->fan_div[0] |= (i >> 3) & 0x04;
710 data->fan_div[1] |= (i >> 4) & 0x04;
711 data->fan_div[2] |= (i >> 5) & 0x04;
712 if (data->has_fan & ((1 << 3) | (1 << 4))) {
713 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
714 data->fan_div[3] = i & 0x03;
715 data->fan_div[4] = ((i >> 2) & 0x03)
716 | ((i >> 5) & 0x04);
717 }
718 if (data->has_fan & (1 << 3)) {
719 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
720 data->fan_div[3] |= (i >> 5) & 0x04;
721 }
722}
723
ec3e5a16
GR		 724static void w83627ehf_update_fan_div_common(struct device *dev,
725 struct w83627ehf_data *data)
726{
a8b3a3a5 727 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 728
729 if (sio_data->kind == nct6776)
730 ; /* no dividers, do nothing */
731 else if (sio_data->kind == nct6775)
732 nct6775_update_fan_div(data);
733 else
734 w83627ehf_update_fan_div(data);
735}
736
737static void nct6775_update_pwm(struct w83627ehf_data *data)
738{
739 int i;
740 int pwmcfg, fanmodecfg;
741
742 for (i = 0; i < data->pwm_num; i++) {
743 pwmcfg = w83627ehf_read_value(data,
744 W83627EHF_REG_PWM_ENABLE[i]);
745 fanmodecfg = w83627ehf_read_value(data,
746 NCT6775_REG_FAN_MODE[i]);
747 data->pwm_mode[i] =
748 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
749 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
750 data->tolerance[i] = fanmodecfg & 0x0f;
751 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
752 }
753}
754
755static void w83627ehf_update_pwm(struct w83627ehf_data *data)
756{
757 int i;
758 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
759
760 for (i = 0; i < data->pwm_num; i++) {
761 if (!(data->has_fan & (1 << i)))
762 continue;
763
764 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
765 if (i != 1) {
766 pwmcfg = w83627ehf_read_value(data,
767 W83627EHF_REG_PWM_ENABLE[i]);
768 tolerance = w83627ehf_read_value(data,
769 W83627EHF_REG_TOLERANCE[i]);
770 }
771 data->pwm_mode[i] =
772 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
773 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
774 & 3) + 1;
775 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
776
777 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
778 }
779}
780
781static void w83627ehf_update_pwm_common(struct device *dev,
782 struct w83627ehf_data *data)
783{
a8b3a3a5 784 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 785
786 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
787 nct6775_update_pwm(data);
788 else
789 w83627ehf_update_pwm(data);
790}
791
08e7e278
JD		 792static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
793{
1ea6dd38 794 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 795 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16 796
08e7e278
JD		 797 int i;
798
9a61bf63 799 mutex_lock(&data->update_lock);
08e7e278 800
6b3e4645 801 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 802 || !data->valid) {
803 /* Fan clock dividers */
ec3e5a16 804 w83627ehf_update_fan_div_common(dev, data);
08e7e278 805
cf0676fe 806 /* Measured voltages and limits */
1ea6dd38 807 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 808 if ((i == 6) && data->in6_skip)
809 continue;
810
1ea6dd38 811 data->in[i] = w83627ehf_read_value(data,
cf0676fe 812 W83627EHF_REG_IN(i));
1ea6dd38 813 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 814 W83627EHF_REG_IN_MIN(i));
1ea6dd38 815 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 816 W83627EHF_REG_IN_MAX(i));
817 }
818
08e7e278
JD		 819 /* Measured fan speeds and limits */
820 for (i = 0; i < 5; i++) {
3382a918
GR		 821 u16 reg;
822
08e7e278
JD		 823 if (!(data->has_fan & (1 << i)))
824 continue;
825
3382a918
GR		 826 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
827 data->rpm[i] = data->fan_from_reg(reg,
828 data->fan_div[i]);
ec3e5a16
GR		 829
830 if (data->has_fan_min & (1 << i))
831 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 832 data->REG_FAN_MIN[i]);
08e7e278 833
8969e84d
GR		 834 /*
835 * If we failed to measure the fan speed and clock
836 * divider can be increased, let's try that for next
837 * time
838 */
26bc440e 839 if (data->has_fan_div
3382a918
GR		 840 && (reg >= 0xff || (sio_data->kind == nct6775
841 && reg == 0x00))
ec3e5a16 842 && data->fan_div[i] < 0x07) {
b55f3757
GR		 843 dev_dbg(dev,
844 "Increasing fan%d clock divider from %u to %u\n",
33725ad3 845 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 846 div_from_reg(data->fan_div[i] + 1));
847 data->fan_div[i]++;
ec3e5a16 848 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 849 /* Preserve min limit if possible */
ec3e5a16
GR		 850 if ((data->has_fan_min & (1 << i))
851 && data->fan_min[i] >= 2
08e7e278 852 && data->fan_min[i] != 255)
1ea6dd38 853 w83627ehf_write_value(data,
279af1a9 854 data->REG_FAN_MIN[i],
08e7e278
JD		 855 (data->fan_min[i] /= 2));
856 }
857 }
858
ec3e5a16
GR		 859 w83627ehf_update_pwm_common(dev, data);
860
da2e0255
GR		 861 for (i = 0; i < data->pwm_num; i++) {
862 if (!(data->has_fan & (1 << i)))
863 continue;
864
ec3e5a16
GR		 865 data->fan_start_output[i] =
866 w83627ehf_read_value(data,
867 data->REG_FAN_START_OUTPUT[i]);
868 data->fan_stop_output[i] =
869 w83627ehf_read_value(data,
870 data->REG_FAN_STOP_OUTPUT[i]);
871 data->fan_stop_time[i] =
872 w83627ehf_read_value(data,
873 data->REG_FAN_STOP_TIME[i]);
874
875 if (data->REG_FAN_MAX_OUTPUT &&
876 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 877 data->fan_max_output[i] =
878 w83627ehf_read_value(data,
ec3e5a16 879 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 880
ec3e5a16
GR		 881 if (data->REG_FAN_STEP_OUTPUT &&
882 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 883 data->fan_step_output[i] =
884 w83627ehf_read_value(data,
ec3e5a16 885 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 886
08c79950 887 data->target_temp[i] =
1ea6dd38 888 w83627ehf_read_value(data,
279af1a9 889 data->REG_TARGET[i]) &
08c79950 890 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 891 }
892
08e7e278 893 /* Measured temperatures and limits */
d36cf32c
GR		 894 for (i = 0; i < NUM_REG_TEMP; i++) {
895 if (!(data->have_temp & (1 << i)))
896 continue;
c5794cfa 897 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 898 data->reg_temp[i]);
899 if (data->reg_temp_over[i])
900 data->temp_max[i]
c5794cfa 901 = w83627ehf_read_temp(data,
ec3e5a16
GR		 902 data->reg_temp_over[i]);
903 if (data->reg_temp_hyst[i])
904 data->temp_max_hyst[i]
c5794cfa 905 = w83627ehf_read_temp(data,
ec3e5a16 906 data->reg_temp_hyst[i]);
45633fb3
JD		 907 if (i > 2)
908 continue;
840e191d
GR		 909 if (data->have_temp_offset & (1 << i))
910 data->temp_offset[i]
911 = w83627ehf_read_value(data,
912 W83627EHF_REG_TEMP_OFFSET[i]);
08e7e278
JD		 913 }
914
1ea6dd38 915 data->alarms = w83627ehf_read_value(data,
a4589dbb 916 W83627EHF_REG_ALARM1) |
1ea6dd38 917 (w83627ehf_read_value(data,
a4589dbb 918 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 919 (w83627ehf_read_value(data,
a4589dbb
JD		 920 W83627EHF_REG_ALARM3) << 16);
921
363a12a4
DA		 922 data->caseopen = w83627ehf_read_value(data,
923 W83627EHF_REG_CASEOPEN_DET);
924
08e7e278
JD		 925 data->last_updated = jiffies;
926 data->valid = 1;
927 }
928
9a61bf63 929 mutex_unlock(&data->update_lock);
08e7e278
JD		 930 return data;
931}
932
933/*
934 * Sysfs callback functions
935 */
cf0676fe
RM		 936#define show_in_reg(reg) \
937static ssize_t \
938show_##reg(struct device *dev, struct device_attribute *attr, \
939 char *buf) \
940{ \
941 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 942 struct sensor_device_attribute *sensor_attr = \
943 to_sensor_dev_attr(attr); \
cf0676fe 944 int nr = sensor_attr->index; \
eff7687d
JD		 945 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
946 data->scale_in)); \
cf0676fe
RM		 947}
948show_in_reg(in)
949show_in_reg(in_min)
950show_in_reg(in_max)
951
952#define store_in_reg(REG, reg) \
953static ssize_t \
e7e1ca6e
GR		 954store_in_##reg(struct device *dev, struct device_attribute *attr, \
955 const char *buf, size_t count) \
cf0676fe 956{ \
1ea6dd38 957 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 958 struct sensor_device_attribute *sensor_attr = \
959 to_sensor_dev_attr(attr); \
cf0676fe 960 int nr = sensor_attr->index; \
bce26c58
GR		 961 unsigned long val; \
962 int err; \
179c4fdb 963 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 964 if (err < 0) \
965 return err; \
cf0676fe 966 mutex_lock(&data->update_lock); \
eff7687d 967 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
1ea6dd38 968 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 969 data->in_##reg[nr]); \
970 mutex_unlock(&data->update_lock); \
971 return count; \
972}
973
974store_in_reg(MIN, min)
975store_in_reg(MAX, max)
976
e7e1ca6e
GR		 977static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
978 char *buf)
a4589dbb
JD		 979{
980 struct w83627ehf_data *data = w83627ehf_update_device(dev);
981 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
982 int nr = sensor_attr->index;
983 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
984}
985
cf0676fe
RM		 986static struct sensor_device_attribute sda_in_input[] = {
987 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
988 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
989 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
990 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
991 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
992 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
993 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
994 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
995 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
996 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
997};
998
a4589dbb
JD		 999static struct sensor_device_attribute sda_in_alarm[] = {
1000 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
1001 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
1002 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
1003 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
1004 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
1005 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
1006 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
1007 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
1008 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
1009 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
1010};
1011
cf0676fe 1012static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 1013 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
1014 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
1015 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
1016 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
1017 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
1018 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
1019 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
1020 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
1021 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
1022 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 1023};
1024
1025static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 1026 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1027 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1028 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1029 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1030 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1031 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1032 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1033 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1034 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1035 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 1036};
1037
ec3e5a16
GR		 1038static ssize_t
1039show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1040{
1041 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1042 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1043 int nr = sensor_attr->index;
3382a918 1044 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 1045}
1046
1047static ssize_t
1048show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1049{
1050 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1051 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1052 int nr = sensor_attr->index;
1053 return sprintf(buf, "%d\n",
26bc440e
GR		 1054 data->fan_from_reg_min(data->fan_min[nr],
1055 data->fan_div[nr]));
08e7e278 1056}
08e7e278
JD		 1057
1058static ssize_t
412fec82
YM		 1059show_fan_div(struct device *dev, struct device_attribute *attr,
1060 char *buf)
08e7e278
JD		 1061{
1062 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1063 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1064 int nr = sensor_attr->index;
1065 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1066}
1067
1068static ssize_t
412fec82
YM		 1069store_fan_min(struct device *dev, struct device_attribute *attr,
1070 const char *buf, size_t count)
08e7e278 1071{
1ea6dd38 1072 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1073 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1074 int nr = sensor_attr->index;
bce26c58
GR		 1075 unsigned long val;
1076 int err;
08e7e278
JD		 1077 unsigned int reg;
1078 u8 new_div;
1079
179c4fdb 1080 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1081 if (err < 0)
1082 return err;
1083
9a61bf63 1084 mutex_lock(&data->update_lock);
26bc440e
GR		 1085 if (!data->has_fan_div) {
1086 /*
1087 * Only NCT6776F for now, so we know that this is a 13 bit
1088 * register
1089 */
ec3e5a16
GR		 1090 if (!val) {
1091 val = 0xff1f;
1092 } else {
1093 if (val > 1350000U)
1094 val = 135000U;
1095 val = 1350000U / val;
1096 val = (val & 0x1f) | ((val << 3) & 0xff00);
1097 }
1098 data->fan_min[nr] = val;
1099 goto done; /* Leave fan divider alone */
1100 }
08e7e278
JD		 1101 if (!val) {
1102 /* No min limit, alarm disabled */
1103 data->fan_min[nr] = 255;
1104 new_div = data->fan_div[nr]; /* No change */
1105 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1106 } else if ((reg = 1350000U / val) >= 128 * 255) {
8969e84d
GR		 1107 /*
1108 * Speed below this value cannot possibly be represented,
1109 * even with the highest divider (128)
1110 */
08e7e278
JD		 1111 data->fan_min[nr] = 254;
1112 new_div = 7; /* 128 == (1 << 7) */
b55f3757
GR		 1113 dev_warn(dev,
1114 "fan%u low limit %lu below minimum %u, set to minimum\n",
1115 nr + 1, val, data->fan_from_reg_min(254, 7));
08e7e278 1116 } else if (!reg) {
8969e84d
GR		 1117 /*
1118 * Speed above this value cannot possibly be represented,
1119 * even with the lowest divider (1)
1120 */
08e7e278
JD		 1121 data->fan_min[nr] = 1;
1122 new_div = 0; /* 1 == (1 << 0) */
b55f3757
GR		 1123 dev_warn(dev,
1124 "fan%u low limit %lu above maximum %u, set to maximum\n",
1125 nr + 1, val, data->fan_from_reg_min(1, 0));
08e7e278 1126 } else {
8969e84d
GR		 1127 /*
1128 * Automatically pick the best divider, i.e. the one such
1129 * that the min limit will correspond to a register value
1130 * in the 96..192 range
1131 */
08e7e278
JD		 1132 new_div = 0;
1133 while (reg > 192 && new_div < 7) {
1134 reg >>= 1;
1135 new_div++;
1136 }
1137 data->fan_min[nr] = reg;
1138 }
1139
8969e84d
GR		 1140 /*
1141 * Write both the fan clock divider (if it changed) and the new
1142 * fan min (unconditionally)
1143 */
08e7e278 1144 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1145 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1146 nr + 1, div_from_reg(data->fan_div[nr]),
1147 div_from_reg(new_div));
1148 data->fan_div[nr] = new_div;
ec3e5a16 1149 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1150 /* Give the chip time to sample a new speed value */
1151 data->last_updated = jiffies;
08e7e278 1152 }
ec3e5a16 1153done:
279af1a9 1154 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1155 data->fan_min[nr]);
9a61bf63 1156 mutex_unlock(&data->update_lock);
08e7e278
JD		 1157
1158 return count;
1159}
1160
412fec82
YM		 1161static struct sensor_device_attribute sda_fan_input[] = {
1162 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1163 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1164 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1165 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1166 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1167};
08e7e278 1168
a4589dbb
JD		 1169static struct sensor_device_attribute sda_fan_alarm[] = {
1170 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1171 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1172 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1173 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1174 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1175};
1176
412fec82
YM		 1177static struct sensor_device_attribute sda_fan_min[] = {
1178 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1179 store_fan_min, 0),
1180 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1181 store_fan_min, 1),
1182 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1183 store_fan_min, 2),
1184 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1185 store_fan_min, 3),
1186 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1187 store_fan_min, 4),
1188};
08e7e278 1189
412fec82
YM		 1190static struct sensor_device_attribute sda_fan_div[] = {
1191 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1192 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1193 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1194 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1195 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1196};
1197
d36cf32c
GR		 1198static ssize_t
1199show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1200{
1201 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1202 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1203 int nr = sensor_attr->index;
1204 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1205}
1206
ec3e5a16 1207#define show_temp_reg(addr, reg) \
08e7e278 1208static ssize_t \
412fec82
YM		 1209show_##reg(struct device *dev, struct device_attribute *attr, \
1210 char *buf) \
08e7e278
JD		 1211{ \
1212 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1213 struct sensor_device_attribute *sensor_attr = \
1214 to_sensor_dev_attr(attr); \
412fec82 1215 int nr = sensor_attr->index; \
c5794cfa 1216 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
08e7e278 1217}
ec3e5a16
GR		 1218show_temp_reg(reg_temp, temp);
1219show_temp_reg(reg_temp_over, temp_max);
1220show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1221
ec3e5a16 1222#define store_temp_reg(addr, reg) \
08e7e278 1223static ssize_t \
412fec82
YM		 1224store_##reg(struct device *dev, struct device_attribute *attr, \
1225 const char *buf, size_t count) \
08e7e278 1226{ \
1ea6dd38 1227 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1228 struct sensor_device_attribute *sensor_attr = \
1229 to_sensor_dev_attr(attr); \
412fec82 1230 int nr = sensor_attr->index; \
bce26c58
GR		 1231 int err; \
1232 long val; \
179c4fdb 1233 err = kstrtol(buf, 10, &val); \
bce26c58
GR		 1234 if (err < 0) \
1235 return err; \
9a61bf63 1236 mutex_lock(&data->update_lock); \
c5794cfa
JD		 1237 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1238 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
9a61bf63 1239 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1240 return count; \
1241}
ec3e5a16
GR		 1242store_temp_reg(reg_temp_over, temp_max);
1243store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1244
840e191d
GR		 1245static ssize_t
1246show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
1247{
1248 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1249 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1250
1251 return sprintf(buf, "%d\n",
1252 data->temp_offset[sensor_attr->index] * 1000);
1253}
1254
1255static ssize_t
1256store_temp_offset(struct device *dev, struct device_attribute *attr,
1257 const char *buf, size_t count)
1258{
1259 struct w83627ehf_data *data = dev_get_drvdata(dev);
1260 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1261 int nr = sensor_attr->index;
1262 long val;
1263 int err;
1264
1265 err = kstrtol(buf, 10, &val);
1266 if (err < 0)
1267 return err;
1268
2a844c14 1269 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
840e191d
GR		 1270
1271 mutex_lock(&data->update_lock);
1272 data->temp_offset[nr] = val;
1273 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[nr], val);
1274 mutex_unlock(&data->update_lock);
1275 return count;
1276}
1277
da667365
JD		 1278static ssize_t
1279show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1280{
1281 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1282 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1283 int nr = sensor_attr->index;
1284 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1285}
1286
a157d06d 1287static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1288 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1289 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1290 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1291 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1292 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1293 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1294 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1295 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1296 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1297};
1298
1299static struct sensor_device_attribute sda_temp_label[] = {
1300 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1301 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1302 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1303 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1304 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1305 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1306 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1307 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1308 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1309};
1310
1311static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1312 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1313 store_temp_max, 0),
bce26c58 1314 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1315 store_temp_max, 1),
bce26c58
GR		 1316 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1317 store_temp_max, 2),
ec3e5a16
GR		 1318 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1319 store_temp_max, 3),
1320 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1321 store_temp_max, 4),
1322 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1323 store_temp_max, 5),
1324 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1325 store_temp_max, 6),
1326 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1327 store_temp_max, 7),
1328 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1329 store_temp_max, 8),
a157d06d
GJ		 1330};
1331
1332static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1333 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1334 store_temp_max_hyst, 0),
bce26c58 1335 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1336 store_temp_max_hyst, 1),
bce26c58
GR		 1337 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1338 store_temp_max_hyst, 2),
ec3e5a16
GR		 1339 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1340 store_temp_max_hyst, 3),
1341 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1342 store_temp_max_hyst, 4),
1343 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1344 store_temp_max_hyst, 5),
1345 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1346 store_temp_max_hyst, 6),
1347 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1348 store_temp_max_hyst, 7),
1349 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1350 store_temp_max_hyst, 8),
a157d06d
GJ		 1351};
1352
1353static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1354 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1355 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1356 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1357};
1358
1359static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1360 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1361 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1362 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1363};
08e7e278 1364
840e191d
GR		 1365static struct sensor_device_attribute sda_temp_offset[] = {
1366 SENSOR_ATTR(temp1_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1367 store_temp_offset, 0),
1368 SENSOR_ATTR(temp2_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1369 store_temp_offset, 1),
1370 SENSOR_ATTR(temp3_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1371 store_temp_offset, 2),
1372};
1373
08c79950 1374#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1375static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1376 char *buf) \
08c79950
RM		 1377{ \
1378 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1379 struct sensor_device_attribute *sensor_attr = \
1380 to_sensor_dev_attr(attr); \
08c79950
RM		 1381 int nr = sensor_attr->index; \
1382 return sprintf(buf, "%d\n", data->reg[nr]); \
1383}
1384
1385show_pwm_reg(pwm_mode)
1386show_pwm_reg(pwm_enable)
1387show_pwm_reg(pwm)
1388
1389static ssize_t
1390store_pwm_mode(struct device *dev, struct device_attribute *attr,
1391 const char *buf, size_t count)
1392{
1ea6dd38 1393 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 1394 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
a8b3a3a5 1395 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08c79950 1396 int nr = sensor_attr->index;
bce26c58
GR		 1397 unsigned long val;
1398 int err;
08c79950
RM		 1399 u16 reg;
1400
179c4fdb 1401 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1402 if (err < 0)
1403 return err;
1404
08c79950
RM		 1405 if (val > 1)
1406 return -EINVAL;
ad77c3e1
GR		 1407
1408 /* On NCT67766F, DC mode is only supported for pwm1 */
1409 if (sio_data->kind == nct6776 && nr && val != 1)
1410 return -EINVAL;
1411
08c79950 1412 mutex_lock(&data->update_lock);
1ea6dd38 1413 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1414 data->pwm_mode[nr] = val;
1415 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1416 if (!val)
1417 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1418 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1419 mutex_unlock(&data->update_lock);
1420 return count;
1421}
1422
1423static ssize_t
1424store_pwm(struct device *dev, struct device_attribute *attr,
1425 const char *buf, size_t count)
1426{
1ea6dd38 1427 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1428 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1429 int nr = sensor_attr->index;
bce26c58
GR		 1430 unsigned long val;
1431 int err;
1432
179c4fdb 1433 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1434 if (err < 0)
1435 return err;
1436
2a844c14 1437 val = clamp_val(val, 0, 255);
08c79950
RM		 1438
1439 mutex_lock(&data->update_lock);
1440 data->pwm[nr] = val;
279af1a9 1441 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1442 mutex_unlock(&data->update_lock);
1443 return count;
1444}
1445
1446static ssize_t
1447store_pwm_enable(struct device *dev, struct device_attribute *attr,
1448 const char *buf, size_t count)
1449{
1ea6dd38 1450 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 1451 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08c79950
RM		 1452 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1453 int nr = sensor_attr->index;
bce26c58
GR		 1454 unsigned long val;
1455 int err;
08c79950
RM		 1456 u16 reg;
1457
179c4fdb 1458 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1459 if (err < 0)
1460 return err;
1461
b84bb518 1462 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1463 return -EINVAL;
ec3e5a16
GR		 1464 /* SmartFan III mode is not supported on NCT6776F */
1465 if (sio_data->kind == nct6776 && val == 4)
1466 return -EINVAL;
1467
08c79950 1468 mutex_lock(&data->update_lock);
08c79950 1469 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1470 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1471 reg = w83627ehf_read_value(data,
1472 NCT6775_REG_FAN_MODE[nr]);
1473 reg &= 0x0f;
1474 reg |= (val - 1) << 4;
1475 w83627ehf_write_value(data,
1476 NCT6775_REG_FAN_MODE[nr], reg);
1477 } else {
1478 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1479 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1480 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1481 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1482 }
08c79950
RM		 1483 mutex_unlock(&data->update_lock);
1484 return count;
1485}
1486
1487
1488#define show_tol_temp(reg) \
1489static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1490 char *buf) \
1491{ \
1492 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1493 struct sensor_device_attribute *sensor_attr = \
1494 to_sensor_dev_attr(attr); \
08c79950 1495 int nr = sensor_attr->index; \
bce26c58 1496 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1497}
1498
1499show_tol_temp(tolerance)
1500show_tol_temp(target_temp)
1501
1502static ssize_t
1503store_target_temp(struct device *dev, struct device_attribute *attr,
1504 const char *buf, size_t count)
1505{
1ea6dd38 1506 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1507 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1508 int nr = sensor_attr->index;
bce26c58
GR		 1509 long val;
1510 int err;
1511
179c4fdb 1512 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1513 if (err < 0)
1514 return err;
1515
2a844c14 1516 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1517
1518 mutex_lock(&data->update_lock);
1519 data->target_temp[nr] = val;
279af1a9 1520 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1521 mutex_unlock(&data->update_lock);
1522 return count;
1523}
1524
1525static ssize_t
1526store_tolerance(struct device *dev, struct device_attribute *attr,
1527 const char *buf, size_t count)
1528{
1ea6dd38 1529 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 1530 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08c79950
RM		 1531 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1532 int nr = sensor_attr->index;
1533 u16 reg;
bce26c58
GR		 1534 long val;
1535 int err;
1536
179c4fdb 1537 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1538 if (err < 0)
1539 return err;
1540
08c79950 1541 /* Limit the temp to 0C - 15C */
2a844c14 1542 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1543
1544 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1545 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1546 /* Limit tolerance further for NCT6776F */
1547 if (sio_data->kind == nct6776 && val > 7)
1548 val = 7;
1549 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1550 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1551 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1552 } else {
1553 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1554 if (nr == 1)
1555 reg = (reg & 0x0f) | (val << 4);
1556 else
1557 reg = (reg & 0xf0) | val;
1558 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1559 }
1560 data->tolerance[nr] = val;
08c79950
RM		 1561 mutex_unlock(&data->update_lock);
1562 return count;
1563}
1564
1565static struct sensor_device_attribute sda_pwm[] = {
1566 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1567 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1568 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1569 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1570};
1571
1572static struct sensor_device_attribute sda_pwm_mode[] = {
1573 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1574 store_pwm_mode, 0),
1575 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1576 store_pwm_mode, 1),
1577 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1578 store_pwm_mode, 2),
1579 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1580 store_pwm_mode, 3),
1581};
1582
1583static struct sensor_device_attribute sda_pwm_enable[] = {
1584 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1585 store_pwm_enable, 0),
1586 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1587 store_pwm_enable, 1),
1588 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1589 store_pwm_enable, 2),
1590 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1591 store_pwm_enable, 3),
1592};
1593
1594static struct sensor_device_attribute sda_target_temp[] = {
1595 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1596 store_target_temp, 0),
1597 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1598 store_target_temp, 1),
1599 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1600 store_target_temp, 2),
1601 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1602 store_target_temp, 3),
1603};
1604
1605static struct sensor_device_attribute sda_tolerance[] = {
1606 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1607 store_tolerance, 0),
1608 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1609 store_tolerance, 1),
1610 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1611 store_tolerance, 2),
1612 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1613 store_tolerance, 3),
1614};
1615
08c79950
RM		 1616/* Smart Fan registers */
1617
1618#define fan_functions(reg, REG) \
1619static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1620 char *buf) \
1621{ \
1622 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1623 struct sensor_device_attribute *sensor_attr = \
1624 to_sensor_dev_attr(attr); \
08c79950
RM		 1625 int nr = sensor_attr->index; \
1626 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1627} \
08c79950
RM		 1628static ssize_t \
1629store_##reg(struct device *dev, struct device_attribute *attr, \
1630 const char *buf, size_t count) \
e7e1ca6e 1631{ \
1ea6dd38 1632 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1633 struct sensor_device_attribute *sensor_attr = \
1634 to_sensor_dev_attr(attr); \
08c79950 1635 int nr = sensor_attr->index; \
bce26c58
GR		 1636 unsigned long val; \
1637 int err; \
179c4fdb 1638 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1639 if (err < 0) \
1640 return err; \
2a844c14 1641 val = clamp_val(val, 1, 255); \
08c79950
RM		 1642 mutex_lock(&data->update_lock); \
1643 data->reg[nr] = val; \
da2e0255 1644 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1645 mutex_unlock(&data->update_lock); \
1646 return count; \
1647}
1648
41e9a062
DB		 1649fan_functions(fan_start_output, FAN_START_OUTPUT)
1650fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1651fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1652fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1653
1654#define fan_time_functions(reg, REG) \
1655static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1656 char *buf) \
1657{ \
1658 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1659 struct sensor_device_attribute *sensor_attr = \
1660 to_sensor_dev_attr(attr); \
08c79950
RM		 1661 int nr = sensor_attr->index; \
1662 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1663 step_time_from_reg(data->reg[nr], \
1664 data->pwm_mode[nr])); \
08c79950
RM		 1665} \
1666\
1667static ssize_t \
1668store_##reg(struct device *dev, struct device_attribute *attr, \
1669 const char *buf, size_t count) \
1670{ \
1ea6dd38 1671 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1672 struct sensor_device_attribute *sensor_attr = \
1673 to_sensor_dev_attr(attr); \
08c79950 1674 int nr = sensor_attr->index; \
bce26c58
GR		 1675 unsigned long val; \
1676 int err; \
179c4fdb 1677 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1678 if (err < 0) \
1679 return err; \
1680 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1681 mutex_lock(&data->update_lock); \
1682 data->reg[nr] = val; \
33fa9b62 1683 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1684 mutex_unlock(&data->update_lock); \
1685 return count; \
1686} \
1687
1688fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1689
1ea6dd38
DH		 1690static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1691 char *buf)
1692{
1693 struct w83627ehf_data *data = dev_get_drvdata(dev);
1694
1695 return sprintf(buf, "%s\n", data->name);
1696}
1697static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1698
1699static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1700 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1701 store_fan_stop_time, 3),
41e9a062
DB		 1702 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1703 store_fan_start_output, 3),
1704 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1705 store_fan_stop_output, 3),
1706 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1707 store_fan_max_output, 3),
1708 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1709 store_fan_step_output, 3),
08c79950
RM		 1710};
1711
eff7687d
JD		 1712static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1713 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1714 store_fan_stop_time, 2),
1715 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1716 store_fan_start_output, 2),
1717 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1718 store_fan_stop_output, 2),
1719};
1720
08c79950
RM		 1721static struct sensor_device_attribute sda_sf3_arrays[] = {
1722 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1723 store_fan_stop_time, 0),
1724 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1725 store_fan_stop_time, 1),
41e9a062
DB		 1726 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1727 store_fan_start_output, 0),
1728 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1729 store_fan_start_output, 1),
41e9a062
DB		 1730 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1731 store_fan_stop_output, 0),
1732 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1733 store_fan_stop_output, 1),
da2e0255 1734};
41e9a062 1735
da2e0255
GR		 1736
1737/*
1738 * pwm1 and pwm3 don't support max and step settings on all chips.
1739 * Need to check support while generating/removing attribute files.
1740 */
1741static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1742 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1743 store_fan_max_output, 0),
1744 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1745 store_fan_step_output, 0),
41e9a062
DB		 1746 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1747 store_fan_max_output, 1),
1748 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1749 store_fan_step_output, 1),
da2e0255
GR		 1750 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1751 store_fan_max_output, 2),
1752 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1753 store_fan_step_output, 2),
08c79950
RM		 1754};
1755
fc18d6c0
JD		 1756static ssize_t
1757show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1758{
1759 struct w83627ehf_data *data = dev_get_drvdata(dev);
1760 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1761}
1762static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1763
363a12a4
DA		 1764
1765/* Case open detection */
1766
1767static ssize_t
1768show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1769{
1770 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1771
1772 return sprintf(buf, "%d\n",
1773 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1774}
1775
1776static ssize_t
1777clear_caseopen(struct device *dev, struct device_attribute *attr,
1778 const char *buf, size_t count)
1779{
1780 struct w83627ehf_data *data = dev_get_drvdata(dev);
1781 unsigned long val;
1782 u16 reg, mask;
1783
179c4fdb 1784 if (kstrtoul(buf, 10, &val) || val != 0)
363a12a4
DA		 1785 return -EINVAL;
1786
1787 mask = to_sensor_dev_attr_2(attr)->nr;
1788
1789 mutex_lock(&data->update_lock);
1790 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1791 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1792 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1793 data->valid = 0; /* Force cache refresh */
1794 mutex_unlock(&data->update_lock);
1795
1796 return count;
1797}
1798
1799static struct sensor_device_attribute_2 sda_caseopen[] = {
1800 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1801 clear_caseopen, 0x80, 0x10),
1802 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1803 clear_caseopen, 0x40, 0x40),
1804};
1805
08e7e278 1806/*
1ea6dd38 1807 * Driver and device management
08e7e278
JD		 1808 */
1809
c18beb5b
DH		 1810static void w83627ehf_device_remove_files(struct device *dev)
1811{
8969e84d
GR		 1812 /*
1813 * some entries in the following arrays may not have been used in
1814 * device_create_file(), but device_remove_file() will ignore them
1815 */
c18beb5b 1816 int i;
1ea6dd38 1817 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1818
1819 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1820 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1821 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1822 struct sensor_device_attribute *attr =
1823 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1824 if (data->REG_FAN_STEP_OUTPUT &&
1825 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1826 device_remove_file(dev, &attr->dev_attr);
1827 }
eff7687d
JD		 1828 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1829 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
c18beb5b
DH		 1830 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1831 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1832 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1833 if ((i == 6) && data->in6_skip)
1834 continue;
c18beb5b
DH		 1835 device_remove_file(dev, &sda_in_input[i].dev_attr);
1836 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1837 device_remove_file(dev, &sda_in_min[i].dev_attr);
1838 device_remove_file(dev, &sda_in_max[i].dev_attr);
1839 }
1840 for (i = 0; i < 5; i++) {
1841 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1842 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1843 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1844 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1845 }
237c8d2f 1846 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1847 device_remove_file(dev, &sda_pwm[i].dev_attr);
1848 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1849 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1850 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1851 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1852 }
d36cf32c
GR		 1853 for (i = 0; i < NUM_REG_TEMP; i++) {
1854 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1855 continue;
1856 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1857 device_remove_file(dev, &sda_temp_label[i].dev_attr);
eff7687d
JD		 1858 if (i == 2 && data->temp3_val_only)
1859 continue;
a157d06d
GJ		 1860 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1861 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1862 if (i > 2)
1863 continue;
a157d06d
GJ		 1864 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1865 device_remove_file(dev, &sda_temp_type[i].dev_attr);
840e191d 1866 device_remove_file(dev, &sda_temp_offset[i].dev_attr);
a157d06d 1867 }
c18beb5b 1868
363a12a4
DA		 1869 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1870 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1871
1ea6dd38 1872 device_remove_file(dev, &dev_attr_name);
cbe311f2 1873 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1874}
08e7e278 1875
1ea6dd38 1876/* Get the monitoring functions started */
6c931ae1 1877static inline void w83627ehf_init_device(struct w83627ehf_data *data,
bf164c58 1878 enum kinds kind)
08e7e278
JD		 1879{
1880 int i;
da667365 1881 u8 tmp, diode;
08e7e278
JD		 1882
1883 /* Start monitoring is needed */
1ea6dd38 1884 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1885 if (!(tmp & 0x01))
1ea6dd38 1886 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1887 tmp | 0x01);
1888
d36cf32c
GR		 1889 /* Enable temperature sensors if needed */
1890 for (i = 0; i < NUM_REG_TEMP; i++) {
1891 if (!(data->have_temp & (1 << i)))
1892 continue;
ec3e5a16 1893 if (!data->reg_temp_config[i])
d36cf32c 1894 continue;
1ea6dd38 1895 tmp = w83627ehf_read_value(data,
ec3e5a16 1896 data->reg_temp_config[i]);
08e7e278 1897 if (tmp & 0x01)
1ea6dd38 1898 w83627ehf_write_value(data,
ec3e5a16 1899 data->reg_temp_config[i],
08e7e278
JD		 1900 tmp & 0xfe);
1901 }
d3130f0e
JD		 1902
1903 /* Enable VBAT monitoring if needed */
1904 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1905 if (!(tmp & 0x01))
1906 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1907
1908 /* Get thermal sensor types */
bf164c58
JD		 1909 switch (kind) {
1910 case w83627ehf:
1911 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1912 break;
eff7687d
JD		 1913 case w83627uhg:
1914 diode = 0x00;
1915 break;
bf164c58
JD		 1916 default:
1917 diode = 0x70;
1918 }
da667365 1919 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1920 const char *label = NULL;
1921
1922 if (data->temp_label)
1923 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1924
1925 /* Digital source overrides analog type */
bfa02b0d 1926 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1927 data->temp_type[i] = 6;
bfa02b0d 1928 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1929 data->temp_type[i] = 5;
1930 else if ((tmp & (0x02 << i)))
bf164c58 1931 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1932 else
1933 data->temp_type[i] = 4; /* thermistor */
1934 }
08e7e278
JD		 1935}
1936
ec3e5a16
GR		 1937static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1938 int r1, int r2)
1939{
1940 u16 tmp;
1941
1942 tmp = data->temp_src[r1];
1943 data->temp_src[r1] = data->temp_src[r2];
1944 data->temp_src[r2] = tmp;
1945
1946 tmp = data->reg_temp[r1];
1947 data->reg_temp[r1] = data->reg_temp[r2];
1948 data->reg_temp[r2] = tmp;
1949
1950 tmp = data->reg_temp_over[r1];
1951 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1952 data->reg_temp_over[r2] = tmp;
1953
1954 tmp = data->reg_temp_hyst[r1];
1955 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1956 data->reg_temp_hyst[r2] = tmp;
1957
1958 tmp = data->reg_temp_config[r1];
1959 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1960 data->reg_temp_config[r2] = tmp;
1961}
1962
6c931ae1 1963static void
6ba71de5
JD		 1964w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1965{
1966 int i;
1967
1968 for (i = 0; i < n_temp; i++) {
1969 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1970 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1971 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1972 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1973 }
1974}
1975
6c931ae1 1976static void
03f5de2b
JD		 1977w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1978 struct w83627ehf_data *data)
1979{
1980 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1981
eff7687d
JD		 1982 /* The W83627UHG is simple, only two fan inputs, no config */
1983 if (sio_data->kind == w83627uhg) {
1984 data->has_fan = 0x03; /* fan1 and fan2 */
1985 data->has_fan_min = 0x03;
1986 return;
1987 }
1988
03f5de2b
JD		 1989 superio_enter(sio_data->sioreg);
1990
1991 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1992 if (sio_data->kind == nct6775) {
1993 /* On NCT6775, fan4 shares pins with the fdc interface */
1994 fan3pin = 1;
1995 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1996 fan4min = 0;
1997 fan5pin = 0;
1998 } else if (sio_data->kind == nct6776) {
585c0fd8
GR		 1999 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
2000
2001 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2002 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
2003
2004 if (regval & 0x80)
2005 fan3pin = gpok;
2006 else
2007 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2008
2009 if (regval & 0x40)
2010 fan4pin = gpok;
2011 else
2012 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2013
2014 if (regval & 0x20)
2015 fan5pin = gpok;
2016 else
2017 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2018
03f5de2b
JD		 2019 fan4min = fan4pin;
2020 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2021 fan3pin = 1;
2022 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
2023 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2024 fan4min = fan4pin;
2025 } else {
2026 fan3pin = 1;
2027 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2028 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2029 fan4min = fan4pin;
2030 }
2031
2032 superio_exit(sio_data->sioreg);
2033
2034 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2035 data->has_fan |= (fan3pin << 2);
2036 data->has_fan_min |= (fan3pin << 2);
2037
2038 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2039 /*
2040 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
2041 * register
2042 */
2043 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2044 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2045 } else {
2046 /*
2047 * It looks like fan4 and fan5 pins can be alternatively used
2048 * as fan on/off switches, but fan5 control is write only :/
2049 * We assume that if the serial interface is disabled, designers
2050 * connected fan5 as input unless they are emitting log 1, which
2051 * is not the default.
2052 */
2053 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2054 if ((regval & (1 << 2)) && fan4pin) {
2055 data->has_fan |= (1 << 3);
2056 data->has_fan_min |= (1 << 3);
2057 }
2058 if (!(regval & (1 << 1)) && fan5pin) {
2059 data->has_fan |= (1 << 4);
2060 data->has_fan_min |= (1 << 4);
2061 }
2062 }
2063}
2064
6c931ae1 2065static int w83627ehf_probe(struct platform_device *pdev)
08e7e278 2066{
1ea6dd38 2067 struct device *dev = &pdev->dev;
a8b3a3a5 2068 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08e7e278 2069 struct w83627ehf_data *data;
1ea6dd38 2070 struct resource *res;
03f5de2b 2071 u8 en_vrm10;
08e7e278
JD		 2072 int i, err = 0;
2073
1ea6dd38
DH		 2074 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2075 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 2076 err = -EBUSY;
1ea6dd38
DH		 2077 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2078 (unsigned long)res->start,
2079 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 2080 goto exit;
2081 }
2082
32260d94
GR		 2083 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2084 GFP_KERNEL);
e7e1ca6e 2085 if (!data) {
08e7e278
JD		 2086 err = -ENOMEM;
2087 goto exit_release;
2088 }
08e7e278 2089
1ea6dd38 2090 data->addr = res->start;
9a61bf63 2091 mutex_init(&data->lock);
9a61bf63 2092 mutex_init(&data->update_lock);
1ea6dd38 2093 data->name = w83627ehf_device_names[sio_data->kind];
3300fb4f 2094 data->bank = 0xff; /* Force initial bank selection */
1ea6dd38 2095 platform_set_drvdata(pdev, data);
08e7e278 2096
237c8d2f
GJ		 2097 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2098 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
eff7687d
JD		 2099 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2100 switch (sio_data->kind) {
2101 default:
2102 data->pwm_num = 4;
2103 break;
2104 case w83667hg:
2105 case w83667hg_b:
2106 case nct6775:
2107 case nct6776:
2108 data->pwm_num = 3;
2109 break;
2110 case w83627uhg:
2111 data->pwm_num = 2;
2112 break;
2113 }
08e7e278 2114
6ba71de5 2115 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 2116 data->have_temp = 0x07;
ec3e5a16
GR		 2117
2118 /* Deal with temperature register setup first. */
2119 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2120 int mask = 0;
2121
2122 /*
2123 * Display temperature sensor output only if it monitors
2124 * a source other than one already reported. Always display
2125 * first three temperature registers, though.
2126 */
2127 for (i = 0; i < NUM_REG_TEMP; i++) {
2128 u8 src;
2129
2130 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2131 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2132 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2133 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2134
2135 src = w83627ehf_read_value(data,
2136 NCT6775_REG_TEMP_SOURCE[i]);
2137 src &= 0x1f;
2138 if (src && !(mask & (1 << src))) {
2139 data->have_temp |= 1 << i;
2140 mask |= 1 << src;
2141 }
2142
2143 data->temp_src[i] = src;
2144
2145 /*
2146 * Now do some register swapping if index 0..2 don't
2147 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2148 * Idea is to have the first three attributes
2149 * report SYSTIN, CPUIN, and AUXIN if possible
2150 * without overriding the basic system configuration.
2151 */
2152 if (i > 0 && data->temp_src[0] != 1
2153 && data->temp_src[i] == 1)
2154 w82627ehf_swap_tempreg(data, 0, i);
2155 if (i > 1 && data->temp_src[1] != 2
2156 && data->temp_src[i] == 2)
2157 w82627ehf_swap_tempreg(data, 1, i);
2158 if (i > 2 && data->temp_src[2] != 3
2159 && data->temp_src[i] == 3)
2160 w82627ehf_swap_tempreg(data, 2, i);
2161 }
2162 if (sio_data->kind == nct6776) {
2163 /*
2164 * On NCT6776, AUXTIN and VIN3 pins are shared.
2165 * Only way to detect it is to check if AUXTIN is used
2166 * as a temperature source, and if that source is
2167 * enabled.
2168 *
2169 * If that is the case, disable in6, which reports VIN3.
2170 * Otherwise disable temp3.
2171 */
2172 if (data->temp_src[2] == 3) {
2173 u8 reg;
2174
2175 if (data->reg_temp_config[2])
2176 reg = w83627ehf_read_value(data,
2177 data->reg_temp_config[2]);
2178 else
2179 reg = 0; /* Assume AUXTIN is used */
2180
2181 if (reg & 0x01)
2182 data->have_temp &= ~(1 << 2);
2183 else
2184 data->in6_skip = 1;
2185 }
02309ad2
GR		 2186 data->temp_label = nct6776_temp_label;
2187 } else {
2188 data->temp_label = nct6775_temp_label;
ec3e5a16 2189 }
840e191d
GR		 2190 data->have_temp_offset = data->have_temp & 0x07;
2191 for (i = 0; i < 3; i++) {
2192 if (data->temp_src[i] > 3)
2193 data->have_temp_offset &= ~(1 << i);
2194 }
d36cf32c
GR		 2195 } else if (sio_data->kind == w83667hg_b) {
2196 u8 reg;
2197
6ba71de5
JD		 2198 w83627ehf_set_temp_reg_ehf(data, 4);
2199
ec3e5a16
GR		 2200 /*
2201 * Temperature sources are selected with bank 0, registers 0x49
2202 * and 0x4a.
2203 */
d36cf32c
GR		 2204 reg = w83627ehf_read_value(data, 0x4a);
2205 data->temp_src[0] = reg >> 5;
2206 reg = w83627ehf_read_value(data, 0x49);
2207 data->temp_src[1] = reg & 0x07;
ec3e5a16 2208 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 2209
2210 /*
2211 * W83667HG-B has another temperature register at 0x7e.
2212 * The temperature source is selected with register 0x7d.
2213 * Support it if the source differs from already reported
2214 * sources.
2215 */
2216 reg = w83627ehf_read_value(data, 0x7d);
2217 reg &= 0x07;
2218 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2219 && reg != data->temp_src[2]) {
2220 data->temp_src[3] = reg;
2221 data->have_temp |= 1 << 3;
2222 }
2223
2224 /*
2225 * Chip supports either AUXTIN or VIN3. Try to find out which
2226 * one.
2227 */
2228 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2229 if (data->temp_src[2] == 2 && (reg & 0x01))
2230 data->have_temp &= ~(1 << 2);
2231
2232 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2233 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2234 data->in6_skip = 1;
2235
eff7687d 2236 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2237 data->have_temp_offset = data->have_temp & 0x07;
2238 for (i = 0; i < 3; i++) {
2239 if (data->temp_src[i] > 2)
2240 data->have_temp_offset &= ~(1 << i);
2241 }
eff7687d
JD		 2242 } else if (sio_data->kind == w83627uhg) {
2243 u8 reg;
2244
2245 w83627ehf_set_temp_reg_ehf(data, 3);
2246
2247 /*
aacb6b00 2248 * Temperature sources for temp2 and temp3 are selected with
eff7687d
JD		 2249 * bank 0, registers 0x49 and 0x4a.
2250 */
2251 data->temp_src[0] = 0; /* SYSTIN */
2252 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2253 /* Adjust to have the same mapping as other source registers */
2254 if (reg == 0)
aacb6b00 2255 data->temp_src[1] = 1;
eff7687d 2256 else if (reg >= 2 && reg <= 5)
aacb6b00 2257 data->temp_src[1] = reg + 2;
eff7687d
JD		 2258 else /* should never happen */
2259 data->have_temp &= ~(1 << 1);
2260 reg = w83627ehf_read_value(data, 0x4a);
2261 data->temp_src[2] = reg >> 5;
2262
2263 /*
2264 * Skip temp3 if source is invalid or the same as temp1
2265 * or temp2.
2266 */
2267 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2268 data->temp_src[2] == data->temp_src[0] ||
2269 ((data->have_temp & (1 << 1)) &&
2270 data->temp_src[2] == data->temp_src[1]))
2271 data->have_temp &= ~(1 << 2);
2272 else
2273 data->temp3_val_only = 1; /* No limit regs */
2274
2275 data->in6_skip = 1; /* No VIN3 */
2276
d36cf32c 2277 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2278 data->have_temp_offset = data->have_temp & 0x03;
2279 for (i = 0; i < 3; i++) {
2280 if (data->temp_src[i] > 1)
2281 data->have_temp_offset &= ~(1 << i);
2282 }
ec3e5a16 2283 } else {
6ba71de5
JD		 2284 w83627ehf_set_temp_reg_ehf(data, 3);
2285
ec3e5a16 2286 /* Temperature sources are fixed */
6ba71de5
JD		 2287
2288 if (sio_data->kind == w83667hg) {
2289 u8 reg;
2290
2291 /*
2292 * Chip supports either AUXTIN or VIN3. Try to find
2293 * out which one.
2294 */
2295 reg = w83627ehf_read_value(data,
2296 W83627EHF_REG_TEMP_CONFIG[2]);
2297 if (reg & 0x01)
2298 data->have_temp &= ~(1 << 2);
2299 else
2300 data->in6_skip = 1;
ec3e5a16 2301 }
840e191d 2302 data->have_temp_offset = data->have_temp & 0x07;
a157d06d
GJ		 2303 }
2304
ec3e5a16 2305 if (sio_data->kind == nct6775) {
26bc440e
GR		 2306 data->has_fan_div = true;
2307 data->fan_from_reg = fan_from_reg16;
2308 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2309 data->REG_PWM = NCT6775_REG_PWM;
2310 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2311 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2312 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2313 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2314 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2315 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2316 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2317 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2318 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2319 data->has_fan_div = false;
2320 data->fan_from_reg = fan_from_reg13;
2321 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2322 data->REG_PWM = NCT6775_REG_PWM;
2323 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2324 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2325 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2326 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2327 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2328 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2329 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2330 data->has_fan_div = true;
2331 data->fan_from_reg = fan_from_reg8;
2332 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2333 data->REG_PWM = W83627EHF_REG_PWM;
2334 data->REG_TARGET = W83627EHF_REG_TARGET;
2335 data->REG_FAN = W83627EHF_REG_FAN;
2336 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2337 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2338 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2339 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2340 data->REG_FAN_MAX_OUTPUT =
2341 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2342 data->REG_FAN_STEP_OUTPUT =
2343 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2344 } else {
26bc440e
GR		 2345 data->has_fan_div = true;
2346 data->fan_from_reg = fan_from_reg8;
2347 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2348 data->REG_PWM = W83627EHF_REG_PWM;
2349 data->REG_TARGET = W83627EHF_REG_TARGET;
2350 data->REG_FAN = W83627EHF_REG_FAN;
2351 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2352 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2353 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2354 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2355 data->REG_FAN_MAX_OUTPUT =
2356 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2357 data->REG_FAN_STEP_OUTPUT =
2358 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2359 }
da2e0255 2360
eff7687d
JD		 2361 /* Setup input voltage scaling factors */
2362 if (sio_data->kind == w83627uhg)
2363 data->scale_in = scale_in_w83627uhg;
2364 else
2365 data->scale_in = scale_in_common;
2366
08e7e278 2367 /* Initialize the chip */
bf164c58 2368 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2369
fc18d6c0
JD		 2370 data->vrm = vid_which_vrm();
2371 superio_enter(sio_data->sioreg);
fc18d6c0 2372 /* Read VID value */
ec3e5a16
GR		 2373 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2374 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
8969e84d
GR		 2375 /*
2376 * W83667HG has different pins for VID input and output, so
2377 * we can get the VID input values directly at logical device D
2378 * 0xe3.
2379 */
237c8d2f
GJ		 2380 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2381 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2382 err = device_create_file(dev, &dev_attr_cpu0_vid);
2383 if (err)
2384 goto exit_release;
eff7687d 2385 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 2386 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2387 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
8969e84d
GR		 2388 /*
2389 * Set VID input sensibility if needed. In theory the
2390 * BIOS should have set it, but in practice it's not
2391 * always the case. We only do it for the W83627EHF/EHG
2392 * because the W83627DHG is more complex in this
2393 * respect.
2394 */
237c8d2f
GJ		 2395 if (sio_data->kind == w83627ehf) {
2396 en_vrm10 = superio_inb(sio_data->sioreg,
2397 SIO_REG_EN_VRM10);
2398 if ((en_vrm10 & 0x08) && data->vrm == 90) {
b55f3757
GR		 2399 dev_warn(dev,
2400 "Setting VID input voltage to TTL\n");
237c8d2f
GJ		 2401 superio_outb(sio_data->sioreg,
2402 SIO_REG_EN_VRM10,
2403 en_vrm10 & ~0x08);
2404 } else if (!(en_vrm10 & 0x08)
2405 && data->vrm == 100) {
b55f3757
GR		 2406 dev_warn(dev,
2407 "Setting VID input voltage to VRM10\n");
237c8d2f
GJ		 2408 superio_outb(sio_data->sioreg,
2409 SIO_REG_EN_VRM10,
2410 en_vrm10 | 0x08);
2411 }
2412 }
2413
2414 data->vid = superio_inb(sio_data->sioreg,
2415 SIO_REG_VID_DATA);
2416 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2417 data->vid &= 0x3f;
2418
2419 err = device_create_file(dev, &dev_attr_cpu0_vid);
2420 if (err)
2421 goto exit_release;
2422 } else {
b55f3757
GR		 2423 dev_info(dev,
2424 "VID pins in output mode, CPU VID not available\n");
237c8d2f 2425 }
fc18d6c0
JD		 2426 }
2427
d42e869a
ID		 2428 if (fan_debounce &&
2429 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2430 u8 tmp;
2431
2432 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2433 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2434 if (sio_data->kind == nct6776)
2435 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2436 0x3e | tmp);
2437 else
2438 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2439 0x1e | tmp);
2440 pr_info("Enabled fan debounce for chip %s\n", data->name);
2441 }
2442
1ea6dd38 2443 superio_exit(sio_data->sioreg);
08c79950 2444
03f5de2b 2445 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 2446
ea7be66c 2447 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2448 w83627ehf_update_fan_div_common(dev, data);
2449
b84bb518
GR		 2450 /* Read pwm data to save original values */
2451 w83627ehf_update_pwm_common(dev, data);
2452 for (i = 0; i < data->pwm_num; i++)
2453 data->pwm_enable_orig[i] = data->pwm_enable[i];
2454
08e7e278 2455 /* Register sysfs hooks */
e7e1ca6e
GR		 2456 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2457 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2458 if (err)
c18beb5b 2459 goto exit_remove;
e7e1ca6e 2460 }
08c79950 2461
da2e0255
GR		 2462 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2463 struct sensor_device_attribute *attr =
2464 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2465 if (data->REG_FAN_STEP_OUTPUT &&
2466 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2467 err = device_create_file(dev, &attr->dev_attr);
2468 if (err)
2469 goto exit_remove;
2470 }
2471 }
eff7687d
JD		 2472 /* if fan3 and fan4 are enabled create the sf3 files for them */
2473 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2474 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2475 err = device_create_file(dev,
2476 &sda_sf3_arrays_fan3[i].dev_attr);
2477 if (err)
2478 goto exit_remove;
2479 }
237c8d2f 2480 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2481 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2482 err = device_create_file(dev,
2483 &sda_sf3_arrays_fan4[i].dev_attr);
2484 if (err)
c18beb5b
DH		 2485 goto exit_remove;
2486 }
08c79950 2487
a157d06d
GJ		 2488 for (i = 0; i < data->in_num; i++) {
2489 if ((i == 6) && data->in6_skip)
2490 continue;
c18beb5b
DH		 2491 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2492 || (err = device_create_file(dev,
2493 &sda_in_alarm[i].dev_attr))
2494 || (err = device_create_file(dev,
2495 &sda_in_min[i].dev_attr))
2496 || (err = device_create_file(dev,
2497 &sda_in_max[i].dev_attr)))
2498 goto exit_remove;
a157d06d 2499 }
cf0676fe 2500
412fec82 2501 for (i = 0; i < 5; i++) {
08c79950 2502 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2503 if ((err = device_create_file(dev,
2504 &sda_fan_input[i].dev_attr))
2505 || (err = device_create_file(dev,
ec3e5a16 2506 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2507 goto exit_remove;
ec3e5a16
GR		 2508 if (sio_data->kind != nct6776) {
2509 err = device_create_file(dev,
2510 &sda_fan_div[i].dev_attr);
2511 if (err)
2512 goto exit_remove;
2513 }
2514 if (data->has_fan_min & (1 << i)) {
2515 err = device_create_file(dev,
2516 &sda_fan_min[i].dev_attr);
2517 if (err)
2518 goto exit_remove;
2519 }
237c8d2f 2520 if (i < data->pwm_num &&
c18beb5b
DH		 2521 ((err = device_create_file(dev,
2522 &sda_pwm[i].dev_attr))
2523 || (err = device_create_file(dev,
2524 &sda_pwm_mode[i].dev_attr))
2525 || (err = device_create_file(dev,
2526 &sda_pwm_enable[i].dev_attr))
2527 || (err = device_create_file(dev,
2528 &sda_target_temp[i].dev_attr))
2529 || (err = device_create_file(dev,
2530 &sda_tolerance[i].dev_attr))))
2531 goto exit_remove;
08c79950 2532 }
08e7e278 2533 }
08c79950 2534
d36cf32c
GR		 2535 for (i = 0; i < NUM_REG_TEMP; i++) {
2536 if (!(data->have_temp & (1 << i)))
a157d06d 2537 continue;
d36cf32c
GR		 2538 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2539 if (err)
2540 goto exit_remove;
2541 if (data->temp_label) {
2542 err = device_create_file(dev,
2543 &sda_temp_label[i].dev_attr);
2544 if (err)
2545 goto exit_remove;
2546 }
eff7687d
JD		 2547 if (i == 2 && data->temp3_val_only)
2548 continue;
ec3e5a16
GR		 2549 if (data->reg_temp_over[i]) {
2550 err = device_create_file(dev,
2551 &sda_temp_max[i].dev_attr);
2552 if (err)
2553 goto exit_remove;
2554 }
2555 if (data->reg_temp_hyst[i]) {
2556 err = device_create_file(dev,
2557 &sda_temp_max_hyst[i].dev_attr);
2558 if (err)
2559 goto exit_remove;
2560 }
d36cf32c 2561 if (i > 2)
ec3e5a16
GR		 2562 continue;
2563 if ((err = device_create_file(dev,
a157d06d
GJ		 2564 &sda_temp_alarm[i].dev_attr))
2565 || (err = device_create_file(dev,
2566 &sda_temp_type[i].dev_attr)))
c18beb5b 2567 goto exit_remove;
840e191d
GR		 2568 if (data->have_temp_offset & (1 << i)) {
2569 err = device_create_file(dev,
2570 &sda_temp_offset[i].dev_attr);
2571 if (err)
2572 goto exit_remove;
2573 }
a157d06d 2574 }
c18beb5b 2575
363a12a4
DA		 2576 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2577 if (err)
2578 goto exit_remove;
2579
2580 if (sio_data->kind == nct6776) {
2581 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2582 if (err)
2583 goto exit_remove;
2584 }
2585
1ea6dd38
DH		 2586 err = device_create_file(dev, &dev_attr_name);
2587 if (err)
2588 goto exit_remove;
2589
1beeffe4
TJ		 2590 data->hwmon_dev = hwmon_device_register(dev);
2591 if (IS_ERR(data->hwmon_dev)) {
2592 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2593 goto exit_remove;
2594 }
08e7e278
JD		 2595
2596 return 0;
2597
c18beb5b
DH		 2598exit_remove:
2599 w83627ehf_device_remove_files(dev);
08e7e278 2600exit_release:
1ea6dd38 2601 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2602exit:
2603 return err;
2604}
2605
281dfd0b 2606static int w83627ehf_remove(struct platform_device *pdev)
08e7e278 2607{
1ea6dd38 2608 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2609
1beeffe4 2610 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2611 w83627ehf_device_remove_files(&pdev->dev);
2612 release_region(data->addr, IOREGION_LENGTH);
08e7e278
JD		 2613
2614 return 0;
2615}
2616
7e630bb5
JD		 2617#ifdef CONFIG_PM
2618static int w83627ehf_suspend(struct device *dev)
2619{
2620 struct w83627ehf_data *data = w83627ehf_update_device(dev);
a8b3a3a5 2621 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
7e630bb5
JD		 2622
2623 mutex_lock(&data->update_lock);
2624 data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
2625 if (sio_data->kind == nct6775) {
2626 data->fandiv1 = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
2627 data->fandiv2 = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
2628 }
2629 mutex_unlock(&data->update_lock);
2630
2631 return 0;
2632}
2633
2634static int w83627ehf_resume(struct device *dev)
2635{
2636 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 2637 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
7e630bb5
JD		 2638 int i;
2639
2640 mutex_lock(&data->update_lock);
2641 data->bank = 0xff; /* Force initial bank selection */
2642
2643 /* Restore limits */
2644 for (i = 0; i < data->in_num; i++) {
2645 if ((i == 6) && data->in6_skip)
2646 continue;
2647
2648 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
2649 data->in_min[i]);
2650 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2651 data->in_max[i]);
2652 }
2653
2654 for (i = 0; i < 5; i++) {
2655 if (!(data->has_fan_min & (1 << i)))
2656 continue;
2657
2658 w83627ehf_write_value(data, data->REG_FAN_MIN[i],
2659 data->fan_min[i]);
2660 }
2661
2662 for (i = 0; i < NUM_REG_TEMP; i++) {
2663 if (!(data->have_temp & (1 << i)))
2664 continue;
2665
2666 if (data->reg_temp_over[i])
2667 w83627ehf_write_temp(data, data->reg_temp_over[i],
2668 data->temp_max[i]);
2669 if (data->reg_temp_hyst[i])
2670 w83627ehf_write_temp(data, data->reg_temp_hyst[i],
2671 data->temp_max_hyst[i]);
45633fb3
JD		 2672 if (i > 2)
2673 continue;
7e630bb5
JD		 2674 if (data->have_temp_offset & (1 << i))
2675 w83627ehf_write_value(data,
2676 W83627EHF_REG_TEMP_OFFSET[i],
2677 data->temp_offset[i]);
2678 }
2679
2680 /* Restore other settings */
2681 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
2682 if (sio_data->kind == nct6775) {
2683 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
2684 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
2685 }
2686
2687 /* Force re-reading all values */
2688 data->valid = 0;
2689 mutex_unlock(&data->update_lock);
2690
2691 return 0;
2692}
2693
2694static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
2695 .suspend = w83627ehf_suspend,
2696 .resume = w83627ehf_resume,
e3b20b3f
HJ		 2697 .freeze = w83627ehf_suspend,
2698 .restore = w83627ehf_resume,
7e630bb5
JD		 2699};
2700
2701#define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
2702#else
2703#define W83627EHF_DEV_PM_OPS NULL
2704#endif /* CONFIG_PM */
2705
1ea6dd38 2706static struct platform_driver w83627ehf_driver = {
cdaf7934 2707 .driver = {
87218842 2708 .owner = THIS_MODULE,
1ea6dd38 2709 .name = DRVNAME,
7e630bb5 2710 .pm = W83627EHF_DEV_PM_OPS,
cdaf7934 2711 },
1ea6dd38 2712 .probe = w83627ehf_probe,
9e5e9b7a 2713 .remove = w83627ehf_remove,
08e7e278
JD		 2714};
2715
1ea6dd38
DH		 2716/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2717static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2718 struct w83627ehf_sio_data *sio_data)
08e7e278 2719{
6f7805a8
UKK		 2720 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2721 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2722 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2723 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2724 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2725 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2726 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2727 static const char sio_name_NCT6775[] __initconst = "NCT6775F";
2728 static const char sio_name_NCT6776[] __initconst = "NCT6776F";
1ea6dd38 2729
08e7e278 2730 u16 val;
1ea6dd38 2731 const char *sio_name;
08e7e278 2732
1ea6dd38 2733 superio_enter(sioaddr);
08e7e278 2734
67b671bc
JD		 2735 if (force_id)
2736 val = force_id;
2737 else
2738 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2739 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2740 switch (val & SIO_ID_MASK) {
657c93b1 2741 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2742 sio_data->kind = w83627ehf;
2743 sio_name = sio_name_W83627EHF;
2744 break;
657c93b1 2745 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2746 sio_data->kind = w83627ehf;
2747 sio_name = sio_name_W83627EHG;
2748 break;
2749 case SIO_W83627DHG_ID:
2750 sio_data->kind = w83627dhg;
2751 sio_name = sio_name_W83627DHG;
657c93b1 2752 break;
c1e48dce
JD		 2753 case SIO_W83627DHG_P_ID:
2754 sio_data->kind = w83627dhg_p;
2755 sio_name = sio_name_W83627DHG_P;
2756 break;
eff7687d
JD		 2757 case SIO_W83627UHG_ID:
2758 sio_data->kind = w83627uhg;
2759 sio_name = sio_name_W83627UHG;
2760 break;
237c8d2f
GJ		 2761 case SIO_W83667HG_ID:
2762 sio_data->kind = w83667hg;
2763 sio_name = sio_name_W83667HG;
2764 break;
c39aedaf
GR		 2765 case SIO_W83667HG_B_ID:
2766 sio_data->kind = w83667hg_b;
2767 sio_name = sio_name_W83667HG_B;
2768 break;
ec3e5a16
GR		 2769 case SIO_NCT6775_ID:
2770 sio_data->kind = nct6775;
2771 sio_name = sio_name_NCT6775;
2772 break;
2773 case SIO_NCT6776_ID:
2774 sio_data->kind = nct6776;
2775 sio_name = sio_name_NCT6776;
2776 break;
657c93b1 2777 default:
9f66036b 2778 if (val != 0xffff)
abdc6fd1 2779 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2780 superio_exit(sioaddr);
08e7e278
JD		 2781 return -ENODEV;
2782 }
2783
1ea6dd38
DH		 2784 /* We have a known chip, find the HWM I/O address */
2785 superio_select(sioaddr, W83627EHF_LD_HWM);
2786 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2787 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2788 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2789 if (*addr == 0) {
abdc6fd1 2790 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2791 superio_exit(sioaddr);
08e7e278
JD		 2792 return -ENODEV;
2793 }
2794
2795 /* Activate logical device if needed */
1ea6dd38 2796 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2797 if (!(val & 0x01)) {
b55f3757 2798 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
1ea6dd38 2799 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2800 }
1ea6dd38
DH		 2801
2802 superio_exit(sioaddr);
abdc6fd1 2803 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2804 sio_data->sioreg = sioaddr;
08e7e278 2805
08e7e278
JD		 2806 return 0;
2807}
2808
8969e84d
GR		 2809/*
2810 * when Super-I/O functions move to a separate file, the Super-I/O
1ea6dd38
DH		 2811 * bus will manage the lifetime of the device and this module will only keep
2812 * track of the w83627ehf driver. But since we platform_device_alloc(), we
8969e84d
GR		 2813 * must keep track of the device
2814 */
1ea6dd38
DH		 2815static struct platform_device *pdev;
2816
08e7e278
JD		 2817static int __init sensors_w83627ehf_init(void)
2818{
1ea6dd38
DH		 2819 int err;
2820 unsigned short address;
2821 struct resource res;
2822 struct w83627ehf_sio_data sio_data;
2823
8969e84d
GR		 2824 /*
2825 * initialize sio_data->kind and sio_data->sioreg.
1ea6dd38
DH		 2826 *
2827 * when Super-I/O functions move to a separate file, the Super-I/O
2828 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
8969e84d
GR		 2829 * w83627ehf hardware monitor, and call probe()
2830 */
1ea6dd38
DH		 2831 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2832 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2833 return -ENODEV;
2834
1ea6dd38
DH		 2835 err = platform_driver_register(&w83627ehf_driver);
2836 if (err)
2837 goto exit;
2838
e7e1ca6e
GR		 2839 pdev = platform_device_alloc(DRVNAME, address);
2840 if (!pdev) {
1ea6dd38 2841 err = -ENOMEM;
abdc6fd1 2842 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2843 goto exit_unregister;
2844 }
2845
2846 err = platform_device_add_data(pdev, &sio_data,
2847 sizeof(struct w83627ehf_sio_data));
2848 if (err) {
abdc6fd1 2849 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2850 goto exit_device_put;
2851 }
2852
2853 memset(&res, 0, sizeof(res));
2854 res.name = DRVNAME;
2855 res.start = address + IOREGION_OFFSET;
2856 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2857 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2858
2859 err = acpi_check_resource_conflict(&res);
2860 if (err)
18632f84 2861 goto exit_device_put;
b9acb64a 2862
1ea6dd38
DH		 2863 err = platform_device_add_resources(pdev, &res, 1);
2864 if (err) {
abdc6fd1 2865 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2866 goto exit_device_put;
2867 }
2868
2869 /* platform_device_add calls probe() */
2870 err = platform_device_add(pdev);
2871 if (err) {
abdc6fd1 2872 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2873 goto exit_device_put;
2874 }
2875
2876 return 0;
2877
2878exit_device_put:
2879 platform_device_put(pdev);
2880exit_unregister:
2881 platform_driver_unregister(&w83627ehf_driver);
2882exit:
2883 return err;
08e7e278
JD		 2884}
2885
2886static void __exit sensors_w83627ehf_exit(void)
2887{
1ea6dd38
DH		 2888 platform_device_unregister(pdev);
2889 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2890}
2891
2892MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2893MODULE_DESCRIPTION("W83627EHF driver");
2894MODULE_LICENSE("GPL");
2895
2896module_init(sensors_w83627ehf_init);
2897module_exit(sensors_w83627ehf_exit);
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