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hwmon: (w83627ehf) Fixed most checkpatch warnings and errors
[mirror_ubuntu-zesty-kernel.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
e7e1ca6e 3 the Winbond W83627EHF Super-I/O chip
08e7e278 4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
e7e1ca6e
GR		 6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
08e7e278
JD		 9
10 Shamelessly ripped from the w83627hf driver
11 Copyright (C) 2003 Mark Studebaker
12
13 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
14 in testing and debugging this driver.
15
8dd2d2ca
JD		 16 This driver also supports the W83627EHG, which is the lead-free
17 version of the W83627EHF.
18
08e7e278
JD		 19 This program is free software; you can redistribute it and/or modify
20 it under the terms of the GNU General Public License as published by
21 the Free Software Foundation; either version 2 of the License, or
22 (at your option) any later version.
23
24 This program is distributed in the hope that it will be useful,
25 but WITHOUT ANY WARRANTY; without even the implied warranty of
26 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 GNU General Public License for more details.
28
29 You should have received a copy of the GNU General Public License
30 along with this program; if not, write to the Free Software
31 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32
33
34 Supports the following chips:
35
657c93b1
DH		 36 Chip #vin #fan #pwm #temp chip IDs man ID
37 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
e7e1ca6e 38 0x8860 0xa1
657c93b1 39 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 40 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 41 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
c39aedaf 42 w83667hg-b 9 5 3 3 0xb350 0xc1 0x5ca3
08e7e278
JD		 43*/
44
abdc6fd1
JP		 45#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
46
08e7e278
JD		 47#include <linux/module.h>
48#include <linux/init.h>
49#include <linux/slab.h>
1ea6dd38
DH		 50#include <linux/jiffies.h>
51#include <linux/platform_device.h>
943b0830 52#include <linux/hwmon.h>
412fec82 53#include <linux/hwmon-sysfs.h>
fc18d6c0 54#include <linux/hwmon-vid.h>
943b0830 55#include <linux/err.h>
9a61bf63 56#include <linux/mutex.h>
b9acb64a 57#include <linux/acpi.h>
6055fae8 58#include <linux/io.h>
08e7e278
JD		 59#include "lm75.h"
60
c39aedaf 61enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b };
08e7e278 62
1ea6dd38 63/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 64static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 65 "w83627ehf",
66 "w83627dhg",
c1e48dce 67 "w83627dhg",
237c8d2f 68 "w83667hg",
c39aedaf 69 "w83667hg",
1ea6dd38
DH		 70};
71
67b671bc
JD		 72static unsigned short force_id;
73module_param(force_id, ushort, 0);
74MODULE_PARM_DESC(force_id, "Override the detected device ID");
75
1ea6dd38 76#define DRVNAME "w83627ehf"
08e7e278 77
657c93b1 78/*
1ea6dd38 79 * Super-I/O constants and functions
657c93b1 80 */
08e7e278
JD		 81
82#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 83#define W83667HG_LD_VID 0x0d
08e7e278
JD		 84
85#define SIO_REG_LDSEL 0x07 /* Logical device select */
86#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 87#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 88#define SIO_REG_ENABLE 0x30 /* Logical device enable */
89#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 90#define SIO_REG_VID_CTRL 0xF0 /* VID control */
91#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 92
657c93b1
DH		 93#define SIO_W83627EHF_ID 0x8850
94#define SIO_W83627EHG_ID 0x8860
95#define SIO_W83627DHG_ID 0xa020
c1e48dce 96#define SIO_W83627DHG_P_ID 0xb070
e7e1ca6e 97#define SIO_W83667HG_ID 0xa510
c39aedaf 98#define SIO_W83667HG_B_ID 0xb350
657c93b1 99#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 100
101static inline void
1ea6dd38 102superio_outb(int ioreg, int reg, int val)
08e7e278 103{
1ea6dd38
DH		 104 outb(reg, ioreg);
105 outb(val, ioreg + 1);
08e7e278
JD		 106}
107
108static inline int
1ea6dd38 109superio_inb(int ioreg, int reg)
08e7e278 110{
1ea6dd38
DH		 111 outb(reg, ioreg);
112 return inb(ioreg + 1);
08e7e278
JD		 113}
114
115static inline void
1ea6dd38 116superio_select(int ioreg, int ld)
08e7e278 117{
1ea6dd38
DH		 118 outb(SIO_REG_LDSEL, ioreg);
119 outb(ld, ioreg + 1);
08e7e278
JD		 120}
121
122static inline void
1ea6dd38 123superio_enter(int ioreg)
08e7e278 124{
1ea6dd38
DH		 125 outb(0x87, ioreg);
126 outb(0x87, ioreg);
08e7e278
JD		 127}
128
129static inline void
1ea6dd38 130superio_exit(int ioreg)
08e7e278 131{
022b75a3 132 outb(0xaa, ioreg);
1ea6dd38
DH		 133 outb(0x02, ioreg);
134 outb(0x02, ioreg + 1);
08e7e278
JD		 135}
136
137/*
138 * ISA constants
139 */
140
e7e1ca6e 141#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 142#define IOREGION_OFFSET 5
143#define IOREGION_LENGTH 2
1ea6dd38
DH		 144#define ADDR_REG_OFFSET 0
145#define DATA_REG_OFFSET 1
08e7e278
JD		 146
147#define W83627EHF_REG_BANK 0x4E
148#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 149
150/* Not currently used:
151 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
152 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
153 * REG_MAN_ID is at port 0x4f
154 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 155
156static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
157static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
158
cf0676fe
RM		 159/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
160#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
161 (0x554 + (((nr) - 7) * 2)))
162#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
163 (0x555 + (((nr) - 7) * 2)))
164#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
165 (0x550 + (nr) - 7))
166
bce26c58
GR		 167static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250 };
168static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253 };
169static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255 };
170static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252 };
08e7e278
JD		 171
172/* Fan clock dividers are spread over the following five registers */
173#define W83627EHF_REG_FANDIV1 0x47
174#define W83627EHF_REG_FANDIV2 0x4B
175#define W83627EHF_REG_VBAT 0x5D
176#define W83627EHF_REG_DIODE 0x59
177#define W83627EHF_REG_SMI_OVT 0x4C
178
a4589dbb
JD		 179#define W83627EHF_REG_ALARM1 0x459
180#define W83627EHF_REG_ALARM2 0x45A
181#define W83627EHF_REG_ALARM3 0x45B
182
08c79950 183/* SmartFan registers */
41e9a062
DB		 184#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
185#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
186
08c79950
RM		 187/* DC or PWM output fan configuration */
188static const u8 W83627EHF_REG_PWM_ENABLE[] = {
189 0x04, /* SYS FAN0 output mode and PWM mode */
190 0x04, /* CPU FAN0 output mode and PWM mode */
191 0x12, /* AUX FAN mode */
41e9a062 192 0x62, /* CPU FAN1 mode */
08c79950
RM		 193};
194
195static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
196static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
197
198/* FAN Duty Cycle, be used to control */
199static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
200static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
201static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
202
08c79950 203/* Advanced Fan control, some values are common for all fans */
41e9a062
DB		 204static const u8 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
205static const u8 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
206static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf
GR		 207
208static const u8 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
209 = { 0xff, 0x67, 0xff, 0x69 };
210static const u8 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
211 = { 0xff, 0x68, 0xff, 0x6a };
212
213static const u8 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
214static const u8 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[] = { 0x68, 0x6a, 0x6c };
08c79950 215
bce26c58
GR		 216static inline int is_word_sized(u16 reg)
217{
218 return (((reg & 0xff00) == 0x100
219 || (reg & 0xff00) == 0x200)
220 && ((reg & 0x00ff) == 0x50
221 || (reg & 0x00ff) == 0x53
222 || (reg & 0x00ff) == 0x55));
223}
224
08e7e278
JD		 225/*
226 * Conversions
227 */
228
08c79950
RM		 229/* 1 is PWM mode, output in ms */
230static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
231{
232 return mode ? 100 * reg : 400 * reg;
233}
234
235static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
236{
237 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
238 (msec + 200) / 400), 1, 255);
239}
240
08e7e278
JD		 241static inline unsigned int
242fan_from_reg(u8 reg, unsigned int div)
243{
244 if (reg == 0 || reg == 255)
245 return 0;
246 return 1350000U / (reg * div);
247}
248
249static inline unsigned int
250div_from_reg(u8 reg)
251{
252 return 1 << reg;
253}
254
255static inline int
bce26c58 256temp_from_reg(u16 reg, s16 regval)
08e7e278 257{
bce26c58
GR		 258 if (is_word_sized(reg))
259 return LM75_TEMP_FROM_REG(regval);
260 return regval * 1000;
08e7e278
JD		 261}
262
bce26c58
GR		 263static inline s16
264temp_to_reg(u16 reg, long temp)
08e7e278 265{
bce26c58
GR		 266 if (is_word_sized(reg))
267 return LM75_TEMP_TO_REG(temp);
268 return DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000), 1000);
08e7e278
JD		 269}
270
cf0676fe
RM		 271/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
272
273static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
274
275static inline long in_from_reg(u8 reg, u8 nr)
276{
277 return reg * scale_in[nr];
278}
279
280static inline u8 in_to_reg(u32 val, u8 nr)
281{
e7e1ca6e
GR		 282 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0,
283 255);
cf0676fe
RM		 284}
285
08e7e278
JD		 286/*
287 * Data structures and manipulation thereof
288 */
289
290struct w83627ehf_data {
1ea6dd38
DH		 291 int addr; /* IO base of hw monitor block */
292 const char *name;
293
1beeffe4 294 struct device *hwmon_dev;
9a61bf63 295 struct mutex lock;
08e7e278 296
da2e0255
GR		 297 const u8 *REG_FAN_START_OUTPUT;
298 const u8 *REG_FAN_STOP_OUTPUT;
299 const u8 *REG_FAN_MAX_OUTPUT;
300 const u8 *REG_FAN_STEP_OUTPUT;
301
9a61bf63 302 struct mutex update_lock;
08e7e278
JD		 303 char valid; /* !=0 if following fields are valid */
304 unsigned long last_updated; /* In jiffies */
305
306 /* Register values */
1ea6dd38 307 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 308 u8 in[10]; /* Register value */
309 u8 in_max[10]; /* Register value */
310 u8 in_min[10]; /* Register value */
08e7e278
JD		 311 u8 fan[5];
312 u8 fan_min[5];
313 u8 fan_div[5];
314 u8 has_fan; /* some fan inputs can be disabled */
da667365 315 u8 temp_type[3];
bce26c58
GR		 316 s16 temp[3];
317 s16 temp_max[3];
318 s16 temp_max_hyst[3];
a4589dbb 319 u32 alarms;
08c79950
RM		 320
321 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
322 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 323 2->thermal cruise mode (also called SmartFan I)
324 3->fan speed cruise mode
e7e1ca6e
GR		 325 4->variable thermal cruise (also called
326 SmartFan III) */
237c8d2f 327 u8 pwm_num; /* number of pwm */
08c79950
RM		 328 u8 pwm[4];
329 u8 target_temp[4];
330 u8 tolerance[4];
331
41e9a062
DB		 332 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
333 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
334 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
335 u8 fan_max_output[4]; /* maximum fan speed */
336 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 337
338 u8 vid;
339 u8 vrm;
a157d06d
GJ		 340
341 u8 temp3_disable;
342 u8 in6_skip;
08e7e278
JD		 343};
344
1ea6dd38
DH		 345struct w83627ehf_sio_data {
346 int sioreg;
347 enum kinds kind;
348};
349
0956895a 350/* Registers 0x50-0x5f are banked */
1ea6dd38 351static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 352{
0956895a 353 if ((reg & 0x00f0) == 0x50) {
1ea6dd38
DH		 354 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
355 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 356 }
357}
358
0956895a 359/* Not strictly necessary, but play it safe for now */
1ea6dd38 360static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 361{
362 if (reg & 0xff00) {
1ea6dd38
DH		 363 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
364 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 365 }
366}
367
1ea6dd38 368static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 369{
08e7e278
JD		 370 int res, word_sized = is_word_sized(reg);
371
9a61bf63 372 mutex_lock(&data->lock);
08e7e278 373
1ea6dd38
DH		 374 w83627ehf_set_bank(data, reg);
375 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
376 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 377 if (word_sized) {
378 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 379 data->addr + ADDR_REG_OFFSET);
380 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 381 }
1ea6dd38 382 w83627ehf_reset_bank(data, reg);
08e7e278 383
9a61bf63 384 mutex_unlock(&data->lock);
08e7e278
JD		 385
386 return res;
387}
388
e7e1ca6e
GR		 389static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
390 u16 value)
08e7e278 391{
08e7e278
JD		 392 int word_sized = is_word_sized(reg);
393
9a61bf63 394 mutex_lock(&data->lock);
08e7e278 395
1ea6dd38
DH		 396 w83627ehf_set_bank(data, reg);
397 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 398 if (word_sized) {
1ea6dd38 399 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 400 outb_p((reg & 0xff) + 1,
1ea6dd38 401 data->addr + ADDR_REG_OFFSET);
08e7e278 402 }
1ea6dd38
DH		 403 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
404 w83627ehf_reset_bank(data, reg);
08e7e278 405
9a61bf63 406 mutex_unlock(&data->lock);
08e7e278
JD		 407 return 0;
408}
409
410/* This function assumes that the caller holds data->update_lock */
1ea6dd38 411static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 412{
08e7e278
JD		 413 u8 reg;
414
415 switch (nr) {
416 case 0:
1ea6dd38 417 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 418 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 419 /* fan5 input control bit is write only, compute the value */
420 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 421 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
422 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 423 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 424 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 425 break;
426 case 1:
1ea6dd38 427 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 428 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 429 /* fan5 input control bit is write only, compute the value */
430 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 431 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
432 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 433 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 434 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 435 break;
436 case 2:
1ea6dd38 437 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 438 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 439 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
440 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 441 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 442 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 443 break;
444 case 3:
1ea6dd38 445 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 446 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 447 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
448 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 449 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 450 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 451 break;
452 case 4:
1ea6dd38 453 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 454 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 455 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 456 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 457 break;
458 }
459}
460
ea7be66c
MH		 461static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
462{
463 int i;
464
465 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
466 data->fan_div[0] = (i >> 4) & 0x03;
467 data->fan_div[1] = (i >> 6) & 0x03;
468 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
469 data->fan_div[2] = (i >> 6) & 0x03;
470 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
471 data->fan_div[0] |= (i >> 3) & 0x04;
472 data->fan_div[1] |= (i >> 4) & 0x04;
473 data->fan_div[2] |= (i >> 5) & 0x04;
474 if (data->has_fan & ((1 << 3) | (1 << 4))) {
475 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
476 data->fan_div[3] = i & 0x03;
477 data->fan_div[4] = ((i >> 2) & 0x03)
478 | ((i >> 5) & 0x04);
479 }
480 if (data->has_fan & (1 << 3)) {
481 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
482 data->fan_div[3] |= (i >> 5) & 0x04;
483 }
484}
485
08e7e278
JD		 486static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
487{
1ea6dd38 488 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 489 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 490 int i;
491
9a61bf63 492 mutex_lock(&data->update_lock);
08e7e278 493
6b3e4645 494 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 495 || !data->valid) {
496 /* Fan clock dividers */
ea7be66c 497 w83627ehf_update_fan_div(data);
08e7e278 498
cf0676fe 499 /* Measured voltages and limits */
1ea6dd38
DH		 500 for (i = 0; i < data->in_num; i++) {
501 data->in[i] = w83627ehf_read_value(data,
cf0676fe 502 W83627EHF_REG_IN(i));
1ea6dd38 503 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 504 W83627EHF_REG_IN_MIN(i));
1ea6dd38 505 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 506 W83627EHF_REG_IN_MAX(i));
507 }
508
08e7e278
JD		 509 /* Measured fan speeds and limits */
510 for (i = 0; i < 5; i++) {
511 if (!(data->has_fan & (1 << i)))
512 continue;
513
1ea6dd38 514 data->fan[i] = w83627ehf_read_value(data,
08e7e278 515 W83627EHF_REG_FAN[i]);
1ea6dd38 516 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 517 W83627EHF_REG_FAN_MIN[i]);
518
519 /* If we failed to measure the fan speed and clock
520 divider can be increased, let's try that for next
521 time */
522 if (data->fan[i] == 0xff
523 && data->fan_div[i] < 0x07) {
e7e1ca6e 524 dev_dbg(dev, "Increasing fan%d "
08e7e278 525 "clock divider from %u to %u\n",
33725ad3 526 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 527 div_from_reg(data->fan_div[i] + 1));
528 data->fan_div[i]++;
1ea6dd38 529 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 530 /* Preserve min limit if possible */
531 if (data->fan_min[i] >= 2
532 && data->fan_min[i] != 255)
1ea6dd38 533 w83627ehf_write_value(data,
08e7e278
JD		 534 W83627EHF_REG_FAN_MIN[i],
535 (data->fan_min[i] /= 2));
536 }
537 }
538
da2e0255
GR		 539 for (i = 0; i < data->pwm_num; i++) {
540 if (!(data->has_fan & (1 << i)))
541 continue;
542
77fa49d9 543 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
08c79950 544 if (i != 1) {
1ea6dd38 545 pwmcfg = w83627ehf_read_value(data,
08c79950 546 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 547 tolerance = w83627ehf_read_value(data,
08c79950
RM		 548 W83627EHF_REG_TOLERANCE[i]);
549 }
550 data->pwm_mode[i] =
551 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
552 ? 0 : 1;
553 data->pwm_enable[i] =
e7e1ca6e
GR		 554 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
555 & 3) + 1;
1ea6dd38 556 data->pwm[i] = w83627ehf_read_value(data,
08c79950 557 W83627EHF_REG_PWM[i]);
41e9a062 558 data->fan_start_output[i] = w83627ehf_read_value(data,
e7e1ca6e 559 W83627EHF_REG_FAN_START_OUTPUT[i]);
41e9a062 560 data->fan_stop_output[i] = w83627ehf_read_value(data,
e7e1ca6e 561 W83627EHF_REG_FAN_STOP_OUTPUT[i]);
1ea6dd38 562 data->fan_stop_time[i] = w83627ehf_read_value(data,
e7e1ca6e 563 W83627EHF_REG_FAN_STOP_TIME[i]);
da2e0255
GR		 564
565 if (data->REG_FAN_MAX_OUTPUT[i] != 0xff)
566 data->fan_max_output[i] =
567 w83627ehf_read_value(data,
568 data->REG_FAN_MAX_OUTPUT[i]);
569
570 if (data->REG_FAN_STEP_OUTPUT[i] != 0xff)
571 data->fan_step_output[i] =
572 w83627ehf_read_value(data,
573 data->REG_FAN_STEP_OUTPUT[i]);
574
08c79950 575 data->target_temp[i] =
1ea6dd38 576 w83627ehf_read_value(data,
08c79950
RM		 577 W83627EHF_REG_TARGET[i]) &
578 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
579 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
580 & 0x0f;
581 }
582
08e7e278 583 /* Measured temperatures and limits */
bce26c58 584 for (i = 0; i < 3; i++) {
1ea6dd38 585 data->temp[i] = w83627ehf_read_value(data,
08e7e278 586 W83627EHF_REG_TEMP[i]);
1ea6dd38 587 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 588 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 589 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 590 W83627EHF_REG_TEMP_HYST[i]);
591 }
592
1ea6dd38 593 data->alarms = w83627ehf_read_value(data,
a4589dbb 594 W83627EHF_REG_ALARM1) |
1ea6dd38 595 (w83627ehf_read_value(data,
a4589dbb 596 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 597 (w83627ehf_read_value(data,
a4589dbb
JD		 598 W83627EHF_REG_ALARM3) << 16);
599
08e7e278
JD		 600 data->last_updated = jiffies;
601 data->valid = 1;
602 }
603
9a61bf63 604 mutex_unlock(&data->update_lock);
08e7e278
JD		 605 return data;
606}
607
608/*
609 * Sysfs callback functions
610 */
cf0676fe
RM		 611#define show_in_reg(reg) \
612static ssize_t \
613show_##reg(struct device *dev, struct device_attribute *attr, \
614 char *buf) \
615{ \
616 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 617 struct sensor_device_attribute *sensor_attr = \
618 to_sensor_dev_attr(attr); \
cf0676fe
RM		 619 int nr = sensor_attr->index; \
620 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
621}
622show_in_reg(in)
623show_in_reg(in_min)
624show_in_reg(in_max)
625
626#define store_in_reg(REG, reg) \
627static ssize_t \
e7e1ca6e
GR		 628store_in_##reg(struct device *dev, struct device_attribute *attr, \
629 const char *buf, size_t count) \
cf0676fe 630{ \
1ea6dd38 631 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 632 struct sensor_device_attribute *sensor_attr = \
633 to_sensor_dev_attr(attr); \
cf0676fe 634 int nr = sensor_attr->index; \
bce26c58
GR		 635 unsigned long val; \
636 int err; \
637 err = strict_strtoul(buf, 10, &val); \
638 if (err < 0) \
639 return err; \
cf0676fe
RM		 640 mutex_lock(&data->update_lock); \
641 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 642 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 643 data->in_##reg[nr]); \
644 mutex_unlock(&data->update_lock); \
645 return count; \
646}
647
648store_in_reg(MIN, min)
649store_in_reg(MAX, max)
650
e7e1ca6e
GR		 651static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
652 char *buf)
a4589dbb
JD		 653{
654 struct w83627ehf_data *data = w83627ehf_update_device(dev);
655 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
656 int nr = sensor_attr->index;
657 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
658}
659
cf0676fe
RM		 660static struct sensor_device_attribute sda_in_input[] = {
661 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
662 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
663 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
664 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
665 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
666 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
667 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
668 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
669 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
670 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
671};
672
a4589dbb
JD		 673static struct sensor_device_attribute sda_in_alarm[] = {
674 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
675 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
676 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
677 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
678 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
679 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
680 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
681 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
682 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
683 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
684};
685
cf0676fe 686static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 687 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
688 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
689 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
690 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
691 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
692 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
693 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
694 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
695 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
696 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 697};
698
699static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 700 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
701 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
702 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
703 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
704 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
705 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
706 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
707 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
708 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
709 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 710};
711
08e7e278
JD		 712#define show_fan_reg(reg) \
713static ssize_t \
412fec82
YM		 714show_##reg(struct device *dev, struct device_attribute *attr, \
715 char *buf) \
08e7e278
JD		 716{ \
717 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 718 struct sensor_device_attribute *sensor_attr = \
719 to_sensor_dev_attr(attr); \
412fec82 720 int nr = sensor_attr->index; \
08e7e278
JD		 721 return sprintf(buf, "%d\n", \
722 fan_from_reg(data->reg[nr], \
723 div_from_reg(data->fan_div[nr]))); \
724}
725show_fan_reg(fan);
726show_fan_reg(fan_min);
727
728static ssize_t
412fec82
YM		 729show_fan_div(struct device *dev, struct device_attribute *attr,
730 char *buf)
08e7e278
JD		 731{
732 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 733 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
734 int nr = sensor_attr->index;
735 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 736}
737
738static ssize_t
412fec82
YM		 739store_fan_min(struct device *dev, struct device_attribute *attr,
740 const char *buf, size_t count)
08e7e278 741{
1ea6dd38 742 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 743 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
744 int nr = sensor_attr->index;
bce26c58
GR		 745 unsigned long val;
746 int err;
08e7e278
JD		 747 unsigned int reg;
748 u8 new_div;
749
bce26c58
GR		 750 err = strict_strtoul(buf, 10, &val);
751 if (err < 0)
752 return err;
753
9a61bf63 754 mutex_lock(&data->update_lock);
08e7e278
JD		 755 if (!val) {
756 /* No min limit, alarm disabled */
757 data->fan_min[nr] = 255;
758 new_div = data->fan_div[nr]; /* No change */
759 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
760 } else if ((reg = 1350000U / val) >= 128 * 255) {
761 /* Speed below this value cannot possibly be represented,
762 even with the highest divider (128) */
763 data->fan_min[nr] = 254;
764 new_div = 7; /* 128 == (1 << 7) */
bce26c58 765 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
08e7e278
JD		 766 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
767 } else if (!reg) {
768 /* Speed above this value cannot possibly be represented,
769 even with the lowest divider (1) */
770 data->fan_min[nr] = 1;
771 new_div = 0; /* 1 == (1 << 0) */
bce26c58 772 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
b9110b1c 773 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 774 } else {
775 /* Automatically pick the best divider, i.e. the one such
776 that the min limit will correspond to a register value
777 in the 96..192 range */
778 new_div = 0;
779 while (reg > 192 && new_div < 7) {
780 reg >>= 1;
781 new_div++;
782 }
783 data->fan_min[nr] = reg;
784 }
785
786 /* Write both the fan clock divider (if it changed) and the new
787 fan min (unconditionally) */
788 if (new_div != data->fan_div[nr]) {
158ce075
JD		 789 /* Preserve the fan speed reading */
790 if (data->fan[nr] != 0xff) {
791 if (new_div > data->fan_div[nr])
792 data->fan[nr] >>= new_div - data->fan_div[nr];
793 else if (data->fan[nr] & 0x80)
794 data->fan[nr] = 0xff;
795 else
796 data->fan[nr] <<= data->fan_div[nr] - new_div;
797 }
08e7e278
JD		 798
799 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
800 nr + 1, div_from_reg(data->fan_div[nr]),
801 div_from_reg(new_div));
802 data->fan_div[nr] = new_div;
1ea6dd38 803 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 804 /* Give the chip time to sample a new speed value */
805 data->last_updated = jiffies;
08e7e278 806 }
1ea6dd38 807 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 808 data->fan_min[nr]);
9a61bf63 809 mutex_unlock(&data->update_lock);
08e7e278
JD		 810
811 return count;
812}
813
412fec82
YM		 814static struct sensor_device_attribute sda_fan_input[] = {
815 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
816 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
817 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
818 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
819 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
820};
08e7e278 821
a4589dbb
JD		 822static struct sensor_device_attribute sda_fan_alarm[] = {
823 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
824 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
825 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
826 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
827 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
828};
829
412fec82
YM		 830static struct sensor_device_attribute sda_fan_min[] = {
831 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
832 store_fan_min, 0),
833 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
834 store_fan_min, 1),
835 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
836 store_fan_min, 2),
837 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
838 store_fan_min, 3),
839 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
840 store_fan_min, 4),
841};
08e7e278 842
412fec82
YM		 843static struct sensor_device_attribute sda_fan_div[] = {
844 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
845 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
846 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
847 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
848 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
849};
850
bce26c58 851#define show_temp_reg(REG, reg) \
08e7e278 852static ssize_t \
412fec82
YM		 853show_##reg(struct device *dev, struct device_attribute *attr, \
854 char *buf) \
08e7e278
JD		 855{ \
856 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 857 struct sensor_device_attribute *sensor_attr = \
858 to_sensor_dev_attr(attr); \
412fec82 859 int nr = sensor_attr->index; \
08e7e278 860 return sprintf(buf, "%d\n", \
bce26c58 861 temp_from_reg(W83627EHF_REG_##REG[nr], data->reg[nr])); \
08e7e278 862}
bce26c58
GR		 863show_temp_reg(TEMP, temp);
864show_temp_reg(TEMP_OVER, temp_max);
865show_temp_reg(TEMP_HYST, temp_max_hyst);
08e7e278
JD		 866
867#define store_temp_reg(REG, reg) \
868static ssize_t \
412fec82
YM		 869store_##reg(struct device *dev, struct device_attribute *attr, \
870 const char *buf, size_t count) \
08e7e278 871{ \
1ea6dd38 872 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 873 struct sensor_device_attribute *sensor_attr = \
874 to_sensor_dev_attr(attr); \
412fec82 875 int nr = sensor_attr->index; \
bce26c58
GR		 876 int err; \
877 long val; \
878 err = strict_strtol(buf, 10, &val); \
879 if (err < 0) \
880 return err; \
9a61bf63 881 mutex_lock(&data->update_lock); \
bce26c58 882 data->reg[nr] = temp_to_reg(W83627EHF_REG_TEMP_##REG[nr], val); \
1ea6dd38 883 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 884 data->reg[nr]); \
9a61bf63 885 mutex_unlock(&data->update_lock); \
08e7e278
JD		 886 return count; \
887}
888store_temp_reg(OVER, temp_max);
889store_temp_reg(HYST, temp_max_hyst);
890
da667365
JD		 891static ssize_t
892show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
893{
894 struct w83627ehf_data *data = w83627ehf_update_device(dev);
895 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
896 int nr = sensor_attr->index;
897 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
898}
899
a157d06d 900static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 901 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
902 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
903 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
a157d06d
GJ		 904};
905
906static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 907 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 908 store_temp_max, 0),
bce26c58 909 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 910 store_temp_max, 1),
bce26c58
GR		 911 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
912 store_temp_max, 2),
a157d06d
GJ		 913};
914
915static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 916 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 917 store_temp_max_hyst, 0),
bce26c58 918 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 919 store_temp_max_hyst, 1),
bce26c58
GR		 920 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
921 store_temp_max_hyst, 2),
a157d06d
GJ		 922};
923
924static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 925 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
926 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
927 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 928};
929
930static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 931 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
932 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
933 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 934};
08e7e278 935
08c79950 936#define show_pwm_reg(reg) \
e7e1ca6e
GR		 937static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
938 char *buf) \
08c79950
RM		 939{ \
940 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 941 struct sensor_device_attribute *sensor_attr = \
942 to_sensor_dev_attr(attr); \
08c79950
RM		 943 int nr = sensor_attr->index; \
944 return sprintf(buf, "%d\n", data->reg[nr]); \
945}
946
947show_pwm_reg(pwm_mode)
948show_pwm_reg(pwm_enable)
949show_pwm_reg(pwm)
950
951static ssize_t
952store_pwm_mode(struct device *dev, struct device_attribute *attr,
953 const char *buf, size_t count)
954{
1ea6dd38 955 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 956 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
957 int nr = sensor_attr->index;
bce26c58
GR		 958 unsigned long val;
959 int err;
08c79950
RM		 960 u16 reg;
961
bce26c58
GR		 962 err = strict_strtoul(buf, 10, &val);
963 if (err < 0)
964 return err;
965
08c79950
RM		 966 if (val > 1)
967 return -EINVAL;
968 mutex_lock(&data->update_lock);
1ea6dd38 969 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 970 data->pwm_mode[nr] = val;
971 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
972 if (!val)
973 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 974 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 975 mutex_unlock(&data->update_lock);
976 return count;
977}
978
979static ssize_t
980store_pwm(struct device *dev, struct device_attribute *attr,
981 const char *buf, size_t count)
982{
1ea6dd38 983 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 984 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
985 int nr = sensor_attr->index;
bce26c58
GR		 986 unsigned long val;
987 int err;
988
989 err = strict_strtoul(buf, 10, &val);
990 if (err < 0)
991 return err;
992
993 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 994
995 mutex_lock(&data->update_lock);
996 data->pwm[nr] = val;
1ea6dd38 997 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 998 mutex_unlock(&data->update_lock);
999 return count;
1000}
1001
1002static ssize_t
1003store_pwm_enable(struct device *dev, struct device_attribute *attr,
1004 const char *buf, size_t count)
1005{
1ea6dd38 1006 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1007 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1008 int nr = sensor_attr->index;
bce26c58
GR		 1009 unsigned long val;
1010 int err;
08c79950
RM		 1011 u16 reg;
1012
bce26c58
GR		 1013 err = strict_strtoul(buf, 10, &val);
1014 if (err < 0)
1015 return err;
1016
41e9a062 1017 if (!val || (val > 4))
08c79950
RM		 1018 return -EINVAL;
1019 mutex_lock(&data->update_lock);
1ea6dd38 1020 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1021 data->pwm_enable[nr] = val;
1022 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1023 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 1024 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1025 mutex_unlock(&data->update_lock);
1026 return count;
1027}
1028
1029
1030#define show_tol_temp(reg) \
1031static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1032 char *buf) \
1033{ \
1034 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1035 struct sensor_device_attribute *sensor_attr = \
1036 to_sensor_dev_attr(attr); \
08c79950 1037 int nr = sensor_attr->index; \
bce26c58 1038 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1039}
1040
1041show_tol_temp(tolerance)
1042show_tol_temp(target_temp)
1043
1044static ssize_t
1045store_target_temp(struct device *dev, struct device_attribute *attr,
1046 const char *buf, size_t count)
1047{
1ea6dd38 1048 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1049 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1050 int nr = sensor_attr->index;
bce26c58
GR		 1051 long val;
1052 int err;
1053
1054 err = strict_strtol(buf, 10, &val);
1055 if (err < 0)
1056 return err;
1057
1058 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1059
1060 mutex_lock(&data->update_lock);
1061 data->target_temp[nr] = val;
1ea6dd38 1062 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 1063 mutex_unlock(&data->update_lock);
1064 return count;
1065}
1066
1067static ssize_t
1068store_tolerance(struct device *dev, struct device_attribute *attr,
1069 const char *buf, size_t count)
1070{
1ea6dd38 1071 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1072 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1073 int nr = sensor_attr->index;
1074 u16 reg;
bce26c58
GR		 1075 long val;
1076 int err;
1077
1078 err = strict_strtol(buf, 10, &val);
1079 if (err < 0)
1080 return err;
1081
08c79950 1082 /* Limit the temp to 0C - 15C */
bce26c58 1083 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1084
1085 mutex_lock(&data->update_lock);
1ea6dd38 1086 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 1087 data->tolerance[nr] = val;
1088 if (nr == 1)
1089 reg = (reg & 0x0f) | (val << 4);
1090 else
1091 reg = (reg & 0xf0) | val;
1ea6dd38 1092 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 1093 mutex_unlock(&data->update_lock);
1094 return count;
1095}
1096
1097static struct sensor_device_attribute sda_pwm[] = {
1098 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1099 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1100 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1101 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1102};
1103
1104static struct sensor_device_attribute sda_pwm_mode[] = {
1105 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1106 store_pwm_mode, 0),
1107 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1108 store_pwm_mode, 1),
1109 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1110 store_pwm_mode, 2),
1111 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1112 store_pwm_mode, 3),
1113};
1114
1115static struct sensor_device_attribute sda_pwm_enable[] = {
1116 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1117 store_pwm_enable, 0),
1118 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1119 store_pwm_enable, 1),
1120 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1121 store_pwm_enable, 2),
1122 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1123 store_pwm_enable, 3),
1124};
1125
1126static struct sensor_device_attribute sda_target_temp[] = {
1127 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1128 store_target_temp, 0),
1129 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1130 store_target_temp, 1),
1131 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1132 store_target_temp, 2),
1133 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1134 store_target_temp, 3),
1135};
1136
1137static struct sensor_device_attribute sda_tolerance[] = {
1138 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1139 store_tolerance, 0),
1140 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1141 store_tolerance, 1),
1142 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1143 store_tolerance, 2),
1144 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1145 store_tolerance, 3),
1146};
1147
08c79950
RM		 1148/* Smart Fan registers */
1149
1150#define fan_functions(reg, REG) \
1151static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1152 char *buf) \
1153{ \
1154 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1155 struct sensor_device_attribute *sensor_attr = \
1156 to_sensor_dev_attr(attr); \
08c79950
RM		 1157 int nr = sensor_attr->index; \
1158 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1159} \
08c79950
RM		 1160static ssize_t \
1161store_##reg(struct device *dev, struct device_attribute *attr, \
1162 const char *buf, size_t count) \
e7e1ca6e 1163{ \
1ea6dd38 1164 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1165 struct sensor_device_attribute *sensor_attr = \
1166 to_sensor_dev_attr(attr); \
08c79950 1167 int nr = sensor_attr->index; \
bce26c58
GR		 1168 unsigned long val; \
1169 int err; \
1170 err = strict_strtoul(buf, 10, &val); \
1171 if (err < 0) \
1172 return err; \
1173 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1174 mutex_lock(&data->update_lock); \
1175 data->reg[nr] = val; \
da2e0255 1176 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1177 mutex_unlock(&data->update_lock); \
1178 return count; \
1179}
1180
41e9a062
DB		 1181fan_functions(fan_start_output, FAN_START_OUTPUT)
1182fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1183fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1184fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1185
1186#define fan_time_functions(reg, REG) \
1187static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1188 char *buf) \
1189{ \
1190 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1191 struct sensor_device_attribute *sensor_attr = \
1192 to_sensor_dev_attr(attr); \
08c79950
RM		 1193 int nr = sensor_attr->index; \
1194 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1195 step_time_from_reg(data->reg[nr], \
1196 data->pwm_mode[nr])); \
08c79950
RM		 1197} \
1198\
1199static ssize_t \
1200store_##reg(struct device *dev, struct device_attribute *attr, \
1201 const char *buf, size_t count) \
1202{ \
1ea6dd38 1203 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1204 struct sensor_device_attribute *sensor_attr = \
1205 to_sensor_dev_attr(attr); \
08c79950 1206 int nr = sensor_attr->index; \
bce26c58
GR		 1207 unsigned long val; \
1208 int err; \
1209 err = strict_strtoul(buf, 10, &val); \
1210 if (err < 0) \
1211 return err; \
1212 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1213 mutex_lock(&data->update_lock); \
1214 data->reg[nr] = val; \
1ea6dd38 1215 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1216 mutex_unlock(&data->update_lock); \
1217 return count; \
1218} \
1219
1220fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1221
1ea6dd38
DH		 1222static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1223 char *buf)
1224{
1225 struct w83627ehf_data *data = dev_get_drvdata(dev);
1226
1227 return sprintf(buf, "%s\n", data->name);
1228}
1229static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1230
1231static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1232 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1233 store_fan_stop_time, 3),
41e9a062
DB		 1234 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1235 store_fan_start_output, 3),
1236 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1237 store_fan_stop_output, 3),
1238 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1239 store_fan_max_output, 3),
1240 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1241 store_fan_step_output, 3),
08c79950
RM		 1242};
1243
1244static struct sensor_device_attribute sda_sf3_arrays[] = {
1245 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1246 store_fan_stop_time, 0),
1247 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1248 store_fan_stop_time, 1),
1249 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1250 store_fan_stop_time, 2),
41e9a062
DB		 1251 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1252 store_fan_start_output, 0),
1253 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1254 store_fan_start_output, 1),
1255 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1256 store_fan_start_output, 2),
1257 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1258 store_fan_stop_output, 0),
1259 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1260 store_fan_stop_output, 1),
1261 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1262 store_fan_stop_output, 2),
da2e0255 1263};
41e9a062 1264
da2e0255
GR		 1265
1266/*
1267 * pwm1 and pwm3 don't support max and step settings on all chips.
1268 * Need to check support while generating/removing attribute files.
1269 */
1270static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1271 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1272 store_fan_max_output, 0),
1273 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1274 store_fan_step_output, 0),
41e9a062
DB		 1275 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1276 store_fan_max_output, 1),
1277 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1278 store_fan_step_output, 1),
da2e0255
GR		 1279 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1280 store_fan_max_output, 2),
1281 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1282 store_fan_step_output, 2),
08c79950
RM		 1283};
1284
fc18d6c0
JD		 1285static ssize_t
1286show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1287{
1288 struct w83627ehf_data *data = dev_get_drvdata(dev);
1289 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1290}
1291static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1292
08e7e278 1293/*
1ea6dd38 1294 * Driver and device management
08e7e278
JD		 1295 */
1296
c18beb5b
DH		 1297static void w83627ehf_device_remove_files(struct device *dev)
1298{
1299 /* some entries in the following arrays may not have been used in
1300 * device_create_file(), but device_remove_file() will ignore them */
1301 int i;
1ea6dd38 1302 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1303
1304 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1305 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1306 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1307 struct sensor_device_attribute *attr =
1308 &sda_sf3_max_step_arrays[i];
1309 if (data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
1310 device_remove_file(dev, &attr->dev_attr);
1311 }
c18beb5b
DH		 1312 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1313 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1314 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1315 if ((i == 6) && data->in6_skip)
1316 continue;
c18beb5b
DH		 1317 device_remove_file(dev, &sda_in_input[i].dev_attr);
1318 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1319 device_remove_file(dev, &sda_in_min[i].dev_attr);
1320 device_remove_file(dev, &sda_in_max[i].dev_attr);
1321 }
1322 for (i = 0; i < 5; i++) {
1323 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1324 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1325 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1326 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1327 }
237c8d2f 1328 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1329 device_remove_file(dev, &sda_pwm[i].dev_attr);
1330 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1331 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1332 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1333 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1334 }
a157d06d
GJ		 1335 for (i = 0; i < 3; i++) {
1336 if ((i == 2) && data->temp3_disable)
1337 continue;
1338 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1339 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1340 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1341 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1342 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1343 }
c18beb5b 1344
1ea6dd38 1345 device_remove_file(dev, &dev_attr_name);
cbe311f2 1346 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1347}
08e7e278 1348
1ea6dd38
DH		 1349/* Get the monitoring functions started */
1350static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1351{
1352 int i;
da667365 1353 u8 tmp, diode;
08e7e278
JD		 1354
1355 /* Start monitoring is needed */
1ea6dd38 1356 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1357 if (!(tmp & 0x01))
1ea6dd38 1358 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1359 tmp | 0x01);
1360
1361 /* Enable temp2 and temp3 if needed */
bce26c58 1362 for (i = 1; i < 3; i++) {
1ea6dd38 1363 tmp = w83627ehf_read_value(data,
08e7e278 1364 W83627EHF_REG_TEMP_CONFIG[i]);
bce26c58 1365 if ((i == 2) && data->temp3_disable)
a157d06d 1366 continue;
08e7e278 1367 if (tmp & 0x01)
1ea6dd38 1368 w83627ehf_write_value(data,
08e7e278
JD		 1369 W83627EHF_REG_TEMP_CONFIG[i],
1370 tmp & 0xfe);
1371 }
d3130f0e
JD		 1372
1373 /* Enable VBAT monitoring if needed */
1374 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1375 if (!(tmp & 0x01))
1376 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1377
1378 /* Get thermal sensor types */
1379 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1380 for (i = 0; i < 3; i++) {
1381 if ((tmp & (0x02 << i)))
1382 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1383 else
1384 data->temp_type[i] = 4; /* thermistor */
1385 }
08e7e278
JD		 1386}
1387
1ea6dd38 1388static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1389{
1ea6dd38
DH		 1390 struct device *dev = &pdev->dev;
1391 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1392 struct w83627ehf_data *data;
1ea6dd38 1393 struct resource *res;
fc18d6c0 1394 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1395 int i, err = 0;
1396
1ea6dd38
DH		 1397 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1398 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1399 err = -EBUSY;
1ea6dd38
DH		 1400 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1401 (unsigned long)res->start,
1402 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1403 goto exit;
1404 }
1405
e7e1ca6e
GR		 1406 data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL);
1407 if (!data) {
08e7e278
JD		 1408 err = -ENOMEM;
1409 goto exit_release;
1410 }
08e7e278 1411
1ea6dd38 1412 data->addr = res->start;
9a61bf63 1413 mutex_init(&data->lock);
9a61bf63 1414 mutex_init(&data->update_lock);
1ea6dd38
DH		 1415 data->name = w83627ehf_device_names[sio_data->kind];
1416 platform_set_drvdata(pdev, data);
08e7e278 1417
237c8d2f
GJ		 1418 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1419 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
1420 /* 667HG has 3 pwms */
c39aedaf
GR		 1421 data->pwm_num = (sio_data->kind == w83667hg
1422 || sio_data->kind == w83667hg_b) ? 3 : 4;
08e7e278 1423
a157d06d 1424 /* Check temp3 configuration bit for 667HG */
c39aedaf 1425 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
a157d06d 1426 data->temp3_disable = w83627ehf_read_value(data,
bce26c58 1427 W83627EHF_REG_TEMP_CONFIG[2]) & 0x01;
a157d06d
GJ		 1428 data->in6_skip = !data->temp3_disable;
1429 }
1430
da2e0255
GR		 1431 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
1432 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
c39aedaf
GR		 1433 if (sio_data->kind == w83667hg_b) {
1434 data->REG_FAN_MAX_OUTPUT =
1435 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
1436 data->REG_FAN_STEP_OUTPUT =
1437 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
1438 } else {
1439 data->REG_FAN_MAX_OUTPUT =
1440 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
1441 data->REG_FAN_STEP_OUTPUT =
1442 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
1443 }
da2e0255 1444
08e7e278 1445 /* Initialize the chip */
1ea6dd38 1446 w83627ehf_init_device(data);
08e7e278 1447
fc18d6c0
JD		 1448 data->vrm = vid_which_vrm();
1449 superio_enter(sio_data->sioreg);
fc18d6c0 1450 /* Read VID value */
c39aedaf 1451 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
237c8d2f
GJ		 1452 /* W83667HG has different pins for VID input and output, so
1453 we can get the VID input values directly at logical device D
1454 0xe3. */
1455 superio_select(sio_data->sioreg, W83667HG_LD_VID);
1456 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 1457 err = device_create_file(dev, &dev_attr_cpu0_vid);
1458 if (err)
1459 goto exit_release;
58e6e781 1460 } else {
237c8d2f
GJ		 1461 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1462 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
1463 /* Set VID input sensibility if needed. In theory the
1464 BIOS should have set it, but in practice it's not
1465 always the case. We only do it for the W83627EHF/EHG
1466 because the W83627DHG is more complex in this
1467 respect. */
1468 if (sio_data->kind == w83627ehf) {
1469 en_vrm10 = superio_inb(sio_data->sioreg,
1470 SIO_REG_EN_VRM10);
1471 if ((en_vrm10 & 0x08) && data->vrm == 90) {
1472 dev_warn(dev, "Setting VID input "
1473 "voltage to TTL\n");
1474 superio_outb(sio_data->sioreg,
1475 SIO_REG_EN_VRM10,
1476 en_vrm10 & ~0x08);
1477 } else if (!(en_vrm10 & 0x08)
1478 && data->vrm == 100) {
1479 dev_warn(dev, "Setting VID input "
1480 "voltage to VRM10\n");
1481 superio_outb(sio_data->sioreg,
1482 SIO_REG_EN_VRM10,
1483 en_vrm10 | 0x08);
1484 }
1485 }
1486
1487 data->vid = superio_inb(sio_data->sioreg,
1488 SIO_REG_VID_DATA);
1489 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1490 data->vid &= 0x3f;
1491
1492 err = device_create_file(dev, &dev_attr_cpu0_vid);
1493 if (err)
1494 goto exit_release;
1495 } else {
1496 dev_info(dev, "VID pins in output mode, CPU VID not "
1497 "available\n");
1498 }
fc18d6c0
JD		 1499 }
1500
08c79950 1501 /* fan4 and fan5 share some pins with the GPIO and serial flash */
c39aedaf 1502 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
237c8d2f
GJ		 1503 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1504 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1505 } else {
1506 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1507 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1508 }
1ea6dd38 1509 superio_exit(sio_data->sioreg);
08c79950 1510
08e7e278 1511 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1512 as fan on/off switches, but fan5 control is write only :/
1513 We assume that if the serial interface is disabled, designers
1514 connected fan5 as input unless they are emitting log 1, which
1515 is not the default. */
08c79950 1516
08e7e278 1517 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1518 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1704b26e 1519 if ((i & (1 << 2)) && fan4pin)
08e7e278 1520 data->has_fan |= (1 << 3);
1704b26e 1521 if (!(i & (1 << 1)) && fan5pin)
08e7e278
JD		 1522 data->has_fan |= (1 << 4);
1523
ea7be66c
MH		 1524 /* Read fan clock dividers immediately */
1525 w83627ehf_update_fan_div(data);
1526
08e7e278 1527 /* Register sysfs hooks */
e7e1ca6e
GR		 1528 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
1529 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
1530 if (err)
c18beb5b 1531 goto exit_remove;
e7e1ca6e 1532 }
08c79950 1533
da2e0255
GR		 1534 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1535 struct sensor_device_attribute *attr =
1536 &sda_sf3_max_step_arrays[i];
1537 if (data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
1538 err = device_create_file(dev, &attr->dev_attr);
1539 if (err)
1540 goto exit_remove;
1541 }
1542 }
08c79950 1543 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 1544 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 1545 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 1546 err = device_create_file(dev,
1547 &sda_sf3_arrays_fan4[i].dev_attr);
1548 if (err)
c18beb5b
DH		 1549 goto exit_remove;
1550 }
08c79950 1551
a157d06d
GJ		 1552 for (i = 0; i < data->in_num; i++) {
1553 if ((i == 6) && data->in6_skip)
1554 continue;
c18beb5b
DH		 1555 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1556 || (err = device_create_file(dev,
1557 &sda_in_alarm[i].dev_attr))
1558 || (err = device_create_file(dev,
1559 &sda_in_min[i].dev_attr))
1560 || (err = device_create_file(dev,
1561 &sda_in_max[i].dev_attr)))
1562 goto exit_remove;
a157d06d 1563 }
cf0676fe 1564
412fec82 1565 for (i = 0; i < 5; i++) {
08c79950 1566 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1567 if ((err = device_create_file(dev,
1568 &sda_fan_input[i].dev_attr))
1569 || (err = device_create_file(dev,
1570 &sda_fan_alarm[i].dev_attr))
1571 || (err = device_create_file(dev,
1572 &sda_fan_div[i].dev_attr))
1573 || (err = device_create_file(dev,
1574 &sda_fan_min[i].dev_attr)))
1575 goto exit_remove;
237c8d2f 1576 if (i < data->pwm_num &&
c18beb5b
DH		 1577 ((err = device_create_file(dev,
1578 &sda_pwm[i].dev_attr))
1579 || (err = device_create_file(dev,
1580 &sda_pwm_mode[i].dev_attr))
1581 || (err = device_create_file(dev,
1582 &sda_pwm_enable[i].dev_attr))
1583 || (err = device_create_file(dev,
1584 &sda_target_temp[i].dev_attr))
1585 || (err = device_create_file(dev,
1586 &sda_tolerance[i].dev_attr))))
1587 goto exit_remove;
08c79950 1588 }
08e7e278 1589 }
08c79950 1590
a157d06d
GJ		 1591 for (i = 0; i < 3; i++) {
1592 if ((i == 2) && data->temp3_disable)
1593 continue;
1594 if ((err = device_create_file(dev,
1595 &sda_temp_input[i].dev_attr))
1596 || (err = device_create_file(dev,
1597 &sda_temp_max[i].dev_attr))
1598 || (err = device_create_file(dev,
1599 &sda_temp_max_hyst[i].dev_attr))
1600 || (err = device_create_file(dev,
1601 &sda_temp_alarm[i].dev_attr))
1602 || (err = device_create_file(dev,
1603 &sda_temp_type[i].dev_attr)))
c18beb5b 1604 goto exit_remove;
a157d06d 1605 }
c18beb5b 1606
1ea6dd38
DH		 1607 err = device_create_file(dev, &dev_attr_name);
1608 if (err)
1609 goto exit_remove;
1610
1beeffe4
TJ		 1611 data->hwmon_dev = hwmon_device_register(dev);
1612 if (IS_ERR(data->hwmon_dev)) {
1613 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 1614 goto exit_remove;
1615 }
08e7e278
JD		 1616
1617 return 0;
1618
c18beb5b
DH		 1619exit_remove:
1620 w83627ehf_device_remove_files(dev);
08e7e278 1621 kfree(data);
1ea6dd38 1622 platform_set_drvdata(pdev, NULL);
08e7e278 1623exit_release:
1ea6dd38 1624 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1625exit:
1626 return err;
1627}
1628
1ea6dd38 1629static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1630{
1ea6dd38 1631 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1632
1beeffe4 1633 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 1634 w83627ehf_device_remove_files(&pdev->dev);
1635 release_region(data->addr, IOREGION_LENGTH);
1636 platform_set_drvdata(pdev, NULL);
943b0830 1637 kfree(data);
08e7e278
JD		 1638
1639 return 0;
1640}
1641
1ea6dd38 1642static struct platform_driver w83627ehf_driver = {
cdaf7934 1643 .driver = {
87218842 1644 .owner = THIS_MODULE,
1ea6dd38 1645 .name = DRVNAME,
cdaf7934 1646 },
1ea6dd38
DH		 1647 .probe = w83627ehf_probe,
1648 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1649};
1650
1ea6dd38
DH		 1651/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1652static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1653 struct w83627ehf_sio_data *sio_data)
08e7e278 1654{
1ea6dd38
DH		 1655 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1656 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1657 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 1658 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 1659 static const char __initdata sio_name_W83667HG[] = "W83667HG";
c39aedaf 1660 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
1ea6dd38 1661
08e7e278 1662 u16 val;
1ea6dd38 1663 const char *sio_name;
08e7e278 1664
1ea6dd38 1665 superio_enter(sioaddr);
08e7e278 1666
67b671bc
JD		 1667 if (force_id)
1668 val = force_id;
1669 else
1670 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1671 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1672 switch (val & SIO_ID_MASK) {
657c93b1 1673 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1674 sio_data->kind = w83627ehf;
1675 sio_name = sio_name_W83627EHF;
1676 break;
657c93b1 1677 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1678 sio_data->kind = w83627ehf;
1679 sio_name = sio_name_W83627EHG;
1680 break;
1681 case SIO_W83627DHG_ID:
1682 sio_data->kind = w83627dhg;
1683 sio_name = sio_name_W83627DHG;
657c93b1 1684 break;
c1e48dce
JD		 1685 case SIO_W83627DHG_P_ID:
1686 sio_data->kind = w83627dhg_p;
1687 sio_name = sio_name_W83627DHG_P;
1688 break;
237c8d2f
GJ		 1689 case SIO_W83667HG_ID:
1690 sio_data->kind = w83667hg;
1691 sio_name = sio_name_W83667HG;
1692 break;
c39aedaf
GR		 1693 case SIO_W83667HG_B_ID:
1694 sio_data->kind = w83667hg_b;
1695 sio_name = sio_name_W83667HG_B;
1696 break;
657c93b1 1697 default:
9f66036b 1698 if (val != 0xffff)
abdc6fd1 1699 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 1700 superio_exit(sioaddr);
08e7e278
JD		 1701 return -ENODEV;
1702 }
1703
1ea6dd38
DH		 1704 /* We have a known chip, find the HWM I/O address */
1705 superio_select(sioaddr, W83627EHF_LD_HWM);
1706 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1707 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1708 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1709 if (*addr == 0) {
abdc6fd1 1710 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 1711 superio_exit(sioaddr);
08e7e278
JD		 1712 return -ENODEV;
1713 }
1714
1715 /* Activate logical device if needed */
1ea6dd38 1716 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 1717 if (!(val & 0x01)) {
e7e1ca6e
GR		 1718 pr_warn("Forcibly enabling Super-I/O. "
1719 "Sensor is probably unusable.\n");
1ea6dd38 1720 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1721 }
1ea6dd38
DH		 1722
1723 superio_exit(sioaddr);
abdc6fd1 1724 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 1725 sio_data->sioreg = sioaddr;
08e7e278 1726
08e7e278
JD		 1727 return 0;
1728}
1729
1ea6dd38
DH		 1730/* when Super-I/O functions move to a separate file, the Super-I/O
1731 * bus will manage the lifetime of the device and this module will only keep
1732 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1733 * must keep track of the device */
1734static struct platform_device *pdev;
1735
08e7e278
JD		 1736static int __init sensors_w83627ehf_init(void)
1737{
1ea6dd38
DH		 1738 int err;
1739 unsigned short address;
1740 struct resource res;
1741 struct w83627ehf_sio_data sio_data;
1742
1743 /* initialize sio_data->kind and sio_data->sioreg.
1744 *
1745 * when Super-I/O functions move to a separate file, the Super-I/O
1746 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1747 * w83627ehf hardware monitor, and call probe() */
1748 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1749 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1750 return -ENODEV;
1751
1ea6dd38
DH		 1752 err = platform_driver_register(&w83627ehf_driver);
1753 if (err)
1754 goto exit;
1755
e7e1ca6e
GR		 1756 pdev = platform_device_alloc(DRVNAME, address);
1757 if (!pdev) {
1ea6dd38 1758 err = -ENOMEM;
abdc6fd1 1759 pr_err("Device allocation failed\n");
1ea6dd38
DH		 1760 goto exit_unregister;
1761 }
1762
1763 err = platform_device_add_data(pdev, &sio_data,
1764 sizeof(struct w83627ehf_sio_data));
1765 if (err) {
abdc6fd1 1766 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 1767 goto exit_device_put;
1768 }
1769
1770 memset(&res, 0, sizeof(res));
1771 res.name = DRVNAME;
1772 res.start = address + IOREGION_OFFSET;
1773 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1774 res.flags = IORESOURCE_IO;
b9acb64a
JD		 1775
1776 err = acpi_check_resource_conflict(&res);
1777 if (err)
18632f84 1778 goto exit_device_put;
b9acb64a 1779
1ea6dd38
DH		 1780 err = platform_device_add_resources(pdev, &res, 1);
1781 if (err) {
abdc6fd1 1782 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 1783 goto exit_device_put;
1784 }
1785
1786 /* platform_device_add calls probe() */
1787 err = platform_device_add(pdev);
1788 if (err) {
abdc6fd1 1789 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 1790 goto exit_device_put;
1791 }
1792
1793 return 0;
1794
1795exit_device_put:
1796 platform_device_put(pdev);
1797exit_unregister:
1798 platform_driver_unregister(&w83627ehf_driver);
1799exit:
1800 return err;
08e7e278
JD		 1801}
1802
1803static void __exit sensors_w83627ehf_exit(void)
1804{
1ea6dd38
DH		 1805 platform_device_unregister(pdev);
1806 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1807}
1808
1809MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1810MODULE_DESCRIPTION("W83627EHF driver");
1811MODULE_LICENSE("GPL");
1812
1813module_init(sensors_w83627ehf_init);
1814module_exit(sensors_w83627ehf_exit);
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