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Merge branches 'pm-qos' and 'pm-devfreq'
[mirror_ubuntu-artful-kernel.git] / drivers / hwmon / w83781d.c
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1da177e4 1/*
aff6e00e
GR		 2 * w83781d.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring
4 * Copyright (c) 1998 - 2001 Frodo Looijaard <frodol@dds.nl>,
5 * Philip Edelbrock <phil@netroedge.com>,
6 * and Mark Studebaker <mdsxyz123@yahoo.com>
7c81c60f 7 * Copyright (c) 2007 - 2008 Jean Delvare <jdelvare@suse.de>
aff6e00e
GR		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
1da177e4
LT		 23
24/*
aff6e00e
GR		 25 * Supports following chips:
26 *
4101ece3 27 * Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
aff6e00e
GR		 28 * as99127f 7 3 0 3 0x31 0x12c3 yes no
29 * as99127f rev.2 (type_name = as99127f) 0x31 0x5ca3 yes no
30 * w83781d 7 3 0 3 0x10-1 0x5ca3 yes yes
31 * w83782d 9 3 2-4 3 0x30 0x5ca3 yes yes
32 * w83783s 5-6 3 2 1-2 0x40 0x5ca3 yes no
33 *
34 */
1da177e4 35
1ca28218
JP		 36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/init.h>
40#include <linux/slab.h>
41#include <linux/jiffies.h>
42#include <linux/i2c.h>
943b0830 43#include <linux/hwmon.h>
303760b4 44#include <linux/hwmon-vid.h>
34875337 45#include <linux/hwmon-sysfs.h>
311ce2ef 46#include <linux/sysfs.h>
943b0830 47#include <linux/err.h>
9a61bf63 48#include <linux/mutex.h>
443850ce
WG		 49
50#ifdef CONFIG_ISA
51#include <linux/platform_device.h>
52#include <linux/ioport.h>
6055fae8 53#include <linux/io.h>
443850ce 54#endif
1da177e4 55
443850ce 56#include "lm75.h"
7666c13c 57
1da177e4 58/* Addresses to scan */
25e9c86d
MH		 59static const unsigned short normal_i2c[] = { 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d,
60 0x2e, 0x2f, I2C_CLIENT_END };
3aed198c 61
e5e9f44c
JD		 62enum chips { w83781d, w83782d, w83783s, as99127f };
63
64/* Insmod parameters */
3aed198c
JD		 65static unsigned short force_subclients[4];
66module_param_array(force_subclients, short, NULL, 0);
b55f3757
GR		 67MODULE_PARM_DESC(force_subclients,
68 "List of subclient addresses: {bus, clientaddr, subclientaddr1, subclientaddr2}");
1da177e4 69
90ab5ee9 70static bool reset;
fabddcd4
JD		 71module_param(reset, bool, 0);
72MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
73
90ab5ee9 74static bool init = 1;
1da177e4
LT		 75module_param(init, bool, 0);
76MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
77
78/* Constants specified below */
79
80/* Length of ISA address segment */
81#define W83781D_EXTENT 8
82
83/* Where are the ISA address/data registers relative to the base address */
84#define W83781D_ADDR_REG_OFFSET 5
85#define W83781D_DATA_REG_OFFSET 6
86
34875337
JD		 87/* The device registers */
88/* in nr from 0 to 8 */
1da177e4
LT		 89#define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
90 (0x554 + (((nr) - 7) * 2)))
91#define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
92 (0x555 + (((nr) - 7) * 2)))
93#define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
94 (0x550 + (nr) - 7))
95
34875337
JD		 96/* fan nr from 0 to 2 */
97#define W83781D_REG_FAN_MIN(nr) (0x3b + (nr))
98#define W83781D_REG_FAN(nr) (0x28 + (nr))
1da177e4
LT		 99
100#define W83781D_REG_BANK 0x4E
101#define W83781D_REG_TEMP2_CONFIG 0x152
102#define W83781D_REG_TEMP3_CONFIG 0x252
34875337 103/* temp nr from 1 to 3 */
1da177e4
LT		 104#define W83781D_REG_TEMP(nr) ((nr == 3) ? (0x0250) : \
105 ((nr == 2) ? (0x0150) : \
106 (0x27)))
107#define W83781D_REG_TEMP_HYST(nr) ((nr == 3) ? (0x253) : \
108 ((nr == 2) ? (0x153) : \
109 (0x3A)))
110#define W83781D_REG_TEMP_OVER(nr) ((nr == 3) ? (0x255) : \
111 ((nr == 2) ? (0x155) : \
112 (0x39)))
113
114#define W83781D_REG_CONFIG 0x40
c7f5d7ed
JD		 115
116/* Interrupt status (W83781D, AS99127F) */
1da177e4
LT		 117#define W83781D_REG_ALARM1 0x41
118#define W83781D_REG_ALARM2 0x42
1da177e4 119
05663368 120/* Real-time status (W83782D, W83783S) */
c7f5d7ed
JD		 121#define W83782D_REG_ALARM1 0x459
122#define W83782D_REG_ALARM2 0x45A
123#define W83782D_REG_ALARM3 0x45B
124
1da177e4
LT		 125#define W83781D_REG_BEEP_CONFIG 0x4D
126#define W83781D_REG_BEEP_INTS1 0x56
127#define W83781D_REG_BEEP_INTS2 0x57
128#define W83781D_REG_BEEP_INTS3 0x453 /* not on W83781D */
129
130#define W83781D_REG_VID_FANDIV 0x47
131
132#define W83781D_REG_CHIPID 0x49
133#define W83781D_REG_WCHIPID 0x58
134#define W83781D_REG_CHIPMAN 0x4F
135#define W83781D_REG_PIN 0x4B
136
137/* 782D/783S only */
138#define W83781D_REG_VBAT 0x5D
139
140/* PWM 782D (1-4) and 783S (1-2) only */
34875337 141static const u8 W83781D_REG_PWM[] = { 0x5B, 0x5A, 0x5E, 0x5F };
1da177e4
LT		 142#define W83781D_REG_PWMCLK12 0x5C
143#define W83781D_REG_PWMCLK34 0x45C
1da177e4
LT		 144
145#define W83781D_REG_I2C_ADDR 0x48
146#define W83781D_REG_I2C_SUBADDR 0x4A
147
aff6e00e
GR		 148/*
149 * The following are undocumented in the data sheets however we
150 * received the information in an email from Winbond tech support
151 */
1da177e4
LT		 152/* Sensor selection - not on 781d */
153#define W83781D_REG_SCFG1 0x5D
154static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
155
156#define W83781D_REG_SCFG2 0x59
157static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
158
159#define W83781D_DEFAULT_BETA 3435
160
474d00a8 161/* Conversions */
2a844c14 162#define IN_TO_REG(val) clamp_val(((val) + 8) / 16, 0, 255)
474d00a8 163#define IN_FROM_REG(val) ((val) * 16)
1da177e4
LT		 164
165static inline u8
166FAN_TO_REG(long rpm, int div)
167{
168 if (rpm == 0)
169 return 255;
2a844c14
GR		 170 rpm = clamp_val(rpm, 1, 1000000);
171 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
1da177e4
LT		 172}
173
474d00a8
JD		 174static inline long
175FAN_FROM_REG(u8 val, int div)
176{
177 if (val == 0)
178 return -1;
179 if (val == 255)
180 return 0;
181 return 1350000 / (val * div);
182}
1da177e4 183
2a844c14 184#define TEMP_TO_REG(val) clamp_val((val) / 1000, -127, 128)
474d00a8 185#define TEMP_FROM_REG(val) ((val) * 1000)
1da177e4 186
c531eb3f 187#define BEEP_MASK_FROM_REG(val, type) ((type) == as99127f ? \
2fbbbf14 188 (~(val)) & 0x7fff : (val) & 0xff7fff)
c531eb3f 189#define BEEP_MASK_TO_REG(val, type) ((type) == as99127f ? \
2fbbbf14 190 (~(val)) & 0x7fff : (val) & 0xff7fff)
1da177e4 191
1da177e4
LT		 192#define DIV_FROM_REG(val) (1 << (val))
193
194static inline u8
195DIV_TO_REG(long val, enum chips type)
196{
197 int i;
2a844c14
GR		 198 val = clamp_val(val, 1,
199 ((type == w83781d || type == as99127f) ? 8 : 128)) >> 1;
abc01922 200 for (i = 0; i < 7; i++) {
1da177e4
LT		 201 if (val == 0)
202 break;
203 val >>= 1;
204 }
474d00a8 205 return i;
1da177e4
LT		 206}
207
1da177e4 208struct w83781d_data {
0217eae3 209 struct i2c_client *client;
1beeffe4 210 struct device *hwmon_dev;
9a61bf63 211 struct mutex lock;
1da177e4
LT		 212 enum chips type;
213
360782dd
JD		 214 /* For ISA device only */
215 const char *name;
216 int isa_addr;
217
9a61bf63 218 struct mutex update_lock;
1da177e4
LT		 219 char valid; /* !=0 if following fields are valid */
220 unsigned long last_updated; /* In jiffies */
221
222 struct i2c_client *lm75[2]; /* for secondary I2C addresses */
223 /* array of 2 pointers to subclients */
224
225 u8 in[9]; /* Register value - 8 & 9 for 782D only */
226 u8 in_max[9]; /* Register value - 8 & 9 for 782D only */
227 u8 in_min[9]; /* Register value - 8 & 9 for 782D only */
228 u8 fan[3]; /* Register value */
229 u8 fan_min[3]; /* Register value */
474d00a8
JD		 230 s8 temp; /* Register value */
231 s8 temp_max; /* Register value */
232 s8 temp_max_hyst; /* Register value */
1da177e4
LT		 233 u16 temp_add[2]; /* Register value */
234 u16 temp_max_add[2]; /* Register value */
235 u16 temp_max_hyst_add[2]; /* Register value */
236 u8 fan_div[3]; /* Register encoding, shifted right */
237 u8 vid; /* Register encoding, combined */
238 u32 alarms; /* Register encoding, combined */
239 u32 beep_mask; /* Register encoding, combined */
1da177e4 240 u8 pwm[4]; /* Register value */
34875337 241 u8 pwm2_enable; /* Boolean */
aff6e00e
GR		 242 u16 sens[3]; /*
243 * 782D/783S only.
244 * 1 = pentium diode; 2 = 3904 diode;
245 * 4 = thermistor
246 */
1da177e4
LT		 247 u8 vrm;
248};
249
443850ce
WG		 250static struct w83781d_data *w83781d_data_if_isa(void);
251static int w83781d_alias_detect(struct i2c_client *client, u8 chipid);
252
31b8dc4d
JD		 253static int w83781d_read_value(struct w83781d_data *data, u16 reg);
254static int w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value);
1da177e4 255static struct w83781d_data *w83781d_update_device(struct device *dev);
7666c13c 256static void w83781d_init_device(struct device *dev);
1da177e4 257
1da177e4
LT		 258/* following are the sysfs callback functions */
259#define show_in_reg(reg) \
c531eb3f 260static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 261 char *buf) \
1da177e4 262{ \
34875337 263 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 264 struct w83781d_data *data = w83781d_update_device(dev); \
34875337
JD		 265 return sprintf(buf, "%ld\n", \
266 (long)IN_FROM_REG(data->reg[attr->index])); \
1da177e4
LT		 267}
268show_in_reg(in);
269show_in_reg(in_min);
270show_in_reg(in_max);
271
272#define store_in_reg(REG, reg) \
c531eb3f 273static ssize_t store_in_##reg(struct device *dev, struct device_attribute \
34875337 274 *da, const char *buf, size_t count) \
1da177e4 275{ \
34875337 276 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
7666c13c 277 struct w83781d_data *data = dev_get_drvdata(dev); \
34875337 278 int nr = attr->index; \
c531eb3f
GR		 279 unsigned long val; \
280 int err = kstrtoul(buf, 10, &val); \
281 if (err) \
282 return err; \
9a61bf63 283 mutex_lock(&data->update_lock); \
1da177e4 284 data->in_##reg[nr] = IN_TO_REG(val); \
c531eb3f
GR		 285 w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
286 data->in_##reg[nr]); \
287 \
9a61bf63 288 mutex_unlock(&data->update_lock); \
1da177e4
LT		 289 return count; \
290}
291store_in_reg(MIN, min);
292store_in_reg(MAX, max);
293
1da177e4 294#define sysfs_in_offsets(offset) \
34875337
JD		 295static SENSOR_DEVICE_ATTR(in##offset##_input, S_IRUGO, \
296 show_in, NULL, offset); \
297static SENSOR_DEVICE_ATTR(in##offset##_min, S_IRUGO | S_IWUSR, \
298 show_in_min, store_in_min, offset); \
299static SENSOR_DEVICE_ATTR(in##offset##_max, S_IRUGO | S_IWUSR, \
300 show_in_max, store_in_max, offset)
1da177e4
LT		 301
302sysfs_in_offsets(0);
303sysfs_in_offsets(1);
304sysfs_in_offsets(2);
305sysfs_in_offsets(3);
306sysfs_in_offsets(4);
307sysfs_in_offsets(5);
308sysfs_in_offsets(6);
309sysfs_in_offsets(7);
310sysfs_in_offsets(8);
311
1da177e4 312#define show_fan_reg(reg) \
c531eb3f 313static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 314 char *buf) \
1da177e4 315{ \
34875337 316 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 317 struct w83781d_data *data = w83781d_update_device(dev); \
c531eb3f 318 return sprintf(buf, "%ld\n", \
34875337
JD		 319 FAN_FROM_REG(data->reg[attr->index], \
320 DIV_FROM_REG(data->fan_div[attr->index]))); \
1da177e4
LT		 321}
322show_fan_reg(fan);
323show_fan_reg(fan_min);
324
325static ssize_t
34875337
JD		 326store_fan_min(struct device *dev, struct device_attribute *da,
327 const char *buf, size_t count)
1da177e4 328{
34875337 329 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 330 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 331 int nr = attr->index;
c531eb3f
GR		 332 unsigned long val;
333 int err;
1da177e4 334
c531eb3f
GR		 335 err = kstrtoul(buf, 10, &val);
336 if (err)
337 return err;
1da177e4 338
9a61bf63 339 mutex_lock(&data->update_lock);
34875337
JD		 340 data->fan_min[nr] =
341 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
31b8dc4d 342 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr),
34875337 343 data->fan_min[nr]);
1da177e4 344
9a61bf63 345 mutex_unlock(&data->update_lock);
1da177e4
LT		 346 return count;
347}
348
34875337
JD		 349static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0);
350static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO | S_IWUSR,
351 show_fan_min, store_fan_min, 0);
352static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1);
353static SENSOR_DEVICE_ATTR(fan2_min, S_IRUGO | S_IWUSR,
354 show_fan_min, store_fan_min, 1);
355static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2);
356static SENSOR_DEVICE_ATTR(fan3_min, S_IRUGO | S_IWUSR,
357 show_fan_min, store_fan_min, 2);
1da177e4 358
1da177e4 359#define show_temp_reg(reg) \
c531eb3f 360static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 361 char *buf) \
1da177e4 362{ \
34875337 363 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 364 struct w83781d_data *data = w83781d_update_device(dev); \
34875337 365 int nr = attr->index; \
1da177e4 366 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
c531eb3f 367 return sprintf(buf, "%d\n", \
1da177e4
LT		 368 LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
369 } else { /* TEMP1 */ \
c531eb3f 370 return sprintf(buf, "%ld\n", (long)TEMP_FROM_REG(data->reg)); \
1da177e4
LT		 371 } \
372}
373show_temp_reg(temp);
374show_temp_reg(temp_max);
375show_temp_reg(temp_max_hyst);
376
377#define store_temp_reg(REG, reg) \
c531eb3f 378static ssize_t store_temp_##reg(struct device *dev, \
34875337 379 struct device_attribute *da, const char *buf, size_t count) \
1da177e4 380{ \
34875337 381 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
7666c13c 382 struct w83781d_data *data = dev_get_drvdata(dev); \
34875337 383 int nr = attr->index; \
5bfedac0 384 long val; \
c531eb3f
GR		 385 int err = kstrtol(buf, 10, &val); \
386 if (err) \
387 return err; \
9a61bf63 388 mutex_lock(&data->update_lock); \
1da177e4
LT		 389 \
390 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
391 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
31b8dc4d 392 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
1da177e4
LT		 393 data->temp_##reg##_add[nr-2]); \
394 } else { /* TEMP1 */ \
395 data->temp_##reg = TEMP_TO_REG(val); \
31b8dc4d 396 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
1da177e4
LT		 397 data->temp_##reg); \
398 } \
399 \
9a61bf63 400 mutex_unlock(&data->update_lock); \
1da177e4
LT		 401 return count; \
402}
403store_temp_reg(OVER, max);
404store_temp_reg(HYST, max_hyst);
405
1da177e4 406#define sysfs_temp_offsets(offset) \
34875337
JD		 407static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, \
408 show_temp, NULL, offset); \
409static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \
410 show_temp_max, store_temp_max, offset); \
411static SENSOR_DEVICE_ATTR(temp##offset##_max_hyst, S_IRUGO | S_IWUSR, \
412 show_temp_max_hyst, store_temp_max_hyst, offset);
1da177e4
LT		 413
414sysfs_temp_offsets(1);
415sysfs_temp_offsets(2);
416sysfs_temp_offsets(3);
417
1da177e4 418static ssize_t
b80b814b 419cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 420{
421 struct w83781d_data *data = w83781d_update_device(dev);
422 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
423}
424
b80b814b 425static DEVICE_ATTR_RO(cpu0_vid);
311ce2ef 426
1da177e4 427static ssize_t
b80b814b 428vrm_show(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4 429{
90d6619a 430 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4
LT		 431 return sprintf(buf, "%ld\n", (long) data->vrm);
432}
433
434static ssize_t
b80b814b
JL		 435vrm_store(struct device *dev, struct device_attribute *attr, const char *buf,
436 size_t count)
1da177e4 437{
7666c13c 438 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 439 unsigned long val;
440 int err;
1da177e4 441
c531eb3f
GR		 442 err = kstrtoul(buf, 10, &val);
443 if (err)
444 return err;
2a844c14 445 data->vrm = clamp_val(val, 0, 255);
1da177e4
LT		 446
447 return count;
448}
449
b80b814b 450static DEVICE_ATTR_RW(vrm);
311ce2ef 451
1da177e4 452static ssize_t
b80b814b 453alarms_show(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 454{
455 struct w83781d_data *data = w83781d_update_device(dev);
68188ba7 456 return sprintf(buf, "%u\n", data->alarms);
1da177e4
LT		 457}
458
b80b814b 459static DEVICE_ATTR_RO(alarms);
311ce2ef 460
7d4a1374
JD		 461static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
462 char *buf)
463{
464 struct w83781d_data *data = w83781d_update_device(dev);
465 int bitnr = to_sensor_dev_attr(attr)->index;
466 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
467}
468
469/* The W83781D has a single alarm bit for temp2 and temp3 */
470static ssize_t show_temp3_alarm(struct device *dev,
471 struct device_attribute *attr, char *buf)
472{
473 struct w83781d_data *data = w83781d_update_device(dev);
474 int bitnr = (data->type == w83781d) ? 5 : 13;
475 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
476}
477
478static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0);
479static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1);
480static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2);
481static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3);
482static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8);
483static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 9);
484static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 10);
485static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16);
486static SENSOR_DEVICE_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17);
487static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6);
488static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7);
489static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11);
490static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4);
491static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5);
492static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_temp3_alarm, NULL, 0);
493
b80b814b 494static ssize_t beep_mask_show(struct device *dev,
c531eb3f 495 struct device_attribute *attr, char *buf)
1da177e4
LT		 496{
497 struct w83781d_data *data = w83781d_update_device(dev);
498 return sprintf(buf, "%ld\n",
499 (long)BEEP_MASK_FROM_REG(data->beep_mask, data->type));
500}
1da177e4 501
1da177e4 502static ssize_t
b80b814b 503beep_mask_store(struct device *dev, struct device_attribute *attr,
34875337 504 const char *buf, size_t count)
1da177e4 505{
7666c13c 506 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 507 unsigned long val;
508 int err;
1da177e4 509
c531eb3f
GR		 510 err = kstrtoul(buf, 10, &val);
511 if (err)
512 return err;
1da177e4 513
9a61bf63 514 mutex_lock(&data->update_lock);
2fbbbf14
JD		 515 data->beep_mask &= 0x8000; /* preserve beep enable */
516 data->beep_mask |= BEEP_MASK_TO_REG(val, data->type);
34875337
JD		 517 w83781d_write_value(data, W83781D_REG_BEEP_INTS1,
518 data->beep_mask & 0xff);
519 w83781d_write_value(data, W83781D_REG_BEEP_INTS2,
2fbbbf14 520 (data->beep_mask >> 8) & 0xff);
34875337
JD		 521 if (data->type != w83781d && data->type != as99127f) {
522 w83781d_write_value(data, W83781D_REG_BEEP_INTS3,
523 ((data->beep_mask) >> 16) & 0xff);
524 }
525 mutex_unlock(&data->update_lock);
1da177e4 526
34875337
JD		 527 return count;
528}
1da177e4 529
b80b814b 530static DEVICE_ATTR_RW(beep_mask);
1da177e4 531
7d4a1374
JD		 532static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
533 char *buf)
534{
535 struct w83781d_data *data = w83781d_update_device(dev);
536 int bitnr = to_sensor_dev_attr(attr)->index;
537 return sprintf(buf, "%u\n", (data->beep_mask >> bitnr) & 1);
538}
539
540static ssize_t
541store_beep(struct device *dev, struct device_attribute *attr,
542 const char *buf, size_t count)
543{
544 struct w83781d_data *data = dev_get_drvdata(dev);
545 int bitnr = to_sensor_dev_attr(attr)->index;
7d4a1374 546 u8 reg;
c531eb3f
GR		 547 unsigned long bit;
548 int err;
549
550 err = kstrtoul(buf, 10, &bit);
551 if (err)
552 return err;
7d4a1374 553
7d4a1374
JD		 554 if (bit & ~1)
555 return -EINVAL;
556
557 mutex_lock(&data->update_lock);
558 if (bit)
559 data->beep_mask |= (1 << bitnr);
560 else
561 data->beep_mask &= ~(1 << bitnr);
562
563 if (bitnr < 8) {
564 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS1);
565 if (bit)
566 reg |= (1 << bitnr);
567 else
568 reg &= ~(1 << bitnr);
569 w83781d_write_value(data, W83781D_REG_BEEP_INTS1, reg);
570 } else if (bitnr < 16) {
571 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS2);
572 if (bit)
573 reg |= (1 << (bitnr - 8));
574 else
575 reg &= ~(1 << (bitnr - 8));
576 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, reg);
577 } else {
578 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS3);
579 if (bit)
580 reg |= (1 << (bitnr - 16));
581 else
582 reg &= ~(1 << (bitnr - 16));
583 w83781d_write_value(data, W83781D_REG_BEEP_INTS3, reg);
584 }
585 mutex_unlock(&data->update_lock);
586
587 return count;
588}
589
590/* The W83781D has a single beep bit for temp2 and temp3 */
591static ssize_t show_temp3_beep(struct device *dev,
592 struct device_attribute *attr, char *buf)
593{
594 struct w83781d_data *data = w83781d_update_device(dev);
595 int bitnr = (data->type == w83781d) ? 5 : 13;
596 return sprintf(buf, "%u\n", (data->beep_mask >> bitnr) & 1);
597}
598
599static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
600 show_beep, store_beep, 0);
601static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO | S_IWUSR,
602 show_beep, store_beep, 1);
603static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO | S_IWUSR,
604 show_beep, store_beep, 2);
605static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO | S_IWUSR,
606 show_beep, store_beep, 3);
607static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO | S_IWUSR,
608 show_beep, store_beep, 8);
609static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO | S_IWUSR,
610 show_beep, store_beep, 9);
611static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO | S_IWUSR,
612 show_beep, store_beep, 10);
613static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO | S_IWUSR,
614 show_beep, store_beep, 16);
615static SENSOR_DEVICE_ATTR(in8_beep, S_IRUGO | S_IWUSR,
616 show_beep, store_beep, 17);
617static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO | S_IWUSR,
618 show_beep, store_beep, 6);
619static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO | S_IWUSR,
620 show_beep, store_beep, 7);
621static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO | S_IWUSR,
622 show_beep, store_beep, 11);
623static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
624 show_beep, store_beep, 4);
625static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO | S_IWUSR,
626 show_beep, store_beep, 5);
627static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO,
628 show_temp3_beep, store_beep, 13);
2fbbbf14
JD		 629static SENSOR_DEVICE_ATTR(beep_enable, S_IRUGO | S_IWUSR,
630 show_beep, store_beep, 15);
7d4a1374 631
1da177e4 632static ssize_t
34875337 633show_fan_div(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 634{
34875337 635 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4
LT		 636 struct w83781d_data *data = w83781d_update_device(dev);
637 return sprintf(buf, "%ld\n",
34875337 638 (long) DIV_FROM_REG(data->fan_div[attr->index]));
1da177e4
LT		 639}
640
aff6e00e
GR		 641/*
642 * Note: we save and restore the fan minimum here, because its value is
643 * determined in part by the fan divisor. This follows the principle of
644 * least surprise; the user doesn't expect the fan minimum to change just
645 * because the divisor changed.
646 */
1da177e4 647static ssize_t
34875337
JD		 648store_fan_div(struct device *dev, struct device_attribute *da,
649 const char *buf, size_t count)
1da177e4 650{
34875337 651 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 652 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4 653 unsigned long min;
34875337 654 int nr = attr->index;
1da177e4 655 u8 reg;
c531eb3f
GR		 656 unsigned long val;
657 int err;
658
659 err = kstrtoul(buf, 10, &val);
660 if (err)
661 return err;
1da177e4 662
9a61bf63 663 mutex_lock(&data->update_lock);
293c0997 664
1da177e4
LT		 665 /* Save fan_min */
666 min = FAN_FROM_REG(data->fan_min[nr],
667 DIV_FROM_REG(data->fan_div[nr]));
668
669 data->fan_div[nr] = DIV_TO_REG(val, data->type);
670
c531eb3f
GR		 671 reg = (w83781d_read_value(data, nr == 2 ?
672 W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
673 & (nr == 0 ? 0xcf : 0x3f))
674 | ((data->fan_div[nr] & 0x03) << (nr == 0 ? 4 : 6));
675 w83781d_write_value(data, nr == 2 ?
676 W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
1da177e4
LT		 677
678 /* w83781d and as99127f don't have extended divisor bits */
679 if (data->type != w83781d && data->type != as99127f) {
31b8dc4d 680 reg = (w83781d_read_value(data, W83781D_REG_VBAT)
1da177e4
LT		 681 & ~(1 << (5 + nr)))
682 | ((data->fan_div[nr] & 0x04) << (3 + nr));
31b8dc4d 683 w83781d_write_value(data, W83781D_REG_VBAT, reg);
1da177e4
LT		 684 }
685
686 /* Restore fan_min */
687 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
34875337 688 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr), data->fan_min[nr]);
1da177e4 689
9a61bf63 690 mutex_unlock(&data->update_lock);
1da177e4
LT		 691 return count;
692}
693
34875337
JD		 694static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR,
695 show_fan_div, store_fan_div, 0);
696static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR,
697 show_fan_div, store_fan_div, 1);
698static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR,
699 show_fan_div, store_fan_div, 2);
1da177e4 700
1da177e4 701static ssize_t
34875337 702show_pwm(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 703{
34875337 704 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4 705 struct w83781d_data *data = w83781d_update_device(dev);
34875337 706 return sprintf(buf, "%d\n", (int)data->pwm[attr->index]);
1da177e4
LT		 707}
708
709static ssize_t
b80b814b 710pwm2_enable_show(struct device *dev, struct device_attribute *da, char *buf)
1da177e4
LT		 711{
712 struct w83781d_data *data = w83781d_update_device(dev);
34875337 713 return sprintf(buf, "%d\n", (int)data->pwm2_enable);
1da177e4
LT		 714}
715
716static ssize_t
34875337
JD		 717store_pwm(struct device *dev, struct device_attribute *da, const char *buf,
718 size_t count)
1da177e4 719{
34875337 720 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 721 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 722 int nr = attr->index;
c531eb3f
GR		 723 unsigned long val;
724 int err;
1da177e4 725
c531eb3f
GR		 726 err = kstrtoul(buf, 10, &val);
727 if (err)
728 return err;
1da177e4 729
9a61bf63 730 mutex_lock(&data->update_lock);
2a844c14 731 data->pwm[nr] = clamp_val(val, 0, 255);
34875337 732 w83781d_write_value(data, W83781D_REG_PWM[nr], data->pwm[nr]);
9a61bf63 733 mutex_unlock(&data->update_lock);
1da177e4
LT		 734 return count;
735}
736
737static ssize_t
b80b814b 738pwm2_enable_store(struct device *dev, struct device_attribute *da,
34875337 739 const char *buf, size_t count)
1da177e4 740{
7666c13c 741 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 742 unsigned long val;
743 u32 reg;
744 int err;
1da177e4 745
c531eb3f
GR		 746 err = kstrtoul(buf, 10, &val);
747 if (err)
748 return err;
1da177e4 749
9a61bf63 750 mutex_lock(&data->update_lock);
1da177e4
LT		 751
752 switch (val) {
753 case 0:
754 case 1:
31b8dc4d
JD		 755 reg = w83781d_read_value(data, W83781D_REG_PWMCLK12);
756 w83781d_write_value(data, W83781D_REG_PWMCLK12,
1da177e4
LT		 757 (reg & 0xf7) | (val << 3));
758
31b8dc4d
JD		 759 reg = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
760 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG,
1da177e4
LT		 761 (reg & 0xef) | (!val << 4));
762
34875337 763 data->pwm2_enable = val;
1da177e4
LT		 764 break;
765
766 default:
9a61bf63 767 mutex_unlock(&data->update_lock);
1da177e4
LT		 768 return -EINVAL;
769 }
770
9a61bf63 771 mutex_unlock(&data->update_lock);
1da177e4
LT		 772 return count;
773}
774
34875337
JD		 775static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 0);
776static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 1);
777static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 2);
778static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 3);
779/* only PWM2 can be enabled/disabled */
b80b814b 780static DEVICE_ATTR_RW(pwm2_enable);
1da177e4 781
1da177e4 782static ssize_t
34875337 783show_sensor(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 784{
34875337 785 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4 786 struct w83781d_data *data = w83781d_update_device(dev);
34875337 787 return sprintf(buf, "%d\n", (int)data->sens[attr->index]);
1da177e4
LT		 788}
789
790static ssize_t
34875337
JD		 791store_sensor(struct device *dev, struct device_attribute *da,
792 const char *buf, size_t count)
1da177e4 793{
34875337 794 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 795 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 796 int nr = attr->index;
c531eb3f
GR		 797 unsigned long val;
798 u32 tmp;
799 int err;
1da177e4 800
c531eb3f
GR		 801 err = kstrtoul(buf, 10, &val);
802 if (err)
803 return err;
1da177e4 804
9a61bf63 805 mutex_lock(&data->update_lock);
1da177e4
LT		 806
807 switch (val) {
808 case 1: /* PII/Celeron diode */
31b8dc4d
JD		 809 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
810 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337 811 tmp | BIT_SCFG1[nr]);
31b8dc4d
JD		 812 tmp = w83781d_read_value(data, W83781D_REG_SCFG2);
813 w83781d_write_value(data, W83781D_REG_SCFG2,
34875337
JD		 814 tmp | BIT_SCFG2[nr]);
815 data->sens[nr] = val;
1da177e4
LT		 816 break;
817 case 2: /* 3904 */
31b8dc4d
JD		 818 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
819 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337 820 tmp | BIT_SCFG1[nr]);
31b8dc4d
JD		 821 tmp = w83781d_read_value(data, W83781D_REG_SCFG2);
822 w83781d_write_value(data, W83781D_REG_SCFG2,
34875337
JD		 823 tmp & ~BIT_SCFG2[nr]);
824 data->sens[nr] = val;
1da177e4 825 break;
b26f9330 826 case W83781D_DEFAULT_BETA:
b55f3757
GR		 827 dev_warn(dev,
828 "Sensor type %d is deprecated, please use 4 instead\n",
829 W83781D_DEFAULT_BETA);
b26f9330
JD		 830 /* fall through */
831 case 4: /* thermistor */
31b8dc4d
JD		 832 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
833 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337
JD		 834 tmp & ~BIT_SCFG1[nr]);
835 data->sens[nr] = val;
1da177e4
LT		 836 break;
837 default:
b26f9330
JD		 838 dev_err(dev, "Invalid sensor type %ld; must be 1, 2, or 4\n",
839 (long) val);
1da177e4
LT		 840 break;
841 }
842
9a61bf63 843 mutex_unlock(&data->update_lock);
1da177e4
LT		 844 return count;
845}
846
34875337
JD		 847static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR,
848 show_sensor, store_sensor, 0);
849static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR,
393cdad6 850 show_sensor, store_sensor, 1);
34875337 851static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR,
393cdad6 852 show_sensor, store_sensor, 2);
1da177e4 853
aff6e00e
GR		 854/*
855 * Assumes that adapter is of I2C, not ISA variety.
1da177e4
LT		 856 * OTHERWISE DON'T CALL THIS
857 */
858static int
0217eae3 859w83781d_detect_subclients(struct i2c_client *new_client)
1da177e4
LT		 860{
861 int i, val1 = 0, id;
862 int err;
0217eae3
WG		 863 int address = new_client->addr;
864 unsigned short sc_addr[2];
865 struct i2c_adapter *adapter = new_client->adapter;
1da177e4 866 struct w83781d_data *data = i2c_get_clientdata(new_client);
0217eae3 867 enum chips kind = data->type;
bbc8a569 868 int num_sc = 1;
1da177e4
LT		 869
870 id = i2c_adapter_id(adapter);
871
872 if (force_subclients[0] == id && force_subclients[1] == address) {
873 for (i = 2; i <= 3; i++) {
874 if (force_subclients[i] < 0x48 ||
875 force_subclients[i] > 0x4f) {
b55f3757
GR		 876 dev_err(&new_client->dev,
877 "Invalid subclient address %d; must be 0x48-0x4f\n",
1da177e4
LT		 878 force_subclients[i]);
879 err = -EINVAL;
880 goto ERROR_SC_1;
881 }
882 }
31b8dc4d 883 w83781d_write_value(data, W83781D_REG_I2C_SUBADDR,
1da177e4
LT		 884 (force_subclients[2] & 0x07) |
885 ((force_subclients[3] & 0x07) << 4));
0217eae3 886 sc_addr[0] = force_subclients[2];
1da177e4 887 } else {
31b8dc4d 888 val1 = w83781d_read_value(data, W83781D_REG_I2C_SUBADDR);
0217eae3 889 sc_addr[0] = 0x48 + (val1 & 0x07);
1da177e4
LT		 890 }
891
892 if (kind != w83783s) {
bbc8a569 893 num_sc = 2;
1da177e4
LT		 894 if (force_subclients[0] == id &&
895 force_subclients[1] == address) {
0217eae3 896 sc_addr[1] = force_subclients[3];
1da177e4 897 } else {
0217eae3 898 sc_addr[1] = 0x48 + ((val1 >> 4) & 0x07);
1da177e4 899 }
0217eae3 900 if (sc_addr[0] == sc_addr[1]) {
1da177e4
LT		 901 dev_err(&new_client->dev,
902 "Duplicate addresses 0x%x for subclients.\n",
0217eae3 903 sc_addr[0]);
1da177e4
LT		 904 err = -EBUSY;
905 goto ERROR_SC_2;
906 }
907 }
908
bbc8a569 909 for (i = 0; i < num_sc; i++) {
0217eae3
WG		 910 data->lm75[i] = i2c_new_dummy(adapter, sc_addr[i]);
911 if (!data->lm75[i]) {
b55f3757
GR		 912 dev_err(&new_client->dev,
913 "Subclient %d registration at address 0x%x failed.\n",
914 i, sc_addr[i]);
0217eae3 915 err = -ENOMEM;
1da177e4
LT		 916 if (i == 1)
917 goto ERROR_SC_3;
918 goto ERROR_SC_2;
919 }
1da177e4
LT		 920 }
921
922 return 0;
923
924/* Undo inits in case of errors */
925ERROR_SC_3:
0217eae3 926 i2c_unregister_device(data->lm75[0]);
1da177e4 927ERROR_SC_2:
1da177e4 928ERROR_SC_1:
1da177e4
LT		 929 return err;
930}
931
34875337
JD		 932#define IN_UNIT_ATTRS(X) \
933 &sensor_dev_attr_in##X##_input.dev_attr.attr, \
934 &sensor_dev_attr_in##X##_min.dev_attr.attr, \
293c0997 935 &sensor_dev_attr_in##X##_max.dev_attr.attr, \
7d4a1374
JD		 936 &sensor_dev_attr_in##X##_alarm.dev_attr.attr, \
937 &sensor_dev_attr_in##X##_beep.dev_attr.attr
311ce2ef 938
34875337
JD		 939#define FAN_UNIT_ATTRS(X) \
940 &sensor_dev_attr_fan##X##_input.dev_attr.attr, \
941 &sensor_dev_attr_fan##X##_min.dev_attr.attr, \
7d4a1374
JD		 942 &sensor_dev_attr_fan##X##_div.dev_attr.attr, \
943 &sensor_dev_attr_fan##X##_alarm.dev_attr.attr, \
944 &sensor_dev_attr_fan##X##_beep.dev_attr.attr
311ce2ef 945
34875337
JD		 946#define TEMP_UNIT_ATTRS(X) \
947 &sensor_dev_attr_temp##X##_input.dev_attr.attr, \
948 &sensor_dev_attr_temp##X##_max.dev_attr.attr, \
7d4a1374
JD		 949 &sensor_dev_attr_temp##X##_max_hyst.dev_attr.attr, \
950 &sensor_dev_attr_temp##X##_alarm.dev_attr.attr, \
951 &sensor_dev_attr_temp##X##_beep.dev_attr.attr
311ce2ef 952
c531eb3f 953static struct attribute *w83781d_attributes[] = {
311ce2ef
JC		 954 IN_UNIT_ATTRS(0),
955 IN_UNIT_ATTRS(2),
956 IN_UNIT_ATTRS(3),
957 IN_UNIT_ATTRS(4),
958 IN_UNIT_ATTRS(5),
959 IN_UNIT_ATTRS(6),
960 FAN_UNIT_ATTRS(1),
961 FAN_UNIT_ATTRS(2),
962 FAN_UNIT_ATTRS(3),
963 TEMP_UNIT_ATTRS(1),
964 TEMP_UNIT_ATTRS(2),
965 &dev_attr_cpu0_vid.attr,
966 &dev_attr_vrm.attr,
967 &dev_attr_alarms.attr,
968 &dev_attr_beep_mask.attr,
2fbbbf14 969 &sensor_dev_attr_beep_enable.dev_attr.attr,
311ce2ef
JC		 970 NULL
971};
972static const struct attribute_group w83781d_group = {
973 .attrs = w83781d_attributes,
974};
975
79501333 976static struct attribute *w83781d_attributes_in1[] = {
311ce2ef 977 IN_UNIT_ATTRS(1),
79501333
GR		 978 NULL
979};
980static const struct attribute_group w83781d_group_in1 = {
981 .attrs = w83781d_attributes_in1,
982};
983
984static struct attribute *w83781d_attributes_in78[] = {
311ce2ef
JC		 985 IN_UNIT_ATTRS(7),
986 IN_UNIT_ATTRS(8),
79501333
GR		 987 NULL
988};
989static const struct attribute_group w83781d_group_in78 = {
990 .attrs = w83781d_attributes_in78,
991};
992
993static struct attribute *w83781d_attributes_temp3[] = {
311ce2ef 994 TEMP_UNIT_ATTRS(3),
79501333
GR		 995 NULL
996};
997static const struct attribute_group w83781d_group_temp3 = {
998 .attrs = w83781d_attributes_temp3,
999};
1000
1001static struct attribute *w83781d_attributes_pwm12[] = {
34875337
JD		 1002 &sensor_dev_attr_pwm1.dev_attr.attr,
1003 &sensor_dev_attr_pwm2.dev_attr.attr,
79501333
GR		 1004 &dev_attr_pwm2_enable.attr,
1005 NULL
1006};
1007static const struct attribute_group w83781d_group_pwm12 = {
1008 .attrs = w83781d_attributes_pwm12,
1009};
1010
1011static struct attribute *w83781d_attributes_pwm34[] = {
34875337
JD		 1012 &sensor_dev_attr_pwm3.dev_attr.attr,
1013 &sensor_dev_attr_pwm4.dev_attr.attr,
79501333
GR		 1014 NULL
1015};
1016static const struct attribute_group w83781d_group_pwm34 = {
1017 .attrs = w83781d_attributes_pwm34,
1018};
1019
1020static struct attribute *w83781d_attributes_other[] = {
34875337
JD		 1021 &sensor_dev_attr_temp1_type.dev_attr.attr,
1022 &sensor_dev_attr_temp2_type.dev_attr.attr,
1023 &sensor_dev_attr_temp3_type.dev_attr.attr,
311ce2ef
JC		 1024 NULL
1025};
79501333
GR		 1026static const struct attribute_group w83781d_group_other = {
1027 .attrs = w83781d_attributes_other,
311ce2ef
JC		 1028};
1029
7666c13c 1030/* No clean up is done on error, it's up to the caller */
1da177e4 1031static int
7666c13c 1032w83781d_create_files(struct device *dev, int kind, int is_isa)
1da177e4 1033{
1da177e4 1034 int err;
1da177e4 1035
c531eb3f
GR		 1036 err = sysfs_create_group(&dev->kobj, &w83781d_group);
1037 if (err)
7666c13c
JD		 1038 return err;
1039
1040 if (kind != w83783s) {
79501333
GR		 1041 err = sysfs_create_group(&dev->kobj, &w83781d_group_in1);
1042 if (err)
7666c13c
JD		 1043 return err;
1044 }
1045 if (kind != as99127f && kind != w83781d && kind != w83783s) {
79501333
GR		 1046 err = sysfs_create_group(&dev->kobj, &w83781d_group_in78);
1047 if (err)
7666c13c
JD		 1048 return err;
1049 }
1050 if (kind != w83783s) {
79501333
GR		 1051 err = sysfs_create_group(&dev->kobj, &w83781d_group_temp3);
1052 if (err)
7666c13c 1053 return err;
7d4a1374 1054
7768aa76 1055 if (kind != w83781d) {
7d4a1374
JD		 1056 err = sysfs_chmod_file(&dev->kobj,
1057 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1058 S_IRUGO | S_IWUSR);
1059 if (err)
1060 return err;
7768aa76 1061 }
1da177e4
LT		 1062 }
1063
7666c13c 1064 if (kind != w83781d && kind != as99127f) {
79501333
GR		 1065 err = sysfs_create_group(&dev->kobj, &w83781d_group_pwm12);
1066 if (err)
7666c13c 1067 return err;
1da177e4 1068 }
7666c13c 1069 if (kind == w83782d && !is_isa) {
79501333
GR		 1070 err = sysfs_create_group(&dev->kobj, &w83781d_group_pwm34);
1071 if (err)
7666c13c
JD		 1072 return err;
1073 }
1074
1075 if (kind != as99127f && kind != w83781d) {
79501333
GR		 1076 err = device_create_file(dev,
1077 &sensor_dev_attr_temp1_type.dev_attr);
1078 if (err)
1079 return err;
1080 err = device_create_file(dev,
1081 &sensor_dev_attr_temp2_type.dev_attr);
1082 if (err)
7666c13c
JD		 1083 return err;
1084 if (kind != w83783s) {
c531eb3f 1085 err = device_create_file(dev,
79501333 1086 &sensor_dev_attr_temp3_type.dev_attr);
c531eb3f 1087 if (err)
7666c13c 1088 return err;
1da177e4 1089 }
7666c13c 1090 }
1da177e4 1091
7666c13c
JD		 1092 return 0;
1093}
1da177e4 1094
0217eae3 1095/* Return 0 if detection is successful, -ENODEV otherwise */
7666c13c 1096static int
310ec792 1097w83781d_detect(struct i2c_client *client, struct i2c_board_info *info)
7666c13c 1098{
bab2bf44 1099 int val1, val2;
0217eae3
WG		 1100 struct w83781d_data *isa = w83781d_data_if_isa();
1101 struct i2c_adapter *adapter = client->adapter;
1102 int address = client->addr;
bab2bf44 1103 const char *client_name;
7666c13c
JD		 1104 enum vendor { winbond, asus } vendid;
1105
0217eae3
WG		 1106 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1107 return -ENODEV;
1da177e4 1108
aff6e00e
GR		 1109 /*
1110 * We block updates of the ISA device to minimize the risk of
1111 * concurrent access to the same W83781D chip through different
1112 * interfaces.
1113 */
0217eae3
WG		 1114 if (isa)
1115 mutex_lock(&isa->update_lock);
1da177e4 1116
bab2bf44
JD		 1117 if (i2c_smbus_read_byte_data(client, W83781D_REG_CONFIG) & 0x80) {
1118 dev_dbg(&adapter->dev,
1119 "Detection of w83781d chip failed at step 3\n");
1120 goto err_nodev;
1121 }
1122
1123 val1 = i2c_smbus_read_byte_data(client, W83781D_REG_BANK);
1124 val2 = i2c_smbus_read_byte_data(client, W83781D_REG_CHIPMAN);
1125 /* Check for Winbond or Asus ID if in bank 0 */
1126 if (!(val1 & 0x07) &&
1127 ((!(val1 & 0x80) && val2 != 0xa3 && val2 != 0xc3) ||
c531eb3f 1128 ((val1 & 0x80) && val2 != 0x5c && val2 != 0x12))) {
bab2bf44
JD		 1129 dev_dbg(&adapter->dev,
1130 "Detection of w83781d chip failed at step 4\n");
1131 goto err_nodev;
1132 }
aff6e00e
GR		 1133 /*
1134 * If Winbond SMBus, check address at 0x48.
1135 * Asus doesn't support, except for as99127f rev.2
1136 */
bab2bf44 1137 if ((!(val1 & 0x80) && val2 == 0xa3) ||
c531eb3f 1138 ((val1 & 0x80) && val2 == 0x5c)) {
bab2bf44
JD		 1139 if (i2c_smbus_read_byte_data(client, W83781D_REG_I2C_ADDR)
1140 != address) {
1141 dev_dbg(&adapter->dev,
1142 "Detection of w83781d chip failed at step 5\n");
0217eae3 1143 goto err_nodev;
1da177e4 1144 }
1da177e4
LT		 1145 }
1146
bab2bf44 1147 /* Put it now into bank 0 and Vendor ID High Byte */
0217eae3
WG		 1148 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1149 (i2c_smbus_read_byte_data(client, W83781D_REG_BANK)
1150 & 0x78) | 0x80);
1da177e4 1151
bab2bf44
JD		 1152 /* Get the vendor ID */
1153 val2 = i2c_smbus_read_byte_data(client, W83781D_REG_CHIPMAN);
1154 if (val2 == 0x5c)
1155 vendid = winbond;
1156 else if (val2 == 0x12)
1157 vendid = asus;
1158 else {
1159 dev_dbg(&adapter->dev,
1160 "w83781d chip vendor is neither Winbond nor Asus\n");
1161 goto err_nodev;
1da177e4
LT		 1162 }
1163
bab2bf44
JD		 1164 /* Determine the chip type. */
1165 val1 = i2c_smbus_read_byte_data(client, W83781D_REG_WCHIPID);
1166 if ((val1 == 0x10 || val1 == 0x11) && vendid == winbond)
1da177e4 1167 client_name = "w83781d";
bab2bf44 1168 else if (val1 == 0x30 && vendid == winbond)
1da177e4 1169 client_name = "w83782d";
bab2bf44 1170 else if (val1 == 0x40 && vendid == winbond && address == 0x2d)
1da177e4 1171 client_name = "w83783s";
bab2bf44 1172 else if (val1 == 0x31)
1da177e4 1173 client_name = "as99127f";
bab2bf44
JD		 1174 else
1175 goto err_nodev;
1176
1177 if (val1 <= 0x30 && w83781d_alias_detect(client, val1)) {
b55f3757
GR		 1178 dev_dbg(&adapter->dev,
1179 "Device at 0x%02x appears to be the same as ISA device\n",
1180 address);
bab2bf44 1181 goto err_nodev;
1da177e4
LT		 1182 }
1183
bab2bf44
JD		 1184 if (isa)
1185 mutex_unlock(&isa->update_lock);
1186
0217eae3
WG		 1187 strlcpy(info->type, client_name, I2C_NAME_SIZE);
1188
1189 return 0;
1190
1191 err_nodev:
1192 if (isa)
1193 mutex_unlock(&isa->update_lock);
1194 return -ENODEV;
1195}
1196
79501333
GR		 1197static void w83781d_remove_files(struct device *dev)
1198{
1199 sysfs_remove_group(&dev->kobj, &w83781d_group);
1200 sysfs_remove_group(&dev->kobj, &w83781d_group_in1);
1201 sysfs_remove_group(&dev->kobj, &w83781d_group_in78);
1202 sysfs_remove_group(&dev->kobj, &w83781d_group_temp3);
1203 sysfs_remove_group(&dev->kobj, &w83781d_group_pwm12);
1204 sysfs_remove_group(&dev->kobj, &w83781d_group_pwm34);
1205 sysfs_remove_group(&dev->kobj, &w83781d_group_other);
1206}
1207
0217eae3
WG		 1208static int
1209w83781d_probe(struct i2c_client *client, const struct i2c_device_id *id)
1210{
1211 struct device *dev = &client->dev;
1212 struct w83781d_data *data;
1213 int err;
1214
144d2b99
GR		 1215 data = devm_kzalloc(dev, sizeof(struct w83781d_data), GFP_KERNEL);
1216 if (!data)
1217 return -ENOMEM;
0217eae3
WG		 1218
1219 i2c_set_clientdata(client, data);
1220 mutex_init(&data->lock);
1221 mutex_init(&data->update_lock);
1da177e4 1222
0217eae3
WG		 1223 data->type = id->driver_data;
1224 data->client = client;
1da177e4
LT		 1225
1226 /* attach secondary i2c lm75-like clients */
0217eae3
WG		 1227 err = w83781d_detect_subclients(client);
1228 if (err)
144d2b99 1229 return err;
1da177e4
LT		 1230
1231 /* Initialize the chip */
7666c13c 1232 w83781d_init_device(dev);
1da177e4
LT		 1233
1234 /* Register sysfs hooks */
0217eae3 1235 err = w83781d_create_files(dev, data->type, 0);
7666c13c 1236 if (err)
144d2b99 1237 goto exit_remove_files;
943b0830 1238
1beeffe4
TJ		 1239 data->hwmon_dev = hwmon_device_register(dev);
1240 if (IS_ERR(data->hwmon_dev)) {
1241 err = PTR_ERR(data->hwmon_dev);
144d2b99 1242 goto exit_remove_files;
1da177e4
LT		 1243 }
1244
1245 return 0;
1246
144d2b99 1247 exit_remove_files:
79501333 1248 w83781d_remove_files(dev);
0217eae3
WG		 1249 if (data->lm75[0])
1250 i2c_unregister_device(data->lm75[0]);
1251 if (data->lm75[1])
1252 i2c_unregister_device(data->lm75[1]);
1da177e4
LT		 1253 return err;
1254}
1255
1256static int
0217eae3 1257w83781d_remove(struct i2c_client *client)
1da177e4 1258{
943b0830 1259 struct w83781d_data *data = i2c_get_clientdata(client);
0217eae3 1260 struct device *dev = &client->dev;
1da177e4 1261
0217eae3 1262 hwmon_device_unregister(data->hwmon_dev);
79501333 1263 w83781d_remove_files(dev);
1da177e4 1264
0217eae3
WG		 1265 if (data->lm75[0])
1266 i2c_unregister_device(data->lm75[0]);
1267 if (data->lm75[1])
1268 i2c_unregister_device(data->lm75[1]);
943b0830 1269
1da177e4
LT		 1270 return 0;
1271}
1272
1da177e4 1273static int
443850ce 1274w83781d_read_value_i2c(struct w83781d_data *data, u16 reg)
1da177e4 1275{
0217eae3 1276 struct i2c_client *client = data->client;
443850ce 1277 int res, bank;
1da177e4
LT		 1278 struct i2c_client *cl;
1279
443850ce
WG		 1280 bank = (reg >> 8) & 0x0f;
1281 if (bank > 2)
1282 /* switch banks */
1283 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1284 bank);
1285 if (bank == 0 || bank > 2) {
1286 res = i2c_smbus_read_byte_data(client, reg & 0xff);
1da177e4 1287 } else {
443850ce
WG		 1288 /* switch to subclient */
1289 cl = data->lm75[bank - 1];
1290 /* convert from ISA to LM75 I2C addresses */
1291 switch (reg & 0xff) {
1292 case 0x50: /* TEMP */
90f4102c 1293 res = i2c_smbus_read_word_swapped(cl, 0);
443850ce
WG		 1294 break;
1295 case 0x52: /* CONFIG */
1296 res = i2c_smbus_read_byte_data(cl, 1);
1297 break;
1298 case 0x53: /* HYST */
90f4102c 1299 res = i2c_smbus_read_word_swapped(cl, 2);
443850ce
WG		 1300 break;
1301 case 0x55: /* OVER */
1302 default:
90f4102c 1303 res = i2c_smbus_read_word_swapped(cl, 3);
443850ce 1304 break;
1da177e4 1305 }
1da177e4 1306 }
443850ce
WG		 1307 if (bank > 2)
1308 i2c_smbus_write_byte_data(client, W83781D_REG_BANK, 0);
1309
1da177e4
LT		 1310 return res;
1311}
1312
1313static int
443850ce 1314w83781d_write_value_i2c(struct w83781d_data *data, u16 reg, u16 value)
1da177e4 1315{
0217eae3 1316 struct i2c_client *client = data->client;
443850ce 1317 int bank;
1da177e4
LT		 1318 struct i2c_client *cl;
1319
443850ce
WG		 1320 bank = (reg >> 8) & 0x0f;
1321 if (bank > 2)
1322 /* switch banks */
1323 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1324 bank);
1325 if (bank == 0 || bank > 2) {
1326 i2c_smbus_write_byte_data(client, reg & 0xff,
1327 value & 0xff);
1da177e4 1328 } else {
443850ce
WG		 1329 /* switch to subclient */
1330 cl = data->lm75[bank - 1];
1331 /* convert from ISA to LM75 I2C addresses */
1332 switch (reg & 0xff) {
1333 case 0x52: /* CONFIG */
1334 i2c_smbus_write_byte_data(cl, 1, value & 0xff);
1335 break;
1336 case 0x53: /* HYST */
90f4102c 1337 i2c_smbus_write_word_swapped(cl, 2, value);
443850ce
WG		 1338 break;
1339 case 0x55: /* OVER */
90f4102c 1340 i2c_smbus_write_word_swapped(cl, 3, value);
443850ce 1341 break;
1da177e4 1342 }
1da177e4 1343 }
443850ce
WG		 1344 if (bank > 2)
1345 i2c_smbus_write_byte_data(client, W83781D_REG_BANK, 0);
1346
1da177e4
LT		 1347 return 0;
1348}
1349
1da177e4 1350static void
7666c13c 1351w83781d_init_device(struct device *dev)
1da177e4 1352{
7666c13c 1353 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4
LT		 1354 int i, p;
1355 int type = data->type;
1356 u8 tmp;
1357
aff6e00e
GR		 1358 if (reset && type != as99127f) { /*
1359 * this resets registers we don't have
1360 * documentation for on the as99127f
1361 */
1362 /*
1363 * Resetting the chip has been the default for a long time,
1364 * but it causes the BIOS initializations (fan clock dividers,
1365 * thermal sensor types...) to be lost, so it is now optional.
1366 * It might even go away if nobody reports it as being useful,
1367 * as I see very little reason why this would be needed at
1368 * all.
1369 */
b55f3757
GR		 1370 dev_info(dev,
1371 "If reset=1 solved a problem you were having, please report!\n");
fabddcd4 1372
1da177e4 1373 /* save these registers */
31b8dc4d
JD		 1374 i = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
1375 p = w83781d_read_value(data, W83781D_REG_PWMCLK12);
aff6e00e
GR		 1376 /*
1377 * Reset all except Watchdog values and last conversion values
1378 * This sets fan-divs to 2, among others
1379 */
31b8dc4d 1380 w83781d_write_value(data, W83781D_REG_CONFIG, 0x80);
aff6e00e
GR		 1381 /*
1382 * Restore the registers and disable power-on abnormal beep.
1383 * This saves FAN 1/2/3 input/output values set by BIOS.
1384 */
31b8dc4d
JD		 1385 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1386 w83781d_write_value(data, W83781D_REG_PWMCLK12, p);
c531eb3f
GR		 1387 /*
1388 * Disable master beep-enable (reset turns it on).
1389 * Individual beep_mask should be reset to off but for some
1390 * reason disabling this bit helps some people not get beeped
1391 */
31b8dc4d 1392 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1da177e4
LT		 1393 }
1394
aff6e00e
GR		 1395 /*
1396 * Disable power-on abnormal beep, as advised by the datasheet.
1397 * Already done if reset=1.
1398 */
fabddcd4 1399 if (init && !reset && type != as99127f) {
31b8dc4d
JD		 1400 i = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
1401 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
fabddcd4
JD		 1402 }
1403
303760b4 1404 data->vrm = vid_which_vrm();
1da177e4
LT		 1405
1406 if ((type != w83781d) && (type != as99127f)) {
31b8dc4d 1407 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
1da177e4
LT		 1408 for (i = 1; i <= 3; i++) {
1409 if (!(tmp & BIT_SCFG1[i - 1])) {
b26f9330 1410 data->sens[i - 1] = 4;
1da177e4
LT		 1411 } else {
1412 if (w83781d_read_value
31b8dc4d 1413 (data,
1da177e4
LT		 1414 W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1415 data->sens[i - 1] = 1;
1416 else
1417 data->sens[i - 1] = 2;
1418 }
7c7a5304 1419 if (type == w83783s && i == 2)
1da177e4
LT		 1420 break;
1421 }
1422 }
1423
1424 if (init && type != as99127f) {
1425 /* Enable temp2 */
31b8dc4d 1426 tmp = w83781d_read_value(data, W83781D_REG_TEMP2_CONFIG);
1da177e4 1427 if (tmp & 0x01) {
b55f3757
GR		 1428 dev_warn(dev,
1429 "Enabling temp2, readings might not make sense\n");
31b8dc4d 1430 w83781d_write_value(data, W83781D_REG_TEMP2_CONFIG,
1da177e4
LT		 1431 tmp & 0xfe);
1432 }
1433
1434 /* Enable temp3 */
7c7a5304 1435 if (type != w83783s) {
31b8dc4d 1436 tmp = w83781d_read_value(data,
1da177e4
LT		 1437 W83781D_REG_TEMP3_CONFIG);
1438 if (tmp & 0x01) {
b55f3757
GR		 1439 dev_warn(dev,
1440 "Enabling temp3, readings might not make sense\n");
31b8dc4d 1441 w83781d_write_value(data,
1da177e4
LT		 1442 W83781D_REG_TEMP3_CONFIG, tmp & 0xfe);
1443 }
1444 }
1da177e4
LT		 1445 }
1446
1447 /* Start monitoring */
31b8dc4d
JD		 1448 w83781d_write_value(data, W83781D_REG_CONFIG,
1449 (w83781d_read_value(data,
1da177e4
LT		 1450 W83781D_REG_CONFIG) & 0xf7)
1451 | 0x01);
7666c13c
JD		 1452
1453 /* A few vars need to be filled upon startup */
34875337
JD		 1454 for (i = 0; i < 3; i++) {
1455 data->fan_min[i] = w83781d_read_value(data,
7666c13c
JD		 1456 W83781D_REG_FAN_MIN(i));
1457 }
7666c13c
JD		 1458
1459 mutex_init(&data->update_lock);
1da177e4
LT		 1460}
1461
1462static struct w83781d_data *w83781d_update_device(struct device *dev)
1463{
7666c13c 1464 struct w83781d_data *data = dev_get_drvdata(dev);
0217eae3 1465 struct i2c_client *client = data->client;
1da177e4
LT		 1466 int i;
1467
9a61bf63 1468 mutex_lock(&data->update_lock);
1da177e4
LT		 1469
1470 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1471 || !data->valid) {
1472 dev_dbg(dev, "Starting device update\n");
1473
1474 for (i = 0; i <= 8; i++) {
7c7a5304 1475 if (data->type == w83783s && i == 1)
1da177e4
LT		 1476 continue; /* 783S has no in1 */
1477 data->in[i] =
31b8dc4d 1478 w83781d_read_value(data, W83781D_REG_IN(i));
1da177e4 1479 data->in_min[i] =
31b8dc4d 1480 w83781d_read_value(data, W83781D_REG_IN_MIN(i));
1da177e4 1481 data->in_max[i] =
31b8dc4d 1482 w83781d_read_value(data, W83781D_REG_IN_MAX(i));
05663368 1483 if ((data->type != w83782d) && (i == 6))
1da177e4
LT		 1484 break;
1485 }
34875337
JD		 1486 for (i = 0; i < 3; i++) {
1487 data->fan[i] =
31b8dc4d 1488 w83781d_read_value(data, W83781D_REG_FAN(i));
34875337 1489 data->fan_min[i] =
31b8dc4d 1490 w83781d_read_value(data, W83781D_REG_FAN_MIN(i));
1da177e4
LT		 1491 }
1492 if (data->type != w83781d && data->type != as99127f) {
34875337
JD		 1493 for (i = 0; i < 4; i++) {
1494 data->pwm[i] =
31b8dc4d 1495 w83781d_read_value(data,
34875337 1496 W83781D_REG_PWM[i]);
848ddf11
JD		 1497 /* Only W83782D on SMBus has PWM3 and PWM4 */
1498 if ((data->type != w83782d || !client)
34875337 1499 && i == 1)
1da177e4
LT		 1500 break;
1501 }
1502 /* Only PWM2 can be disabled */
34875337 1503 data->pwm2_enable = (w83781d_read_value(data,
c531eb3f 1504 W83781D_REG_PWMCLK12) & 0x08) >> 3;
1da177e4
LT		 1505 }
1506
31b8dc4d 1507 data->temp = w83781d_read_value(data, W83781D_REG_TEMP(1));
1da177e4 1508 data->temp_max =
31b8dc4d 1509 w83781d_read_value(data, W83781D_REG_TEMP_OVER(1));
1da177e4 1510 data->temp_max_hyst =
31b8dc4d 1511 w83781d_read_value(data, W83781D_REG_TEMP_HYST(1));
1da177e4 1512 data->temp_add[0] =
31b8dc4d 1513 w83781d_read_value(data, W83781D_REG_TEMP(2));
1da177e4 1514 data->temp_max_add[0] =
31b8dc4d 1515 w83781d_read_value(data, W83781D_REG_TEMP_OVER(2));
1da177e4 1516 data->temp_max_hyst_add[0] =
31b8dc4d 1517 w83781d_read_value(data, W83781D_REG_TEMP_HYST(2));
7c7a5304 1518 if (data->type != w83783s) {
1da177e4 1519 data->temp_add[1] =
31b8dc4d 1520 w83781d_read_value(data, W83781D_REG_TEMP(3));
1da177e4 1521 data->temp_max_add[1] =
31b8dc4d 1522 w83781d_read_value(data,
1da177e4
LT		 1523 W83781D_REG_TEMP_OVER(3));
1524 data->temp_max_hyst_add[1] =
31b8dc4d 1525 w83781d_read_value(data,
1da177e4
LT		 1526 W83781D_REG_TEMP_HYST(3));
1527 }
31b8dc4d 1528 i = w83781d_read_value(data, W83781D_REG_VID_FANDIV);
7c7a5304 1529 data->vid = i & 0x0f;
31b8dc4d 1530 data->vid |= (w83781d_read_value(data,
7c7a5304 1531 W83781D_REG_CHIPID) & 0x01) << 4;
1da177e4
LT		 1532 data->fan_div[0] = (i >> 4) & 0x03;
1533 data->fan_div[1] = (i >> 6) & 0x03;
31b8dc4d 1534 data->fan_div[2] = (w83781d_read_value(data,
7c7a5304 1535 W83781D_REG_PIN) >> 6) & 0x03;
1da177e4 1536 if ((data->type != w83781d) && (data->type != as99127f)) {
31b8dc4d 1537 i = w83781d_read_value(data, W83781D_REG_VBAT);
1da177e4
LT		 1538 data->fan_div[0] |= (i >> 3) & 0x04;
1539 data->fan_div[1] |= (i >> 4) & 0x04;
7c7a5304 1540 data->fan_div[2] |= (i >> 5) & 0x04;
1da177e4 1541 }
05663368 1542 if (data->type == w83782d) {
31b8dc4d 1543 data->alarms = w83781d_read_value(data,
c7f5d7ed 1544 W83782D_REG_ALARM1)
31b8dc4d 1545 | (w83781d_read_value(data,
c7f5d7ed 1546 W83782D_REG_ALARM2) << 8)
31b8dc4d 1547 | (w83781d_read_value(data,
c7f5d7ed
JD		 1548 W83782D_REG_ALARM3) << 16);
1549 } else if (data->type == w83783s) {
31b8dc4d 1550 data->alarms = w83781d_read_value(data,
c7f5d7ed 1551 W83782D_REG_ALARM1)
31b8dc4d 1552 | (w83781d_read_value(data,
c7f5d7ed
JD		 1553 W83782D_REG_ALARM2) << 8);
1554 } else {
aff6e00e
GR		 1555 /*
1556 * No real-time status registers, fall back to
1557 * interrupt status registers
1558 */
31b8dc4d 1559 data->alarms = w83781d_read_value(data,
c7f5d7ed 1560 W83781D_REG_ALARM1)
31b8dc4d 1561 | (w83781d_read_value(data,
c7f5d7ed 1562 W83781D_REG_ALARM2) << 8);
1da177e4 1563 }
31b8dc4d 1564 i = w83781d_read_value(data, W83781D_REG_BEEP_INTS2);
2fbbbf14 1565 data->beep_mask = (i << 8) +
31b8dc4d 1566 w83781d_read_value(data, W83781D_REG_BEEP_INTS1);
1da177e4
LT		 1567 if ((data->type != w83781d) && (data->type != as99127f)) {
1568 data->beep_mask |=
31b8dc4d 1569 w83781d_read_value(data,
1da177e4
LT		 1570 W83781D_REG_BEEP_INTS3) << 16;
1571 }
1572 data->last_updated = jiffies;
1573 data->valid = 1;
1574 }
1575
9a61bf63 1576 mutex_unlock(&data->update_lock);
1da177e4
LT		 1577
1578 return data;
1579}
1580
0217eae3
WG		 1581static const struct i2c_device_id w83781d_ids[] = {
1582 { "w83781d", w83781d, },
1583 { "w83782d", w83782d, },
1584 { "w83783s", w83783s, },
1585 { "as99127f", as99127f },
1586 { /* LIST END */ }
1587};
1588MODULE_DEVICE_TABLE(i2c, w83781d_ids);
1589
1590static struct i2c_driver w83781d_driver = {
1591 .class = I2C_CLASS_HWMON,
1592 .driver = {
1593 .name = "w83781d",
1594 },
1595 .probe = w83781d_probe,
1596 .remove = w83781d_remove,
1597 .id_table = w83781d_ids,
1598 .detect = w83781d_detect,
c3813d6a 1599 .address_list = normal_i2c,
0217eae3
WG		 1600};
1601
1602/*
1603 * ISA related code
1604 */
443850ce
WG		 1605#ifdef CONFIG_ISA
1606
1607/* ISA device, if found */
1608static struct platform_device *pdev;
1609
1610static unsigned short isa_address = 0x290;
1611
aff6e00e
GR		 1612/*
1613 * I2C devices get this name attribute automatically, but for ISA devices
1614 * we must create it by ourselves.
1615 */
443850ce 1616static ssize_t
b80b814b 1617name_show(struct device *dev, struct device_attribute *devattr, char *buf)
443850ce
WG		 1618{
1619 struct w83781d_data *data = dev_get_drvdata(dev);
360782dd 1620 return sprintf(buf, "%s\n", data->name);
443850ce 1621}
b80b814b 1622static DEVICE_ATTR_RO(name);
443850ce
WG		 1623
1624static struct w83781d_data *w83781d_data_if_isa(void)
1625{
1626 return pdev ? platform_get_drvdata(pdev) : NULL;
1627}
1628
1629/* Returns 1 if the I2C chip appears to be an alias of the ISA chip */
1630static int w83781d_alias_detect(struct i2c_client *client, u8 chipid)
1631{
0217eae3 1632 struct w83781d_data *isa;
443850ce
WG		 1633 int i;
1634
1635 if (!pdev) /* No ISA chip */
1636 return 0;
1637
443850ce
WG		 1638 isa = platform_get_drvdata(pdev);
1639
1640 if (w83781d_read_value(isa, W83781D_REG_I2C_ADDR) != client->addr)
1641 return 0; /* Address doesn't match */
1642 if (w83781d_read_value(isa, W83781D_REG_WCHIPID) != chipid)
1643 return 0; /* Chip type doesn't match */
1644
aff6e00e
GR		 1645 /*
1646 * We compare all the limit registers, the config register and the
1647 * interrupt mask registers
1648 */
443850ce 1649 for (i = 0x2b; i <= 0x3d; i++) {
0217eae3
WG		 1650 if (w83781d_read_value(isa, i) !=
1651 i2c_smbus_read_byte_data(client, i))
443850ce
WG		 1652 return 0;
1653 }
1654 if (w83781d_read_value(isa, W83781D_REG_CONFIG) !=
0217eae3 1655 i2c_smbus_read_byte_data(client, W83781D_REG_CONFIG))
443850ce
WG		 1656 return 0;
1657 for (i = 0x43; i <= 0x46; i++) {
0217eae3
WG		 1658 if (w83781d_read_value(isa, i) !=
1659 i2c_smbus_read_byte_data(client, i))
443850ce
WG		 1660 return 0;
1661 }
1662
1663 return 1;
1664}
1665
1666static int
1667w83781d_read_value_isa(struct w83781d_data *data, u16 reg)
1668{
443850ce
WG		 1669 int word_sized, res;
1670
1671 word_sized = (((reg & 0xff00) == 0x100)
1672 || ((reg & 0xff00) == 0x200))
1673 && (((reg & 0x00ff) == 0x50)
1674 || ((reg & 0x00ff) == 0x53)
1675 || ((reg & 0x00ff) == 0x55));
1676 if (reg & 0xff00) {
1677 outb_p(W83781D_REG_BANK,
360782dd 1678 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1679 outb_p(reg >> 8,
360782dd 1680 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1681 }
360782dd
JD		 1682 outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET);
1683 res = inb_p(data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1684 if (word_sized) {
1685 outb_p((reg & 0xff) + 1,
360782dd 1686 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1687 res =
360782dd 1688 (res << 8) + inb_p(data->isa_addr +
443850ce
WG		 1689 W83781D_DATA_REG_OFFSET);
1690 }
1691 if (reg & 0xff00) {
1692 outb_p(W83781D_REG_BANK,
360782dd
JD		 1693 data->isa_addr + W83781D_ADDR_REG_OFFSET);
1694 outb_p(0, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1695 }
1696 return res;
1697}
1698
1699static void
1700w83781d_write_value_isa(struct w83781d_data *data, u16 reg, u16 value)
1701{
443850ce
WG		 1702 int word_sized;
1703
1704 word_sized = (((reg & 0xff00) == 0x100)
1705 || ((reg & 0xff00) == 0x200))
1706 && (((reg & 0x00ff) == 0x53)
1707 || ((reg & 0x00ff) == 0x55));
1708 if (reg & 0xff00) {
1709 outb_p(W83781D_REG_BANK,
360782dd 1710 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1711 outb_p(reg >> 8,
360782dd 1712 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1713 }
360782dd 1714 outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce
WG		 1715 if (word_sized) {
1716 outb_p(value >> 8,
360782dd 1717 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1718 outb_p((reg & 0xff) + 1,
360782dd 1719 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1720 }
360782dd 1721 outb_p(value & 0xff, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1722 if (reg & 0xff00) {
1723 outb_p(W83781D_REG_BANK,
360782dd
JD		 1724 data->isa_addr + W83781D_ADDR_REG_OFFSET);
1725 outb_p(0, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1726 }
1727}
1728
aff6e00e
GR		 1729/*
1730 * The SMBus locks itself, usually, but nothing may access the Winbond between
1731 * bank switches. ISA access must always be locked explicitly!
1732 * We ignore the W83781D BUSY flag at this moment - it could lead to deadlocks,
1733 * would slow down the W83781D access and should not be necessary.
1734 * There are some ugly typecasts here, but the good news is - they should
1735 * nowhere else be necessary!
1736 */
443850ce
WG		 1737static int
1738w83781d_read_value(struct w83781d_data *data, u16 reg)
1739{
0217eae3 1740 struct i2c_client *client = data->client;
443850ce
WG		 1741 int res;
1742
1743 mutex_lock(&data->lock);
0217eae3 1744 if (client)
443850ce
WG		 1745 res = w83781d_read_value_i2c(data, reg);
1746 else
1747 res = w83781d_read_value_isa(data, reg);
1748 mutex_unlock(&data->lock);
1749 return res;
1750}
1751
1752static int
1753w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
1754{
0217eae3 1755 struct i2c_client *client = data->client;
443850ce
WG		 1756
1757 mutex_lock(&data->lock);
0217eae3 1758 if (client)
443850ce
WG		 1759 w83781d_write_value_i2c(data, reg, value);
1760 else
1761 w83781d_write_value_isa(data, reg, value);
1762 mutex_unlock(&data->lock);
1763 return 0;
1764}
1765
6c931ae1 1766static int
443850ce
WG		 1767w83781d_isa_probe(struct platform_device *pdev)
1768{
1769 int err, reg;
1770 struct w83781d_data *data;
1771 struct resource *res;
443850ce
WG		 1772
1773 /* Reserve the ISA region */
1774 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
144d2b99
GR		 1775 if (!devm_request_region(&pdev->dev,
1776 res->start + W83781D_ADDR_REG_OFFSET, 2,
1777 "w83781d"))
1778 return -EBUSY;
1779
1780 data = devm_kzalloc(&pdev->dev, sizeof(struct w83781d_data),
1781 GFP_KERNEL);
1782 if (!data)
1783 return -ENOMEM;
443850ce 1784
443850ce 1785 mutex_init(&data->lock);
360782dd 1786 data->isa_addr = res->start;
443850ce
WG		 1787 platform_set_drvdata(pdev, data);
1788
1789 reg = w83781d_read_value(data, W83781D_REG_WCHIPID);
1790 switch (reg) {
1791 case 0x30:
1792 data->type = w83782d;
360782dd 1793 data->name = "w83782d";
443850ce
WG		 1794 break;
1795 default:
1796 data->type = w83781d;
360782dd 1797 data->name = "w83781d";
443850ce 1798 }
443850ce
WG		 1799
1800 /* Initialize the W83781D chip */
1801 w83781d_init_device(&pdev->dev);
1802
1803 /* Register sysfs hooks */
1804 err = w83781d_create_files(&pdev->dev, data->type, 1);
1805 if (err)
1806 goto exit_remove_files;
1807
1808 err = device_create_file(&pdev->dev, &dev_attr_name);
1809 if (err)
1810 goto exit_remove_files;
1811
1812 data->hwmon_dev = hwmon_device_register(&pdev->dev);
1813 if (IS_ERR(data->hwmon_dev)) {
1814 err = PTR_ERR(data->hwmon_dev);
1815 goto exit_remove_files;
1816 }
1817
1818 return 0;
1819
1820 exit_remove_files:
79501333 1821 w83781d_remove_files(&pdev->dev);
443850ce 1822 device_remove_file(&pdev->dev, &dev_attr_name);
443850ce
WG		 1823 return err;
1824}
1825
281dfd0b 1826static int
443850ce
WG		 1827w83781d_isa_remove(struct platform_device *pdev)
1828{
1829 struct w83781d_data *data = platform_get_drvdata(pdev);
1830
1831 hwmon_device_unregister(data->hwmon_dev);
79501333 1832 w83781d_remove_files(&pdev->dev);
443850ce 1833 device_remove_file(&pdev->dev, &dev_attr_name);
443850ce
WG		 1834
1835 return 0;
1836}
1837
1838static struct platform_driver w83781d_isa_driver = {
1839 .driver = {
443850ce
WG		 1840 .name = "w83781d",
1841 },
1842 .probe = w83781d_isa_probe,
9e5e9b7a 1843 .remove = w83781d_isa_remove,
443850ce
WG		 1844};
1845
7666c13c
JD		 1846/* return 1 if a supported chip is found, 0 otherwise */
1847static int __init
1848w83781d_isa_found(unsigned short address)
1849{
1850 int val, save, found = 0;
b0bcdd3c
JD		 1851 int port;
1852
aff6e00e
GR		 1853 /*
1854 * Some boards declare base+0 to base+7 as a PNP device, some base+4
b0bcdd3c 1855 * to base+7 and some base+5 to base+6. So we better request each port
aff6e00e
GR		 1856 * individually for the probing phase.
1857 */
b0bcdd3c
JD		 1858 for (port = address; port < address + W83781D_EXTENT; port++) {
1859 if (!request_region(port, 1, "w83781d")) {
1ca28218 1860 pr_debug("Failed to request port 0x%x\n", port);
b0bcdd3c
JD		 1861 goto release;
1862 }
2961cb22 1863 }
7666c13c
JD		 1864
1865#define REALLY_SLOW_IO
aff6e00e
GR		 1866 /*
1867 * We need the timeouts for at least some W83781D-like
1868 * chips. But only if we read 'undefined' registers.
1869 */
7666c13c
JD		 1870 val = inb_p(address + 1);
1871 if (inb_p(address + 2) != val
1872 || inb_p(address + 3) != val
1873 || inb_p(address + 7) != val) {
1ca28218 1874 pr_debug("Detection failed at step %d\n", 1);
7666c13c
JD		 1875 goto release;
1876 }
1877#undef REALLY_SLOW_IO
1878
aff6e00e
GR		 1879 /*
1880 * We should be able to change the 7 LSB of the address port. The
1881 * MSB (busy flag) should be clear initially, set after the write.
1882 */
7666c13c
JD		 1883 save = inb_p(address + W83781D_ADDR_REG_OFFSET);
1884 if (save & 0x80) {
1ca28218 1885 pr_debug("Detection failed at step %d\n", 2);
7666c13c
JD		 1886 goto release;
1887 }
1888 val = ~save & 0x7f;
1889 outb_p(val, address + W83781D_ADDR_REG_OFFSET);
1890 if (inb_p(address + W83781D_ADDR_REG_OFFSET) != (val | 0x80)) {
1891 outb_p(save, address + W83781D_ADDR_REG_OFFSET);
1ca28218 1892 pr_debug("Detection failed at step %d\n", 3);
7666c13c
JD		 1893 goto release;
1894 }
1895
1896 /* We found a device, now see if it could be a W83781D */
1897 outb_p(W83781D_REG_CONFIG, address + W83781D_ADDR_REG_OFFSET);
1898 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1899 if (val & 0x80) {
1ca28218 1900 pr_debug("Detection failed at step %d\n", 4);
7666c13c
JD		 1901 goto release;
1902 }
1903 outb_p(W83781D_REG_BANK, address + W83781D_ADDR_REG_OFFSET);
1904 save = inb_p(address + W83781D_DATA_REG_OFFSET);
1905 outb_p(W83781D_REG_CHIPMAN, address + W83781D_ADDR_REG_OFFSET);
1906 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1907 if ((!(save & 0x80) && (val != 0xa3))
1908 || ((save & 0x80) && (val != 0x5c))) {
1ca28218 1909 pr_debug("Detection failed at step %d\n", 5);
7666c13c
JD		 1910 goto release;
1911 }
1912 outb_p(W83781D_REG_I2C_ADDR, address + W83781D_ADDR_REG_OFFSET);
1913 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1914 if (val < 0x03 || val > 0x77) { /* Not a valid I2C address */
1ca28218 1915 pr_debug("Detection failed at step %d\n", 6);
7666c13c
JD		 1916 goto release;
1917 }
1918
1919 /* The busy flag should be clear again */
1920 if (inb_p(address + W83781D_ADDR_REG_OFFSET) & 0x80) {
1ca28218 1921 pr_debug("Detection failed at step %d\n", 7);
7666c13c
JD		 1922 goto release;
1923 }
1924
1925 /* Determine the chip type */
1926 outb_p(W83781D_REG_BANK, address + W83781D_ADDR_REG_OFFSET);
1927 save = inb_p(address + W83781D_DATA_REG_OFFSET);
1928 outb_p(save & 0xf8, address + W83781D_DATA_REG_OFFSET);
1929 outb_p(W83781D_REG_WCHIPID, address + W83781D_ADDR_REG_OFFSET);
1930 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1931 if ((val & 0xfe) == 0x10 /* W83781D */
05663368 1932 || val == 0x30) /* W83782D */
7666c13c
JD		 1933 found = 1;
1934
1935 if (found)
1ca28218 1936 pr_info("Found a %s chip at %#x\n",
7666c13c
JD		 1937 val == 0x30 ? "W83782D" : "W83781D", (int)address);
1938
1939 release:
b0bcdd3c
JD		 1940 for (port--; port >= address; port--)
1941 release_region(port, 1);
7666c13c
JD		 1942 return found;
1943}
1944
1945static int __init
1946w83781d_isa_device_add(unsigned short address)
1947{
1948 struct resource res = {
1949 .start = address,
15bde2f1 1950 .end = address + W83781D_EXTENT - 1,
7666c13c
JD		 1951 .name = "w83781d",
1952 .flags = IORESOURCE_IO,
1953 };
1954 int err;
1955
1956 pdev = platform_device_alloc("w83781d", address);
1957 if (!pdev) {
1958 err = -ENOMEM;
1ca28218 1959 pr_err("Device allocation failed\n");
7666c13c
JD		 1960 goto exit;
1961 }
1962
1963 err = platform_device_add_resources(pdev, &res, 1);
1964 if (err) {
1ca28218 1965 pr_err("Device resource addition failed (%d)\n", err);
7666c13c
JD		 1966 goto exit_device_put;
1967 }
1968
1969 err = platform_device_add(pdev);
1970 if (err) {
1ca28218 1971 pr_err("Device addition failed (%d)\n", err);
7666c13c
JD		 1972 goto exit_device_put;
1973 }
1974
1975 return 0;
1976
1977 exit_device_put:
1978 platform_device_put(pdev);
1979 exit:
1980 pdev = NULL;
1981 return err;
1982}
1983
1da177e4 1984static int __init
443850ce 1985w83781d_isa_register(void)
1da177e4 1986{
fde09509
JD		 1987 int res;
1988
7666c13c
JD		 1989 if (w83781d_isa_found(isa_address)) {
1990 res = platform_driver_register(&w83781d_isa_driver);
1991 if (res)
c6566206 1992 goto exit;
fde09509 1993
7666c13c
JD		 1994 /* Sets global pdev as a side effect */
1995 res = w83781d_isa_device_add(isa_address);
1996 if (res)
1997 goto exit_unreg_isa_driver;
1998 }
fde09509
JD		 1999
2000 return 0;
7666c13c 2001
443850ce 2002exit_unreg_isa_driver:
7666c13c 2003 platform_driver_unregister(&w83781d_isa_driver);
443850ce 2004exit:
7666c13c 2005 return res;
1da177e4
LT		 2006}
2007
dd56b638 2008static void
443850ce 2009w83781d_isa_unregister(void)
1da177e4 2010{
7666c13c
JD		 2011 if (pdev) {
2012 platform_device_unregister(pdev);
2013 platform_driver_unregister(&w83781d_isa_driver);
2014 }
443850ce
WG		 2015}
2016#else /* !CONFIG_ISA */
2017
2018static struct w83781d_data *w83781d_data_if_isa(void)
2019{
2020 return NULL;
2021}
2022
2023static int
2024w83781d_alias_detect(struct i2c_client *client, u8 chipid)
2025{
2026 return 0;
2027}
2028
2029static int
2030w83781d_read_value(struct w83781d_data *data, u16 reg)
2031{
2032 int res;
2033
2034 mutex_lock(&data->lock);
2035 res = w83781d_read_value_i2c(data, reg);
2036 mutex_unlock(&data->lock);
2037
2038 return res;
2039}
2040
2041static int
2042w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
2043{
2044 mutex_lock(&data->lock);
2045 w83781d_write_value_i2c(data, reg, value);
2046 mutex_unlock(&data->lock);
2047
2048 return 0;
2049}
2050
2051static int __init
2052w83781d_isa_register(void)
2053{
2054 return 0;
2055}
2056
dd56b638 2057static void
443850ce
WG		 2058w83781d_isa_unregister(void)
2059{
2060}
2061#endif /* CONFIG_ISA */
2062
2063static int __init
2064sensors_w83781d_init(void)
2065{
2066 int res;
2067
aff6e00e
GR		 2068 /*
2069 * We register the ISA device first, so that we can skip the
2070 * registration of an I2C interface to the same device.
2071 */
443850ce
WG		 2072 res = w83781d_isa_register();
2073 if (res)
2074 goto exit;
2075
2076 res = i2c_add_driver(&w83781d_driver);
2077 if (res)
2078 goto exit_unreg_isa;
2079
2080 return 0;
2081
2082 exit_unreg_isa:
2083 w83781d_isa_unregister();
2084 exit:
2085 return res;
2086}
2087
2088static void __exit
2089sensors_w83781d_exit(void)
2090{
2091 w83781d_isa_unregister();
1da177e4
LT		 2092 i2c_del_driver(&w83781d_driver);
2093}
2094
2095MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
2096 "Philip Edelbrock <phil@netroedge.com>, "
2097 "and Mark Studebaker <mdsxyz123@yahoo.com>");
2098MODULE_DESCRIPTION("W83781D driver");
2099MODULE_LICENSE("GPL");
2100
2101module_init(sensors_w83781d_init);
2102module_exit(sensors_w83781d_exit);
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