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70ba4cc2 SQ |
1 | /* |
2 | * OMAP hardware spinlock driver | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Contact: Simon Que <sque@ti.com> | |
7 | * Hari Kanigeri <h-kanigeri2@ti.com> | |
8 | * Ohad Ben-Cohen <ohad@wizery.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * version 2 as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/hwspinlock.h> | |
30 | #include <linux/platform_device.h> | |
31 | ||
32 | #include "hwspinlock_internal.h" | |
33 | ||
34 | /* Spinlock register offsets */ | |
35 | #define SYSSTATUS_OFFSET 0x0014 | |
36 | #define LOCK_BASE_OFFSET 0x0800 | |
37 | ||
38 | #define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) | |
39 | ||
40 | /* Possible values of SPINLOCK_LOCK_REG */ | |
41 | #define SPINLOCK_NOTTAKEN (0) /* free */ | |
42 | #define SPINLOCK_TAKEN (1) /* locked */ | |
43 | ||
70ba4cc2 SQ |
44 | static int omap_hwspinlock_trylock(struct hwspinlock *lock) |
45 | { | |
300bab97 | 46 | void __iomem *lock_addr = lock->priv; |
70ba4cc2 SQ |
47 | |
48 | /* attempt to acquire the lock by reading its value */ | |
300bab97 | 49 | return (SPINLOCK_NOTTAKEN == readl(lock_addr)); |
70ba4cc2 SQ |
50 | } |
51 | ||
52 | static void omap_hwspinlock_unlock(struct hwspinlock *lock) | |
53 | { | |
300bab97 | 54 | void __iomem *lock_addr = lock->priv; |
70ba4cc2 SQ |
55 | |
56 | /* release the lock by writing 0 to it */ | |
300bab97 | 57 | writel(SPINLOCK_NOTTAKEN, lock_addr); |
70ba4cc2 SQ |
58 | } |
59 | ||
60 | /* | |
61 | * relax the OMAP interconnect while spinning on it. | |
62 | * | |
63 | * The specs recommended that the retry delay time will be | |
64 | * just over half of the time that a requester would be | |
65 | * expected to hold the lock. | |
66 | * | |
67 | * The number below is taken from an hardware specs example, | |
68 | * obviously it is somewhat arbitrary. | |
69 | */ | |
70 | static void omap_hwspinlock_relax(struct hwspinlock *lock) | |
71 | { | |
72 | ndelay(50); | |
73 | } | |
74 | ||
75 | static const struct hwspinlock_ops omap_hwspinlock_ops = { | |
76 | .trylock = omap_hwspinlock_trylock, | |
77 | .unlock = omap_hwspinlock_unlock, | |
78 | .relax = omap_hwspinlock_relax, | |
79 | }; | |
80 | ||
57129106 | 81 | static int omap_hwspinlock_probe(struct platform_device *pdev) |
70ba4cc2 | 82 | { |
c3c1250e | 83 | struct hwspinlock_pdata *pdata = pdev->dev.platform_data; |
300bab97 OBC |
84 | struct hwspinlock_device *bank; |
85 | struct hwspinlock *hwlock; | |
70ba4cc2 SQ |
86 | struct resource *res; |
87 | void __iomem *io_base; | |
300bab97 | 88 | int num_locks, i, ret; |
70ba4cc2 | 89 | |
c3c1250e OBC |
90 | if (!pdata) |
91 | return -ENODEV; | |
92 | ||
70ba4cc2 SQ |
93 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
94 | if (!res) | |
95 | return -ENODEV; | |
96 | ||
70ba4cc2 | 97 | io_base = ioremap(res->start, resource_size(res)); |
c97f6dd0 OBC |
98 | if (!io_base) |
99 | return -ENOMEM; | |
70ba4cc2 SQ |
100 | |
101 | /* Determine number of locks */ | |
102 | i = readl(io_base + SYSSTATUS_OFFSET); | |
103 | i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; | |
104 | ||
105 | /* one of the four lsb's must be set, and nothing else */ | |
106 | if (hweight_long(i & 0xf) != 1 || i > 8) { | |
107 | ret = -EINVAL; | |
108 | goto iounmap_base; | |
109 | } | |
110 | ||
300bab97 | 111 | num_locks = i * 32; /* actual number of locks in this device */ |
c97f6dd0 | 112 | |
300bab97 OBC |
113 | bank = kzalloc(sizeof(*bank) + num_locks * sizeof(*hwlock), GFP_KERNEL); |
114 | if (!bank) { | |
c97f6dd0 OBC |
115 | ret = -ENOMEM; |
116 | goto iounmap_base; | |
117 | } | |
118 | ||
300bab97 | 119 | platform_set_drvdata(pdev, bank); |
70ba4cc2 | 120 | |
300bab97 OBC |
121 | for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) |
122 | hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; | |
70ba4cc2 SQ |
123 | |
124 | /* | |
125 | * runtime PM will make sure the clock of this module is | |
126 | * enabled iff at least one lock is requested | |
127 | */ | |
128 | pm_runtime_enable(&pdev->dev); | |
129 | ||
300bab97 OBC |
130 | ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops, |
131 | pdata->base_id, num_locks); | |
132 | if (ret) | |
133 | goto reg_fail; | |
70ba4cc2 SQ |
134 | |
135 | return 0; | |
136 | ||
300bab97 | 137 | reg_fail: |
70ba4cc2 | 138 | pm_runtime_disable(&pdev->dev); |
300bab97 | 139 | kfree(bank); |
70ba4cc2 SQ |
140 | iounmap_base: |
141 | iounmap(io_base); | |
70ba4cc2 SQ |
142 | return ret; |
143 | } | |
144 | ||
e533a349 | 145 | static int omap_hwspinlock_remove(struct platform_device *pdev) |
70ba4cc2 | 146 | { |
300bab97 OBC |
147 | struct hwspinlock_device *bank = platform_get_drvdata(pdev); |
148 | void __iomem *io_base = bank->lock[0].priv - LOCK_BASE_OFFSET; | |
149 | int ret; | |
150 | ||
151 | ret = hwspin_lock_unregister(bank); | |
152 | if (ret) { | |
153 | dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); | |
154 | return ret; | |
70ba4cc2 SQ |
155 | } |
156 | ||
157 | pm_runtime_disable(&pdev->dev); | |
300bab97 OBC |
158 | iounmap(io_base); |
159 | kfree(bank); | |
70ba4cc2 SQ |
160 | |
161 | return 0; | |
162 | } | |
163 | ||
164 | static struct platform_driver omap_hwspinlock_driver = { | |
165 | .probe = omap_hwspinlock_probe, | |
9eb26bdd | 166 | .remove = omap_hwspinlock_remove, |
70ba4cc2 SQ |
167 | .driver = { |
168 | .name = "omap_hwspinlock", | |
e467b642 | 169 | .owner = THIS_MODULE, |
70ba4cc2 SQ |
170 | }, |
171 | }; | |
172 | ||
173 | static int __init omap_hwspinlock_init(void) | |
174 | { | |
175 | return platform_driver_register(&omap_hwspinlock_driver); | |
176 | } | |
177 | /* board init code might need to reserve hwspinlocks for predefined purposes */ | |
178 | postcore_initcall(omap_hwspinlock_init); | |
179 | ||
180 | static void __exit omap_hwspinlock_exit(void) | |
181 | { | |
182 | platform_driver_unregister(&omap_hwspinlock_driver); | |
183 | } | |
184 | module_exit(omap_hwspinlock_exit); | |
185 | ||
186 | MODULE_LICENSE("GPL v2"); | |
187 | MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); | |
188 | MODULE_AUTHOR("Simon Que <sque@ti.com>"); | |
189 | MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); | |
190 | MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); |