]>
Commit | Line | Data |
---|---|---|
357ace03 | 1 | // SPDX-License-Identifier: GPL-2.0 |
70ba4cc2 SQ |
2 | /* |
3 | * OMAP hardware spinlock driver | |
4 | * | |
b9ddb250 | 5 | * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com |
70ba4cc2 SQ |
6 | * |
7 | * Contact: Simon Que <sque@ti.com> | |
8 | * Hari Kanigeri <h-kanigeri2@ti.com> | |
9 | * Ohad Ben-Cohen <ohad@wizery.com> | |
b9ddb250 | 10 | * Suman Anna <s-anna@ti.com> |
70ba4cc2 SQ |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/bitops.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/hwspinlock.h> | |
65bd4341 | 23 | #include <linux/of.h> |
70ba4cc2 SQ |
24 | #include <linux/platform_device.h> |
25 | ||
26 | #include "hwspinlock_internal.h" | |
27 | ||
28 | /* Spinlock register offsets */ | |
29 | #define SYSSTATUS_OFFSET 0x0014 | |
30 | #define LOCK_BASE_OFFSET 0x0800 | |
31 | ||
32 | #define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) | |
33 | ||
34 | /* Possible values of SPINLOCK_LOCK_REG */ | |
35 | #define SPINLOCK_NOTTAKEN (0) /* free */ | |
36 | #define SPINLOCK_TAKEN (1) /* locked */ | |
37 | ||
70ba4cc2 SQ |
38 | static int omap_hwspinlock_trylock(struct hwspinlock *lock) |
39 | { | |
300bab97 | 40 | void __iomem *lock_addr = lock->priv; |
70ba4cc2 SQ |
41 | |
42 | /* attempt to acquire the lock by reading its value */ | |
300bab97 | 43 | return (SPINLOCK_NOTTAKEN == readl(lock_addr)); |
70ba4cc2 SQ |
44 | } |
45 | ||
46 | static void omap_hwspinlock_unlock(struct hwspinlock *lock) | |
47 | { | |
300bab97 | 48 | void __iomem *lock_addr = lock->priv; |
70ba4cc2 SQ |
49 | |
50 | /* release the lock by writing 0 to it */ | |
300bab97 | 51 | writel(SPINLOCK_NOTTAKEN, lock_addr); |
70ba4cc2 SQ |
52 | } |
53 | ||
54 | /* | |
55 | * relax the OMAP interconnect while spinning on it. | |
56 | * | |
57 | * The specs recommended that the retry delay time will be | |
58 | * just over half of the time that a requester would be | |
59 | * expected to hold the lock. | |
60 | * | |
61 | * The number below is taken from an hardware specs example, | |
62 | * obviously it is somewhat arbitrary. | |
63 | */ | |
64 | static void omap_hwspinlock_relax(struct hwspinlock *lock) | |
65 | { | |
66 | ndelay(50); | |
67 | } | |
68 | ||
69 | static const struct hwspinlock_ops omap_hwspinlock_ops = { | |
70 | .trylock = omap_hwspinlock_trylock, | |
71 | .unlock = omap_hwspinlock_unlock, | |
72 | .relax = omap_hwspinlock_relax, | |
73 | }; | |
74 | ||
57129106 | 75 | static int omap_hwspinlock_probe(struct platform_device *pdev) |
70ba4cc2 | 76 | { |
65bd4341 | 77 | struct device_node *node = pdev->dev.of_node; |
300bab97 OBC |
78 | struct hwspinlock_device *bank; |
79 | struct hwspinlock *hwlock; | |
70ba4cc2 | 80 | void __iomem *io_base; |
300bab97 | 81 | int num_locks, i, ret; |
65bd4341 SA |
82 | /* Only a single hwspinlock block device is supported */ |
83 | int base_id = 0; | |
70ba4cc2 | 84 | |
65bd4341 | 85 | if (!node) |
c3c1250e OBC |
86 | return -ENODEV; |
87 | ||
bf274006 BW |
88 | io_base = devm_platform_ioremap_resource(pdev, 0); |
89 | if (IS_ERR(io_base)) | |
90 | return PTR_ERR(io_base); | |
70ba4cc2 | 91 | |
e1e4528f SA |
92 | /* |
93 | * make sure the module is enabled and clocked before reading | |
94 | * the module SYSSTATUS register | |
95 | */ | |
96 | pm_runtime_enable(&pdev->dev); | |
97 | ret = pm_runtime_get_sync(&pdev->dev); | |
98 | if (ret < 0) { | |
99 | pm_runtime_put_noidle(&pdev->dev); | |
bf274006 | 100 | goto runtime_err; |
e1e4528f SA |
101 | } |
102 | ||
70ba4cc2 SQ |
103 | /* Determine number of locks */ |
104 | i = readl(io_base + SYSSTATUS_OFFSET); | |
105 | i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; | |
106 | ||
e1e4528f SA |
107 | /* |
108 | * runtime PM will make sure the clock of this module is | |
109 | * enabled again iff at least one lock is requested | |
110 | */ | |
111 | ret = pm_runtime_put(&pdev->dev); | |
112 | if (ret < 0) | |
bf274006 | 113 | goto runtime_err; |
e1e4528f | 114 | |
70ba4cc2 SQ |
115 | /* one of the four lsb's must be set, and nothing else */ |
116 | if (hweight_long(i & 0xf) != 1 || i > 8) { | |
117 | ret = -EINVAL; | |
bf274006 | 118 | goto runtime_err; |
70ba4cc2 SQ |
119 | } |
120 | ||
300bab97 | 121 | num_locks = i * 32; /* actual number of locks in this device */ |
c97f6dd0 | 122 | |
42f291eb BW |
123 | bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks), |
124 | GFP_KERNEL); | |
300bab97 | 125 | if (!bank) { |
c97f6dd0 | 126 | ret = -ENOMEM; |
bf274006 | 127 | goto runtime_err; |
c97f6dd0 OBC |
128 | } |
129 | ||
300bab97 | 130 | platform_set_drvdata(pdev, bank); |
70ba4cc2 | 131 | |
300bab97 OBC |
132 | for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) |
133 | hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; | |
70ba4cc2 | 134 | |
300bab97 | 135 | ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops, |
65bd4341 | 136 | base_id, num_locks); |
300bab97 | 137 | if (ret) |
42f291eb | 138 | goto runtime_err; |
70ba4cc2 | 139 | |
d4d98bba SA |
140 | dev_dbg(&pdev->dev, "Registered %d locks with HwSpinlock core\n", |
141 | num_locks); | |
142 | ||
70ba4cc2 SQ |
143 | return 0; |
144 | ||
bf274006 | 145 | runtime_err: |
e1e4528f | 146 | pm_runtime_disable(&pdev->dev); |
70ba4cc2 SQ |
147 | return ret; |
148 | } | |
149 | ||
e533a349 | 150 | static int omap_hwspinlock_remove(struct platform_device *pdev) |
70ba4cc2 | 151 | { |
300bab97 | 152 | struct hwspinlock_device *bank = platform_get_drvdata(pdev); |
300bab97 OBC |
153 | int ret; |
154 | ||
155 | ret = hwspin_lock_unregister(bank); | |
156 | if (ret) { | |
157 | dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); | |
158 | return ret; | |
70ba4cc2 SQ |
159 | } |
160 | ||
161 | pm_runtime_disable(&pdev->dev); | |
70ba4cc2 SQ |
162 | |
163 | return 0; | |
164 | } | |
165 | ||
65bd4341 SA |
166 | static const struct of_device_id omap_hwspinlock_of_match[] = { |
167 | { .compatible = "ti,omap4-hwspinlock", }, | |
b9ddb250 | 168 | { .compatible = "ti,am64-hwspinlock", }, |
6fa154e2 | 169 | { .compatible = "ti,am654-hwspinlock", }, |
65bd4341 SA |
170 | { /* end */ }, |
171 | }; | |
172 | MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match); | |
173 | ||
70ba4cc2 SQ |
174 | static struct platform_driver omap_hwspinlock_driver = { |
175 | .probe = omap_hwspinlock_probe, | |
9eb26bdd | 176 | .remove = omap_hwspinlock_remove, |
70ba4cc2 SQ |
177 | .driver = { |
178 | .name = "omap_hwspinlock", | |
65bd4341 | 179 | .of_match_table = of_match_ptr(omap_hwspinlock_of_match), |
70ba4cc2 SQ |
180 | }, |
181 | }; | |
182 | ||
183 | static int __init omap_hwspinlock_init(void) | |
184 | { | |
185 | return platform_driver_register(&omap_hwspinlock_driver); | |
186 | } | |
187 | /* board init code might need to reserve hwspinlocks for predefined purposes */ | |
188 | postcore_initcall(omap_hwspinlock_init); | |
189 | ||
190 | static void __exit omap_hwspinlock_exit(void) | |
191 | { | |
192 | platform_driver_unregister(&omap_hwspinlock_driver); | |
193 | } | |
194 | module_exit(omap_hwspinlock_exit); | |
195 | ||
196 | MODULE_LICENSE("GPL v2"); | |
197 | MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); | |
198 | MODULE_AUTHOR("Simon Que <sque@ti.com>"); | |
199 | MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); | |
200 | MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); |