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70ba4cc2 SQ |
1 | /* |
2 | * OMAP hardware spinlock driver | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Contact: Simon Que <sque@ti.com> | |
7 | * Hari Kanigeri <h-kanigeri2@ti.com> | |
8 | * Ohad Ben-Cohen <ohad@wizery.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * version 2 as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/hwspinlock.h> | |
30 | #include <linux/platform_device.h> | |
31 | ||
32 | #include "hwspinlock_internal.h" | |
33 | ||
34 | /* Spinlock register offsets */ | |
35 | #define SYSSTATUS_OFFSET 0x0014 | |
36 | #define LOCK_BASE_OFFSET 0x0800 | |
37 | ||
38 | #define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) | |
39 | ||
40 | /* Possible values of SPINLOCK_LOCK_REG */ | |
41 | #define SPINLOCK_NOTTAKEN (0) /* free */ | |
42 | #define SPINLOCK_TAKEN (1) /* locked */ | |
43 | ||
44 | #define to_omap_hwspinlock(lock) \ | |
45 | container_of(lock, struct omap_hwspinlock, lock) | |
46 | ||
47 | struct omap_hwspinlock { | |
48 | struct hwspinlock lock; | |
49 | void __iomem *addr; | |
50 | }; | |
51 | ||
52 | struct omap_hwspinlock_state { | |
53 | int num_locks; /* Total number of locks in system */ | |
54 | void __iomem *io_base; /* Mapped base address */ | |
c97f6dd0 | 55 | struct omap_hwspinlock lock[0]; /* Array of 'num_locks' locks */ |
70ba4cc2 SQ |
56 | }; |
57 | ||
58 | static int omap_hwspinlock_trylock(struct hwspinlock *lock) | |
59 | { | |
60 | struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); | |
61 | ||
62 | /* attempt to acquire the lock by reading its value */ | |
63 | return (SPINLOCK_NOTTAKEN == readl(omap_lock->addr)); | |
64 | } | |
65 | ||
66 | static void omap_hwspinlock_unlock(struct hwspinlock *lock) | |
67 | { | |
68 | struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); | |
69 | ||
70 | /* release the lock by writing 0 to it */ | |
71 | writel(SPINLOCK_NOTTAKEN, omap_lock->addr); | |
72 | } | |
73 | ||
74 | /* | |
75 | * relax the OMAP interconnect while spinning on it. | |
76 | * | |
77 | * The specs recommended that the retry delay time will be | |
78 | * just over half of the time that a requester would be | |
79 | * expected to hold the lock. | |
80 | * | |
81 | * The number below is taken from an hardware specs example, | |
82 | * obviously it is somewhat arbitrary. | |
83 | */ | |
84 | static void omap_hwspinlock_relax(struct hwspinlock *lock) | |
85 | { | |
86 | ndelay(50); | |
87 | } | |
88 | ||
89 | static const struct hwspinlock_ops omap_hwspinlock_ops = { | |
90 | .trylock = omap_hwspinlock_trylock, | |
91 | .unlock = omap_hwspinlock_unlock, | |
92 | .relax = omap_hwspinlock_relax, | |
93 | }; | |
94 | ||
95 | static int __devinit omap_hwspinlock_probe(struct platform_device *pdev) | |
96 | { | |
c3c1250e | 97 | struct hwspinlock_pdata *pdata = pdev->dev.platform_data; |
70ba4cc2 SQ |
98 | struct omap_hwspinlock *omap_lock; |
99 | struct omap_hwspinlock_state *state; | |
70ba4cc2 SQ |
100 | struct resource *res; |
101 | void __iomem *io_base; | |
102 | int i, ret; | |
103 | ||
c3c1250e OBC |
104 | if (!pdata) |
105 | return -ENODEV; | |
106 | ||
70ba4cc2 SQ |
107 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
108 | if (!res) | |
109 | return -ENODEV; | |
110 | ||
70ba4cc2 | 111 | io_base = ioremap(res->start, resource_size(res)); |
c97f6dd0 OBC |
112 | if (!io_base) |
113 | return -ENOMEM; | |
70ba4cc2 SQ |
114 | |
115 | /* Determine number of locks */ | |
116 | i = readl(io_base + SYSSTATUS_OFFSET); | |
117 | i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; | |
118 | ||
119 | /* one of the four lsb's must be set, and nothing else */ | |
120 | if (hweight_long(i & 0xf) != 1 || i > 8) { | |
121 | ret = -EINVAL; | |
122 | goto iounmap_base; | |
123 | } | |
124 | ||
c97f6dd0 OBC |
125 | i *= 32; /* actual number of locks in this device */ |
126 | ||
127 | state = kzalloc(sizeof(*state) + i * sizeof(*omap_lock), GFP_KERNEL); | |
128 | if (!state) { | |
129 | ret = -ENOMEM; | |
130 | goto iounmap_base; | |
131 | } | |
132 | ||
133 | state->num_locks = i; | |
70ba4cc2 SQ |
134 | state->io_base = io_base; |
135 | ||
136 | platform_set_drvdata(pdev, state); | |
137 | ||
138 | /* | |
139 | * runtime PM will make sure the clock of this module is | |
140 | * enabled iff at least one lock is requested | |
141 | */ | |
142 | pm_runtime_enable(&pdev->dev); | |
143 | ||
144 | for (i = 0; i < state->num_locks; i++) { | |
c97f6dd0 | 145 | omap_lock = &state->lock[i]; |
70ba4cc2 SQ |
146 | |
147 | omap_lock->lock.dev = &pdev->dev; | |
c3c1250e | 148 | omap_lock->lock.id = pdata->base_id + i; |
70ba4cc2 SQ |
149 | omap_lock->lock.ops = &omap_hwspinlock_ops; |
150 | omap_lock->addr = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; | |
151 | ||
152 | ret = hwspin_lock_register(&omap_lock->lock); | |
c97f6dd0 | 153 | if (ret) |
70ba4cc2 | 154 | goto free_locks; |
70ba4cc2 SQ |
155 | } |
156 | ||
157 | return 0; | |
158 | ||
159 | free_locks: | |
c97f6dd0 OBC |
160 | while (--i >= 0) |
161 | hwspin_lock_unregister(i); | |
70ba4cc2 | 162 | pm_runtime_disable(&pdev->dev); |
c97f6dd0 | 163 | kfree(state); |
70ba4cc2 SQ |
164 | iounmap_base: |
165 | iounmap(io_base); | |
70ba4cc2 SQ |
166 | return ret; |
167 | } | |
168 | ||
169 | static int omap_hwspinlock_remove(struct platform_device *pdev) | |
170 | { | |
171 | struct omap_hwspinlock_state *state = platform_get_drvdata(pdev); | |
172 | struct hwspinlock *lock; | |
70ba4cc2 SQ |
173 | int i; |
174 | ||
175 | for (i = 0; i < state->num_locks; i++) { | |
176 | lock = hwspin_lock_unregister(i); | |
177 | /* this shouldn't happen at this point. if it does, at least | |
178 | * don't continue with the remove */ | |
179 | if (!lock) { | |
180 | dev_err(&pdev->dev, "%s: failed on %d\n", __func__, i); | |
181 | return -EBUSY; | |
182 | } | |
70ba4cc2 SQ |
183 | } |
184 | ||
185 | pm_runtime_disable(&pdev->dev); | |
186 | iounmap(state->io_base); | |
187 | kfree(state); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
192 | static struct platform_driver omap_hwspinlock_driver = { | |
193 | .probe = omap_hwspinlock_probe, | |
194 | .remove = omap_hwspinlock_remove, | |
195 | .driver = { | |
196 | .name = "omap_hwspinlock", | |
e467b642 | 197 | .owner = THIS_MODULE, |
70ba4cc2 SQ |
198 | }, |
199 | }; | |
200 | ||
201 | static int __init omap_hwspinlock_init(void) | |
202 | { | |
203 | return platform_driver_register(&omap_hwspinlock_driver); | |
204 | } | |
205 | /* board init code might need to reserve hwspinlocks for predefined purposes */ | |
206 | postcore_initcall(omap_hwspinlock_init); | |
207 | ||
208 | static void __exit omap_hwspinlock_exit(void) | |
209 | { | |
210 | platform_driver_unregister(&omap_hwspinlock_driver); | |
211 | } | |
212 | module_exit(omap_hwspinlock_exit); | |
213 | ||
214 | MODULE_LICENSE("GPL v2"); | |
215 | MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); | |
216 | MODULE_AUTHOR("Simon Que <sque@ti.com>"); | |
217 | MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); | |
218 | MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); |