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2e1cdfe1 PP |
1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #ifndef _CORESIGHT_CORESIGHT_ETM_H | |
14 | #define _CORESIGHT_CORESIGHT_ETM_H | |
15 | ||
c38a9ec2 | 16 | #include <asm/local.h> |
2e1cdfe1 PP |
17 | #include <linux/spinlock.h> |
18 | #include "coresight-priv.h" | |
19 | ||
20 | /* | |
21 | * Device registers: | |
22 | * 0x000 - 0x2FC: Trace registers | |
23 | * 0x300 - 0x314: Management registers | |
24 | * 0x318 - 0xEFC: Trace registers | |
25 | * 0xF00: Management registers | |
26 | * 0xFA0 - 0xFA4: Trace registers | |
27 | * 0xFA8 - 0xFFC: Management registers | |
28 | */ | |
29 | /* Trace registers (0x000-0x2FC) */ | |
30 | /* Main control and configuration registers */ | |
31 | #define TRCPRGCTLR 0x004 | |
32 | #define TRCPROCSELR 0x008 | |
33 | #define TRCSTATR 0x00C | |
34 | #define TRCCONFIGR 0x010 | |
35 | #define TRCAUXCTLR 0x018 | |
36 | #define TRCEVENTCTL0R 0x020 | |
37 | #define TRCEVENTCTL1R 0x024 | |
38 | #define TRCSTALLCTLR 0x02C | |
39 | #define TRCTSCTLR 0x030 | |
40 | #define TRCSYNCPR 0x034 | |
41 | #define TRCCCCTLR 0x038 | |
42 | #define TRCBBCTLR 0x03C | |
43 | #define TRCTRACEIDR 0x040 | |
44 | #define TRCQCTLR 0x044 | |
45 | /* Filtering control registers */ | |
46 | #define TRCVICTLR 0x080 | |
47 | #define TRCVIIECTLR 0x084 | |
48 | #define TRCVISSCTLR 0x088 | |
49 | #define TRCVIPCSSCTLR 0x08C | |
50 | #define TRCVDCTLR 0x0A0 | |
51 | #define TRCVDSACCTLR 0x0A4 | |
52 | #define TRCVDARCCTLR 0x0A8 | |
53 | /* Derived resources registers */ | |
54 | #define TRCSEQEVRn(n) (0x100 + (n * 4)) | |
55 | #define TRCSEQRSTEVR 0x118 | |
56 | #define TRCSEQSTR 0x11C | |
57 | #define TRCEXTINSELR 0x120 | |
58 | #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) | |
59 | #define TRCCNTCTLRn(n) (0x150 + (n * 4)) | |
60 | #define TRCCNTVRn(n) (0x160 + (n * 4)) | |
61 | /* ID registers */ | |
62 | #define TRCIDR8 0x180 | |
63 | #define TRCIDR9 0x184 | |
64 | #define TRCIDR10 0x188 | |
65 | #define TRCIDR11 0x18C | |
66 | #define TRCIDR12 0x190 | |
67 | #define TRCIDR13 0x194 | |
68 | #define TRCIMSPEC0 0x1C0 | |
69 | #define TRCIMSPECn(n) (0x1C0 + (n * 4)) | |
70 | #define TRCIDR0 0x1E0 | |
71 | #define TRCIDR1 0x1E4 | |
72 | #define TRCIDR2 0x1E8 | |
73 | #define TRCIDR3 0x1EC | |
74 | #define TRCIDR4 0x1F0 | |
75 | #define TRCIDR5 0x1F4 | |
76 | #define TRCIDR6 0x1F8 | |
77 | #define TRCIDR7 0x1FC | |
78 | /* Resource selection registers */ | |
79 | #define TRCRSCTLRn(n) (0x200 + (n * 4)) | |
80 | /* Single-shot comparator registers */ | |
81 | #define TRCSSCCRn(n) (0x280 + (n * 4)) | |
82 | #define TRCSSCSRn(n) (0x2A0 + (n * 4)) | |
83 | #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) | |
84 | /* Management registers (0x300-0x314) */ | |
85 | #define TRCOSLAR 0x300 | |
86 | #define TRCOSLSR 0x304 | |
87 | #define TRCPDCR 0x310 | |
88 | #define TRCPDSR 0x314 | |
89 | /* Trace registers (0x318-0xEFC) */ | |
90 | /* Comparator registers */ | |
91 | #define TRCACVRn(n) (0x400 + (n * 8)) | |
92 | #define TRCACATRn(n) (0x480 + (n * 8)) | |
93 | #define TRCDVCVRn(n) (0x500 + (n * 16)) | |
94 | #define TRCDVCMRn(n) (0x580 + (n * 16)) | |
95 | #define TRCCIDCVRn(n) (0x600 + (n * 8)) | |
96 | #define TRCVMIDCVRn(n) (0x640 + (n * 8)) | |
97 | #define TRCCIDCCTLR0 0x680 | |
98 | #define TRCCIDCCTLR1 0x684 | |
99 | #define TRCVMIDCCTLR0 0x688 | |
100 | #define TRCVMIDCCTLR1 0x68C | |
101 | /* Management register (0xF00) */ | |
102 | /* Integration control registers */ | |
103 | #define TRCITCTRL 0xF00 | |
104 | /* Trace registers (0xFA0-0xFA4) */ | |
105 | /* Claim tag registers */ | |
106 | #define TRCCLAIMSET 0xFA0 | |
107 | #define TRCCLAIMCLR 0xFA4 | |
108 | /* Management registers (0xFA8-0xFFC) */ | |
109 | #define TRCDEVAFF0 0xFA8 | |
110 | #define TRCDEVAFF1 0xFAC | |
111 | #define TRCLAR 0xFB0 | |
112 | #define TRCLSR 0xFB4 | |
113 | #define TRCAUTHSTATUS 0xFB8 | |
114 | #define TRCDEVARCH 0xFBC | |
115 | #define TRCDEVID 0xFC8 | |
116 | #define TRCDEVTYPE 0xFCC | |
117 | #define TRCPIDR4 0xFD0 | |
118 | #define TRCPIDR5 0xFD4 | |
119 | #define TRCPIDR6 0xFD8 | |
120 | #define TRCPIDR7 0xFDC | |
121 | #define TRCPIDR0 0xFE0 | |
122 | #define TRCPIDR1 0xFE4 | |
123 | #define TRCPIDR2 0xFE8 | |
124 | #define TRCPIDR3 0xFEC | |
125 | #define TRCCIDR0 0xFF0 | |
126 | #define TRCCIDR1 0xFF4 | |
127 | #define TRCCIDR2 0xFF8 | |
128 | #define TRCCIDR3 0xFFC | |
129 | ||
130 | /* ETMv4 resources */ | |
131 | #define ETM_MAX_NR_PE 8 | |
132 | #define ETMv4_MAX_CNTR 4 | |
133 | #define ETM_MAX_SEQ_STATES 4 | |
134 | #define ETM_MAX_EXT_INP_SEL 4 | |
135 | #define ETM_MAX_EXT_INP 256 | |
136 | #define ETM_MAX_EXT_OUT 4 | |
137 | #define ETM_MAX_SINGLE_ADDR_CMP 16 | |
138 | #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) | |
139 | #define ETM_MAX_DATA_VAL_CMP 8 | |
140 | #define ETMv4_MAX_CTXID_CMP 8 | |
141 | #define ETM_MAX_VMID_CMP 8 | |
142 | #define ETM_MAX_PE_CMP 8 | |
143 | #define ETM_MAX_RES_SEL 16 | |
144 | #define ETM_MAX_SS_CMP 8 | |
145 | ||
146 | #define ETM_ARCH_V4 0x40 | |
147 | #define ETMv4_SYNC_MASK 0x1F | |
148 | #define ETM_CYC_THRESHOLD_MASK 0xFFF | |
149 | #define ETMv4_EVENT_MASK 0xFF | |
150 | #define ETM_CNTR_MAX_VAL 0xFFFF | |
151 | #define ETM_TRACEID_MASK 0x3f | |
152 | ||
153 | /* ETMv4 programming modes */ | |
154 | #define ETM_MODE_EXCLUDE BIT(0) | |
155 | #define ETM_MODE_LOAD BIT(1) | |
156 | #define ETM_MODE_STORE BIT(2) | |
157 | #define ETM_MODE_LOAD_STORE BIT(3) | |
158 | #define ETM_MODE_BB BIT(4) | |
159 | #define ETMv4_MODE_CYCACC BIT(5) | |
160 | #define ETMv4_MODE_CTXID BIT(6) | |
161 | #define ETM_MODE_VMID BIT(7) | |
162 | #define ETM_MODE_COND(val) BMVAL(val, 8, 10) | |
163 | #define ETMv4_MODE_TIMESTAMP BIT(11) | |
164 | #define ETM_MODE_RETURNSTACK BIT(12) | |
165 | #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) | |
166 | #define ETM_MODE_DATA_TRACE_ADDR BIT(15) | |
167 | #define ETM_MODE_DATA_TRACE_VAL BIT(16) | |
168 | #define ETM_MODE_ISTALL BIT(17) | |
169 | #define ETM_MODE_DSTALL BIT(18) | |
170 | #define ETM_MODE_ATB_TRIGGER BIT(19) | |
171 | #define ETM_MODE_LPOVERRIDE BIT(20) | |
172 | #define ETM_MODE_ISTALL_EN BIT(21) | |
173 | #define ETM_MODE_DSTALL_EN BIT(22) | |
174 | #define ETM_MODE_INSTPRIO BIT(23) | |
175 | #define ETM_MODE_NOOVERFLOW BIT(24) | |
176 | #define ETM_MODE_TRACE_RESET BIT(25) | |
177 | #define ETM_MODE_TRACE_ERR BIT(26) | |
178 | #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) | |
179 | #define ETMv4_MODE_ALL 0xFFFFFFF | |
180 | ||
181 | #define TRCSTATR_IDLE_BIT 0 | |
fc208abe MP |
182 | #define ETM_DEFAULT_ADDR_COMP 0 |
183 | ||
184 | /* secure state access levels */ | |
185 | #define ETM_EXLEVEL_S_APP BIT(8) | |
186 | #define ETM_EXLEVEL_S_OS BIT(9) | |
187 | #define ETM_EXLEVEL_S_NA BIT(10) | |
188 | #define ETM_EXLEVEL_S_HYP BIT(11) | |
189 | /* non-secure state access levels */ | |
190 | #define ETM_EXLEVEL_NS_APP BIT(12) | |
191 | #define ETM_EXLEVEL_NS_OS BIT(13) | |
192 | #define ETM_EXLEVEL_NS_HYP BIT(14) | |
193 | #define ETM_EXLEVEL_NS_NA BIT(15) | |
2e1cdfe1 PP |
194 | |
195 | /** | |
54ff892b | 196 | * struct etmv4_config - configuration information related to an ETMv4 |
2e1cdfe1 | 197 | * @mode: Controls various modes supported by this ETM. |
2e1cdfe1 PP |
198 | * @pe_sel: Controls which PE to trace. |
199 | * @cfg: Controls the tracing options. | |
200 | * @eventctrl0: Controls the tracing of arbitrary events. | |
201 | * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. | |
202 | * @stallctl: If functionality that prevents trace unit buffer overflows | |
203 | * is available. | |
2e1cdfe1 PP |
204 | * @ts_ctrl: Controls the insertion of global timestamps in the |
205 | * trace streams. | |
2e1cdfe1 | 206 | * @syncfreq: Controls how often trace synchronization requests occur. |
2e1cdfe1 PP |
207 | * the TRCCCCTLR register. |
208 | * @ccctlr: Sets the threshold value for cycle counting. | |
2e1cdfe1 PP |
209 | * @vinst_ctrl: Controls instruction trace filtering. |
210 | * @viiectlr: Set or read, the address range comparators. | |
211 | * @vissctlr: Set, or read, the single address comparators that control the | |
212 | * ViewInst start-stop logic. | |
213 | * @vipcssctlr: Set, or read, which PE comparator inputs can control the | |
214 | * ViewInst start-stop logic. | |
215 | * @seq_idx: Sequencor index selector. | |
216 | * @seq_ctrl: Control for the sequencer state transition control register. | |
217 | * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. | |
218 | * @seq_state: Set, or read the sequencer state. | |
219 | * @cntr_idx: Counter index seletor. | |
220 | * @cntrldvr: Sets or returns the reload count value for a counter. | |
221 | * @cntr_ctrl: Controls the operation of a counter. | |
222 | * @cntr_val: Sets or returns the value for a counter. | |
223 | * @res_idx: Resource index selector. | |
224 | * @res_ctrl: Controls the selection of the resources in the trace unit. | |
225 | * @ss_ctrl: Controls the corresponding single-shot comparator resource. | |
226 | * @ss_status: The status of the corresponding single-shot comparator. | |
227 | * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. | |
228 | * @addr_idx: Address comparator index selector. | |
229 | * @addr_val: Value for address comparator. | |
230 | * @addr_acc: Address comparator access type. | |
231 | * @addr_type: Current status of the comparator register. | |
232 | * @ctxid_idx: Context ID index selector. | |
cd196ac3 | 233 | * @ctxid_pid: Value of the context ID comparator. |
f67b467a CZ |
234 | * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise |
235 | * the same value of ctxid_pid. | |
2e1cdfe1 PP |
236 | * @ctxid_mask0:Context ID comparator mask for comparator 0-3. |
237 | * @ctxid_mask1:Context ID comparator mask for comparator 4-7. | |
238 | * @vmid_idx: VM ID index selector. | |
2e1cdfe1 PP |
239 | * @vmid_val: Value of the VM ID comparator. |
240 | * @vmid_mask0: VM ID comparator mask for comparator 0-3. | |
241 | * @vmid_mask1: VM ID comparator mask for comparator 4-7. | |
2e1cdfe1 PP |
242 | * @ext_inp: External input selection. |
243 | */ | |
54ff892b | 244 | struct etmv4_config { |
2e1cdfe1 | 245 | u32 mode; |
2e1cdfe1 PP |
246 | u32 pe_sel; |
247 | u32 cfg; | |
248 | u32 eventctrl0; | |
249 | u32 eventctrl1; | |
2e1cdfe1 | 250 | u32 stall_ctrl; |
2e1cdfe1 | 251 | u32 ts_ctrl; |
2e1cdfe1 | 252 | u32 syncfreq; |
2e1cdfe1 | 253 | u32 ccctlr; |
2e1cdfe1 | 254 | u32 bb_ctrl; |
2e1cdfe1 PP |
255 | u32 vinst_ctrl; |
256 | u32 viiectlr; | |
257 | u32 vissctlr; | |
258 | u32 vipcssctlr; | |
259 | u8 seq_idx; | |
260 | u32 seq_ctrl[ETM_MAX_SEQ_STATES]; | |
261 | u32 seq_rst; | |
262 | u32 seq_state; | |
263 | u8 cntr_idx; | |
264 | u32 cntrldvr[ETMv4_MAX_CNTR]; | |
265 | u32 cntr_ctrl[ETMv4_MAX_CNTR]; | |
266 | u32 cntr_val[ETMv4_MAX_CNTR]; | |
267 | u8 res_idx; | |
268 | u32 res_ctrl[ETM_MAX_RES_SEL]; | |
269 | u32 ss_ctrl[ETM_MAX_SS_CMP]; | |
270 | u32 ss_status[ETM_MAX_SS_CMP]; | |
271 | u32 ss_pe_cmp[ETM_MAX_SS_CMP]; | |
272 | u8 addr_idx; | |
273 | u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; | |
274 | u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; | |
275 | u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; | |
276 | u8 ctxid_idx; | |
cd196ac3 | 277 | u64 ctxid_pid[ETMv4_MAX_CTXID_CMP]; |
f67b467a | 278 | u64 ctxid_vpid[ETMv4_MAX_CTXID_CMP]; |
2e1cdfe1 PP |
279 | u32 ctxid_mask0; |
280 | u32 ctxid_mask1; | |
281 | u8 vmid_idx; | |
2e1cdfe1 PP |
282 | u64 vmid_val[ETM_MAX_VMID_CMP]; |
283 | u32 vmid_mask0; | |
284 | u32 vmid_mask1; | |
54ff892b MP |
285 | u32 ext_inp; |
286 | }; | |
287 | ||
288 | /** | |
289 | * struct etm4_drvdata - specifics associated to an ETM component | |
290 | * @base: Memory mapped base address for this component. | |
291 | * @dev: The device entity associated to this component. | |
292 | * @csdev: Component vitals needed by the framework. | |
293 | * @spinlock: Only one at a time pls. | |
c38a9ec2 | 294 | * @mode: This tracer's mode, i.e sysFS, Perf or disabled. |
54ff892b MP |
295 | * @cpu: The cpu this component is affined to. |
296 | * @arch: ETM version number. | |
297 | * @nr_pe: The number of processing entity available for tracing. | |
298 | * @nr_pe_cmp: The number of processing entity comparator inputs that are | |
299 | * available for tracing. | |
300 | * @nr_addr_cmp:Number of pairs of address comparators available | |
301 | * as found in ETMIDR4 0-3. | |
302 | * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. | |
303 | * @nr_ext_inp: Number of external input. | |
304 | * @numcidc: Number of contextID comparators. | |
305 | * @numvmidc: Number of VMID comparators. | |
306 | * @nrseqstate: The number of sequencer states that are implemented. | |
307 | * @nr_event: Indicates how many events the trace unit support. | |
308 | * @nr_resource:The number of resource selection pairs available for tracing. | |
309 | * @nr_ss_cmp: Number of single-shot comparator controls that are available. | |
310 | * @trcid: value of the current ID for this component. | |
311 | * @trcid_size: Indicates the trace ID width. | |
312 | * @ts_size: Global timestamp size field. | |
313 | * @ctxid_size: Size of the context ID field to consider. | |
314 | * @vmid_size: Size of the VM ID comparator to consider. | |
315 | * @ccsize: Indicates the size of the cycle counter in bits. | |
316 | * @ccitmin: minimum value that can be programmed in | |
317 | * @s_ex_level: In secure state, indicates whether instruction tracing is | |
318 | * supported for the corresponding Exception level. | |
319 | * @ns_ex_level:In non-secure state, indicates whether instruction tracing is | |
320 | * supported for the corresponding Exception level. | |
54ff892b MP |
321 | * @sticky_enable: true if ETM base configuration has been done. |
322 | * @boot_enable:True if we should start tracing at boot time. | |
323 | * @os_unlock: True if access to management registers is allowed. | |
324 | * @instrp0: Tracing of load and store instructions | |
325 | * as P0 elements is supported. | |
326 | * @trcbb: Indicates if the trace unit supports branch broadcast tracing. | |
327 | * @trccond: If the trace unit supports conditional | |
328 | * instruction tracing. | |
329 | * @retstack: Indicates if the implementation supports a return stack. | |
330 | * @trccci: Indicates if the trace unit supports cycle counting | |
331 | * for instruction. | |
332 | * @q_support: Q element support characteristics. | |
333 | * @trc_error: Whether a trace unit can trace a system | |
334 | * error exception. | |
335 | * @syncpr: Indicates if an implementation has a fixed | |
336 | * synchronization period. | |
337 | * @stall_ctrl: Enables trace unit functionality that prevents trace | |
338 | * unit buffer overflows. | |
339 | * @sysstall: Does the system support stall control of the PE? | |
340 | * @nooverflow: Indicate if overflow prevention is supported. | |
341 | * @atbtrig: If the implementation can support ATB triggers | |
342 | * @lpoverride: If the implementation can support low-power state over. | |
343 | * @config: structure holding configuration parameters. | |
344 | */ | |
345 | struct etmv4_drvdata { | |
346 | void __iomem *base; | |
347 | struct device *dev; | |
348 | struct coresight_device *csdev; | |
349 | spinlock_t spinlock; | |
c38a9ec2 | 350 | local_t mode; |
54ff892b MP |
351 | int cpu; |
352 | u8 arch; | |
353 | u8 nr_pe; | |
354 | u8 nr_pe_cmp; | |
355 | u8 nr_addr_cmp; | |
356 | u8 nr_cntr; | |
357 | u8 nr_ext_inp; | |
358 | u8 numcidc; | |
359 | u8 numvmidc; | |
360 | u8 nrseqstate; | |
361 | u8 nr_event; | |
362 | u8 nr_resource; | |
363 | u8 nr_ss_cmp; | |
364 | u8 trcid; | |
365 | u8 trcid_size; | |
366 | u8 ts_size; | |
367 | u8 ctxid_size; | |
368 | u8 vmid_size; | |
369 | u8 ccsize; | |
370 | u8 ccitmin; | |
2e1cdfe1 PP |
371 | u8 s_ex_level; |
372 | u8 ns_ex_level; | |
54ff892b MP |
373 | bool sticky_enable; |
374 | bool boot_enable; | |
375 | bool os_unlock; | |
376 | bool instrp0; | |
377 | bool trcbb; | |
378 | bool trccond; | |
379 | bool retstack; | |
380 | bool trccci; | |
381 | bool q_support; | |
382 | bool trc_error; | |
383 | bool syncpr; | |
384 | bool stallctl; | |
385 | bool sysstall; | |
386 | bool nooverflow; | |
387 | bool atbtrig; | |
388 | bool lpoverride; | |
389 | struct etmv4_config config; | |
2e1cdfe1 PP |
390 | }; |
391 | ||
392 | /* Address comparator access types */ | |
393 | enum etm_addr_acctype { | |
394 | ETM_INSTR_ADDR, | |
395 | ETM_DATA_LOAD_ADDR, | |
396 | ETM_DATA_STORE_ADDR, | |
397 | ETM_DATA_LOAD_STORE_ADDR, | |
398 | }; | |
399 | ||
400 | /* Address comparator context types */ | |
401 | enum etm_addr_ctxtype { | |
402 | ETM_CTX_NONE, | |
403 | ETM_CTX_CTXID, | |
404 | ETM_CTX_VMID, | |
405 | ETM_CTX_CTXID_VMID, | |
406 | }; | |
407 | ||
408 | enum etm_addr_type { | |
409 | ETM_ADDR_TYPE_NONE, | |
410 | ETM_ADDR_TYPE_SINGLE, | |
411 | ETM_ADDR_TYPE_RANGE, | |
412 | ETM_ADDR_TYPE_START, | |
413 | ETM_ADDR_TYPE_STOP, | |
414 | }; | |
a77de263 MP |
415 | |
416 | extern const struct attribute_group *coresight_etmv4_groups[]; | |
2e1cdfe1 | 417 | #endif |