[mirror_ubuntu-hirsute-kernel.git] / drivers / hwtracing / intel_th / pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel(R) Trace Hub pci driver
 *
 * Copyright (C) 2014-2015 Intel Corporation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/types.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/sysfs.h>
#include <linux/pci.h>

#include "intel_th.h"

#define DRIVER_NAME "intel_th_pci"

enum {
	TH_PCI_CONFIG_BAR	= 0,
	TH_PCI_STH_SW_BAR	= 2,
	TH_PCI_RTIT_BAR		= 4,
};

#define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) | BIT(TH_PCI_STH_SW_BAR))

#define PCI_REG_NPKDSC	0x80
#define NPKDSC_TSACT	BIT(5)

static int intel_th_pci_activate(struct intel_th *th)
{
	struct pci_dev *pdev = to_pci_dev(th->dev);
	u32 npkdsc;
	int err;

	if (!INTEL_TH_CAP(th, tscu_enable))
		return 0;

	err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
	if (!err) {
		npkdsc |= NPKDSC_TSACT;
		err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
	}

	if (err)
		dev_err(&pdev->dev, "failed to read NPKDSC register\n");

	return err;
}

static void intel_th_pci_deactivate(struct intel_th *th)
{
	struct pci_dev *pdev = to_pci_dev(th->dev);
	u32 npkdsc;
	int err;

	if (!INTEL_TH_CAP(th, tscu_enable))
		return;

	err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
	if (!err) {
		npkdsc |= NPKDSC_TSACT;
		err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
	}

	if (err)
		dev_err(&pdev->dev, "failed to read NPKDSC register\n");
}

static int intel_th_pci_probe(struct pci_dev *pdev,
			      const struct pci_device_id *id)
{
	struct intel_th_drvdata *drvdata = (void *)id->driver_data;
	struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = {
		[TH_MMIO_CONFIG]	= pdev->resource[TH_PCI_CONFIG_BAR],
		[TH_MMIO_SW]		= pdev->resource[TH_PCI_STH_SW_BAR],
	};
	int err, r = TH_MMIO_SW + 1, i;
	struct intel_th *th;

	err = pcim_enable_device(pdev);
	if (err)
		return err;

	err = pcim_iomap_regions_request_all(pdev, BAR_MASK, DRIVER_NAME);
	if (err)
		return err;

	if (pdev->resource[TH_PCI_RTIT_BAR].start) {
		resource[TH_MMIO_RTIT] = pdev->resource[TH_PCI_RTIT_BAR];
		r++;
	}

	err = pci_alloc_irq_vectors(pdev, 1, 8, PCI_IRQ_ALL_TYPES);
	if (err > 0)
		for (i = 0; i < err; i++, r++) {
			resource[r].flags = IORESOURCE_IRQ;
			resource[r].start = pci_irq_vector(pdev, i);
		}

	th = intel_th_alloc(&pdev->dev, drvdata, resource, r);
	if (IS_ERR(th))
		return PTR_ERR(th);

	th->activate   = intel_th_pci_activate;
	th->deactivate = intel_th_pci_deactivate;

	pci_set_master(pdev);

	return 0;
}

static void intel_th_pci_remove(struct pci_dev *pdev)
{
	struct intel_th *th = pci_get_drvdata(pdev);

	intel_th_free(th);

	pci_free_irq_vectors(pdev);
}

static const struct intel_th_drvdata intel_th_1x_multi_is_broken = {
	.multi_is_broken	= 1,
};

static const struct intel_th_drvdata intel_th_2x = {
	.tscu_enable	= 1,
	.has_mintctl	= 1,
};

static const struct pci_device_id intel_th_pci_id_table[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9d26),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa126),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Apollo Lake */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x5a8e),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Broxton */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0a80),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Broxton B-step */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1a8e),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Kaby Lake PCH-H */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
		.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
	},
	{
		/* Denverton */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Lewisburg PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa1a6),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Lewisburg PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa226),
		.driver_data = (kernel_ulong_t)0,
	},
	{
		/* Gemini Lake */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Cannon Lake H */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa326),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Cannon Lake LP */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9da6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Cedar Fork PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x18e1),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Ice Lake PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x34a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Comet Lake */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x02a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Comet Lake PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x06a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Comet Lake PCH-V */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa3a6),
		.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
	},
	{
		/* Ice Lake NNPI */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x45c5),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Ice Lake CPU */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8a29),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Tiger Lake CPU */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9a33),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Tiger Lake PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa0a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Tiger Lake PCH-H */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x43a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Jasper Lake PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Jasper Lake CPU */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4e29),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Elkhart Lake CPU */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4529),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Elkhart Lake */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4b26),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Emmitsburg PCH */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1bcc),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Alder Lake */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7aa6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Alder Lake-P */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x51a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Alder Lake-M */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x54a6),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Alder Lake CPU */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{
		/* Rocket Lake CPU */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c19),
		.driver_data = (kernel_ulong_t)&intel_th_2x,
	},
	{ 0 },
};

MODULE_DEVICE_TABLE(pci, intel_th_pci_id_table);

static struct pci_driver intel_th_pci_driver = {
	.name		= DRIVER_NAME,
	.id_table	= intel_th_pci_id_table,
	.probe		= intel_th_pci_probe,
	.remove		= intel_th_pci_remove,
};

module_pci_driver(intel_th_pci_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel(R) Trace Hub PCI controller driver");
MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@intel.com>");
Commit	Line	Data
50352fa7	1	// SPDX-License-Identifier: GPL-2.0
2b0b16d3 AS	2	/*
	3	* Intel(R) Trace Hub pci driver
	4	*
	5	* Copyright (C) 2014-2015 Intel Corporation.
2b0b16d3 AS	6	*/
	7
	8	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	9
	10	#include <linux/types.h>
	11	#include <linux/module.h>
	12	#include <linux/device.h>
	13	#include <linux/sysfs.h>
	14	#include <linux/pci.h>
	15
	16	#include "intel_th.h"
	17
	18	#define DRIVER_NAME "intel_th_pci"
	19
db73a059 AS	20	enum {
	21	TH_PCI_CONFIG_BAR = 0,
	22	TH_PCI_STH_SW_BAR = 2,
fc027f4c	23	TH_PCI_RTIT_BAR = 4,
db73a059 AS	24	};
	25
	26	#define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) \| BIT(TH_PCI_STH_SW_BAR))
2b0b16d3	27
a0e7df33 AS	28	#define PCI_REG_NPKDSC 0x80
	29	#define NPKDSC_TSACT BIT(5)
	30
	31	static int intel_th_pci_activate(struct intel_th *th)
	32	{
	33	struct pci_dev *pdev = to_pci_dev(th->dev);
	34	u32 npkdsc;
	35	int err;
	36
	37	if (!INTEL_TH_CAP(th, tscu_enable))
	38	return 0;
	39
	40	err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
	41	if (!err) {
	42	npkdsc \|= NPKDSC_TSACT;
	43	err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
	44	}
	45
	46	if (err)
	47	dev_err(&pdev->dev, "failed to read NPKDSC register\n");
	48
	49	return err;
	50	}
	51
	52	static void intel_th_pci_deactivate(struct intel_th *th)
	53	{
	54	struct pci_dev *pdev = to_pci_dev(th->dev);
	55	u32 npkdsc;
	56	int err;
	57
	58	if (!INTEL_TH_CAP(th, tscu_enable))
	59	return;
	60
	61	err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
	62	if (!err) {
	63	npkdsc \|= NPKDSC_TSACT;
	64	err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
	65	}
	66
	67	if (err)
	68	dev_err(&pdev->dev, "failed to read NPKDSC register\n");
	69	}
	70
2b0b16d3 AS	71	static int intel_th_pci_probe(struct pci_dev *pdev,
	72	const struct pci_device_id *id)
	73	{
3321371b	74	struct intel_th_drvdata drvdata = (void )id->driver_data;
7b7036d4	75	struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = {
db73a059 AS	76	[TH_MMIO_CONFIG] = pdev->resource[TH_PCI_CONFIG_BAR],
	77	[TH_MMIO_SW] = pdev->resource[TH_PCI_STH_SW_BAR],
	78	};
7b7036d4	79	int err, r = TH_MMIO_SW + 1, i;
2b0b16d3	80	struct intel_th *th;
2b0b16d3 AS	81
	82	err = pcim_enable_device(pdev);
	83	if (err)
	84	return err;
	85
	86	err = pcim_iomap_regions_request_all(pdev, BAR_MASK, DRIVER_NAME);
	87	if (err)
	88	return err;
	89
fc027f4c AS	90	if (pdev->resource[TH_PCI_RTIT_BAR].start) {
	91	resource[TH_MMIO_RTIT] = pdev->resource[TH_PCI_RTIT_BAR];
	92	r++;
	93	}
	94
7b7036d4 AS	95	err = pci_alloc_irq_vectors(pdev, 1, 8, PCI_IRQ_ALL_TYPES);
	96	if (err > 0)
	97	for (i = 0; i < err; i++, r++) {
	98	resource[r].flags = IORESOURCE_IRQ;
	99	resource[r].start = pci_irq_vector(pdev, i);
	100	}
62a59302 AS	101
62a59302 AS	102	th = intel_th_alloc(&pdev->dev, drvdata, resource, r);
2b0b16d3 AS	103	if (IS_ERR(th))
2b0b16d3 AS	104	return PTR_ERR(th);
2b0b16d3	105
a0e7df33 AS	106	th->activate = intel_th_pci_activate;
	107	th->deactivate = intel_th_pci_deactivate;
	108
e9b2b3e7 AS	109	pci_set_master(pdev);
e9b2b3e7 AS	110
2b0b16d3 AS	111	return 0;
	112	}
	113
	114	static void intel_th_pci_remove(struct pci_dev *pdev)
	115	{
	116	struct intel_th *th = pci_get_drvdata(pdev);
	117
	118	intel_th_free(th);
7b7036d4 AS	119
7b7036d4 AS	120	pci_free_irq_vectors(pdev);
2b0b16d3 AS	121	}
2b0b16d3 AS	122
397c7729 AS	123	static const struct intel_th_drvdata intel_th_1x_multi_is_broken = {
	124	.multi_is_broken = 1,
	125	};
	126
a0e7df33 AS	127	static const struct intel_th_drvdata intel_th_2x = {
a0e7df33 AS	128	.tscu_enable = 1,
4c5bb6eb	129	.has_mintctl = 1,
a0e7df33 AS	130	};
a0e7df33 AS	131
2b0b16d3 AS	132	static const struct pci_device_id intel_th_pci_id_table[] = {
	133	{
	134	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9d26),
	135	.driver_data = (kernel_ulong_t)0,
	136	},
	137	{
	138	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa126),
	139	.driver_data = (kernel_ulong_t)0,
	140	},
6396b912 AS	141	{
	142	/* Apollo Lake */
	143	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x5a8e),
	144	.driver_data = (kernel_ulong_t)0,
	145	},
3f040887 AS	146	{
	147	/* Broxton */
	148	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0a80),
	149	.driver_data = (kernel_ulong_t)0,
	150	},
aaa3ca82 AS	151	{
	152	/* Broxton B-step */
	153	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1a8e),
	154	.driver_data = (kernel_ulong_t)0,
	155	},
7a1a47ce AS	156	{
	157	/* Kaby Lake PCH-H */
	158	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
397c7729	159	.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
7a1a47ce	160	},
5118ccd3 AS	161	{
	162	/* Denverton */
	163	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
	164	.driver_data = (kernel_ulong_t)0,
	165	},
24600840 AS	166	{
	167	/* Lewisburg PCH */
	168	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa1a6),
	169	.driver_data = (kernel_ulong_t)0,
	170	},
164eb56e AS	171	{
	172	/* Lewisburg PCH */
	173	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa226),
	174	.driver_data = (kernel_ulong_t)0,
	175	},
340837f9 AS	176	{
	177	/* Gemini Lake */
	178	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
a0e7df33	179	.driver_data = (kernel_ulong_t)&intel_th_2x,
340837f9	180	},
84331e13 AS	181	{
	182	/* Cannon Lake H */
	183	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa326),
a0e7df33	184	.driver_data = (kernel_ulong_t)&intel_th_2x,
84331e13	185	},
efb3669e AS	186	{
	187	/* Cannon Lake LP */
	188	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9da6),
a0e7df33	189	.driver_data = (kernel_ulong_t)&intel_th_2x,
efb3669e	190	},
920ce7c3 AS	191	{
	192	/* Cedar Fork PCH */
	193	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x18e1),
	194	.driver_data = (kernel_ulong_t)&intel_th_2x,
	195	},
59d08d00 AS	196	{
	197	/* Ice Lake PCH */
	198	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x34a6),
	199	.driver_data = (kernel_ulong_t)&intel_th_2x,
	200	},
e60e9a4b AS	201	{
	202	/* Comet Lake */
	203	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x02a6),
	204	.driver_data = (kernel_ulong_t)&intel_th_2x,
	205	},
3adbb571 AS	206	{
	207	/* Comet Lake PCH */
	208	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x06a6),
	209	.driver_data = (kernel_ulong_t)&intel_th_2x,
	210	},
e4de2a5d AS	211	{
	212	/* Comet Lake PCH-V */
	213	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa3a6),
397c7729	214	.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
e4de2a5d	215	},
4aa5aed2 AS	216	{
	217	/* Ice Lake NNPI */
	218	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x45c5),
	219	.driver_data = (kernel_ulong_t)&intel_th_2x,
	220	},
6a174342 AS	221	{
	222	/* Ice Lake CPU */
	223	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8a29),
	224	.driver_data = (kernel_ulong_t)&intel_th_2x,
	225	},
6e6c18bc AS	226	{
	227	/* Tiger Lake CPU */
	228	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9a33),
	229	.driver_data = (kernel_ulong_t)&intel_th_2x,
	230	},
9c78255f AS	231	{
	232	/* Tiger Lake PCH */
	233	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa0a6),
	234	.driver_data = (kernel_ulong_t)&intel_th_2x,
	235	},
6227585d AS	236	{
	237	/* Tiger Lake PCH-H */
	238	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x43a6),
	239	.driver_data = (kernel_ulong_t)&intel_th_2x,
	240	},
9d55499d AS	241	{
	242	/* Jasper Lake PCH */
	243	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
	244	.driver_data = (kernel_ulong_t)&intel_th_2x,
	245	},
203c1f61 AS	246	{
	247	/* Jasper Lake CPU */
	248	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4e29),
	249	.driver_data = (kernel_ulong_t)&intel_th_2x,
	250	},
add492d2 AS	251	{
	252	/* Elkhart Lake CPU */
	253	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4529),
	254	.driver_data = (kernel_ulong_t)&intel_th_2x,
	255	},
88385866 AS	256	{
	257	/* Elkhart Lake */
	258	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4b26),
	259	.driver_data = (kernel_ulong_t)&intel_th_2x,
	260	},
fd73d74a AS	261	{
	262	/* Emmitsburg PCH */
	263	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1bcc),
	264	.driver_data = (kernel_ulong_t)&intel_th_2x,
	265	},
951e4d71 AS	266	{
	267	/* Alder Lake */
	268	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7aa6),
	269	.driver_data = (kernel_ulong_t)&intel_th_2x,
	270	},
cb5c681a AS	271	{
	272	/* Alder Lake-P */
	273	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x51a6),
	274	.driver_data = (kernel_ulong_t)&intel_th_2x,
	275	},
bb5ded9b AS	276	{
	277	/* Alder Lake-M */
	278	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x54a6),
	279	.driver_data = (kernel_ulong_t)&intel_th_2x,
	280	},
9f126c56 AS	281	{
	282	/* Alder Lake CPU */
	283	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f),
	284	.driver_data = (kernel_ulong_t)&intel_th_2x,
	285	},
f0059c4f AS	286	{
	287	/* Rocket Lake CPU */
	288	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c19),
	289	.driver_data = (kernel_ulong_t)&intel_th_2x,
	290	},
2b0b16d3 AS	291	{ 0 },
	292	};
	293
	294	MODULE_DEVICE_TABLE(pci, intel_th_pci_id_table);
	295
	296	static struct pci_driver intel_th_pci_driver = {
	297	.name = DRIVER_NAME,
	298	.id_table = intel_th_pci_id_table,
	299	.probe = intel_th_pci_probe,
	300	.remove = intel_th_pci_remove,
	301	};
	302
	303	module_pci_driver(intel_th_pci_driver);
	304
	305	MODULE_LICENSE("GPL v2");
	306	MODULE_DESCRIPTION("Intel(R) Trace Hub PCI controller driver");
	307	MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@intel.com>");