[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-amd756.c

/*
    amd756.c - Part of lm_sensors, Linux kernel modules for hardware
              monitoring

    Copyright (c) 1999-2002 Merlin Hughes <merlin@merlin.org>

    Shamelessly ripped from i2c-piix4.c:

    Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl> and
    Philip Edelbrock <phil@netroedge.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
    2002-04-08: Added nForce support. (Csaba Halasz)
    2002-10-03: Fixed nForce PnP I/O port. (Michael Steil)
    2002-12-28: Rewritten into something that resembles a Linux driver (hch)
    2003-11-29: Added back AMD8111 removed by the previous rewrite.
                (Philip Pokorny)
*/

/*
   Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce
   Note: we assume there can only be one device, with one SMBus interface.
*/

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <asm/io.h>

/* AMD756 SMBus address offsets */
#define SMB_ADDR_OFFSET		0xE0
#define SMB_IOSIZE		16
#define SMB_GLOBAL_STATUS	(0x0 + amd756_ioport)
#define SMB_GLOBAL_ENABLE	(0x2 + amd756_ioport)
#define SMB_HOST_ADDRESS	(0x4 + amd756_ioport)
#define SMB_HOST_DATA		(0x6 + amd756_ioport)
#define SMB_HOST_COMMAND	(0x8 + amd756_ioport)
#define SMB_HOST_BLOCK_DATA	(0x9 + amd756_ioport)
#define SMB_HAS_DATA		(0xA + amd756_ioport)
#define SMB_HAS_DEVICE_ADDRESS	(0xC + amd756_ioport)
#define SMB_HAS_HOST_ADDRESS	(0xE + amd756_ioport)
#define SMB_SNOOP_ADDRESS	(0xF + amd756_ioport)

/* PCI Address Constants */

/* address of I/O space */
#define SMBBA		0x058		/* mh */
#define SMBBANFORCE	0x014

/* general configuration */
#define SMBGCFG		0x041		/* mh */

/* silicon revision code */
#define SMBREV		0x008

/* Other settings */
#define MAX_TIMEOUT	500

/* AMD756 constants */
#define AMD756_QUICK		0x00
#define AMD756_BYTE		0x01
#define AMD756_BYTE_DATA	0x02
#define AMD756_WORD_DATA	0x03
#define AMD756_PROCESS_CALL	0x04
#define AMD756_BLOCK_DATA	0x05

static struct pci_driver amd756_driver;
static unsigned short amd756_ioport;

/* 
  SMBUS event = I/O 28-29 bit 11
     see E0 for the status bits and enabled in E2
     
*/
#define GS_ABRT_STS	(1 << 0)
#define GS_COL_STS	(1 << 1)
#define GS_PRERR_STS	(1 << 2)
#define GS_HST_STS	(1 << 3)
#define GS_HCYC_STS	(1 << 4)
#define GS_TO_STS	(1 << 5)
#define GS_SMB_STS	(1 << 11)

#define GS_CLEAR_STS	(GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \
			 GS_HCYC_STS | GS_TO_STS )

#define GE_CYC_TYPE_MASK	(7)
#define GE_HOST_STC		(1 << 3)
#define GE_ABORT		(1 << 5)


static int amd756_transaction(struct i2c_adapter *adap)
{
	int temp;
	int result = 0;
	int timeout = 0;

	dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
		"DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
		inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
		inb_p(SMB_HOST_DATA));

	/* Make sure the SMBus host is ready to start transmitting */
	if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) {
		dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
		do {
			msleep(1);
			temp = inw_p(SMB_GLOBAL_STATUS);
		} while ((temp & (GS_HST_STS | GS_SMB_STS)) &&
		         (timeout++ < MAX_TIMEOUT));
		/* If the SMBus is still busy, we give up */
		if (timeout >= MAX_TIMEOUT) {
			dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
			goto abort;
		}
		timeout = 0;
	}

	/* start the transaction by setting the start bit */
	outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE);

	/* We will always wait for a fraction of a second! */
	do {
		msleep(1);
		temp = inw_p(SMB_GLOBAL_STATUS);
	} while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));

	/* If the SMBus is still busy, we give up */
	if (timeout >= MAX_TIMEOUT) {
		dev_dbg(&adap->dev, "Completion timeout!\n");
		goto abort;
	}

	if (temp & GS_PRERR_STS) {
		result = -ENXIO;
		dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
	}

	if (temp & GS_COL_STS) {
		result = -EIO;
		dev_warn(&adap->dev, "SMBus collision!\n");
	}

	if (temp & GS_TO_STS) {
		result = -ETIMEDOUT;
		dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
	}

	if (temp & GS_HCYC_STS)
		dev_dbg(&adap->dev, "SMBus protocol success!\n");

	outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);

#ifdef DEBUG
	if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
		dev_dbg(&adap->dev,
			"Failed reset at end of transaction (%04x)\n", temp);
	}
#endif

	dev_dbg(&adap->dev,
		"Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
		inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
		inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));

	return result;

 abort:
	dev_warn(&adap->dev, "Sending abort\n");
	outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE);
	msleep(100);
	outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
	return -EIO;
}

/* Return negative errno on error. */
static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
		  unsigned short flags, char read_write,
		  u8 command, int size, union i2c_smbus_data * data)
{
	int i, len;
	int status;

	/** TODO: Should I supporte the 10-bit transfers? */
	switch (size) {
	case I2C_SMBUS_PROC_CALL:
		dev_dbg(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
		/* TODO: Well... It is supported, I'm just not sure what to do here... */
		return -EOPNOTSUPP;
	case I2C_SMBUS_QUICK:
		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMB_HOST_ADDRESS);
		size = AMD756_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMB_HOST_ADDRESS);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, SMB_HOST_DATA);
		size = AMD756_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMB_HOST_ADDRESS);
		outb_p(command, SMB_HOST_COMMAND);
		if (read_write == I2C_SMBUS_WRITE)
			outw_p(data->byte, SMB_HOST_DATA);
		size = AMD756_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMB_HOST_ADDRESS);
		outb_p(command, SMB_HOST_COMMAND);
		if (read_write == I2C_SMBUS_WRITE)
			outw_p(data->word, SMB_HOST_DATA);	/* TODO: endian???? */
		size = AMD756_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMB_HOST_ADDRESS);
		outb_p(command, SMB_HOST_COMMAND);
		if (read_write == I2C_SMBUS_WRITE) {
			len = data->block[0];
			if (len < 0)
				len = 0;
			if (len > 32)
				len = 32;
			outw_p(len, SMB_HOST_DATA);
			/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
			for (i = 1; i <= len; i++)
				outb_p(data->block[i],
				       SMB_HOST_BLOCK_DATA);
		}
		size = AMD756_BLOCK_DATA;
		break;
	}

	/* How about enabling interrupts... */
	outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);

	status = amd756_transaction(adap);
	if (status)
		return status;

	if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
		return 0;


	switch (size) {
	case AMD756_BYTE:
		data->byte = inw_p(SMB_HOST_DATA);
		break;
	case AMD756_BYTE_DATA:
		data->byte = inw_p(SMB_HOST_DATA);
		break;
	case AMD756_WORD_DATA:
		data->word = inw_p(SMB_HOST_DATA);	/* TODO: endian???? */
		break;
	case AMD756_BLOCK_DATA:
		data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
		if(data->block[0] > 32)
			data->block[0] = 32;
		/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
		for (i = 1; i <= data->block[0]; i++)
			data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
		break;
	}

	return 0;
}

static u32 amd756_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	    I2C_FUNC_SMBUS_BLOCK_DATA;
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= amd756_access,
	.functionality	= amd756_func,
};

struct i2c_adapter amd756_smbus = {
	.owner		= THIS_MODULE,
	.id		= I2C_HW_SMBUS_AMD756,
	.class          = I2C_CLASS_HWMON,
	.algo		= &smbus_algorithm,
};

enum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 };
static const char* chipname[] = {
	"AMD756", "AMD766", "AMD768",
	"nVidia nForce", "AMD8111",
};

static struct pci_device_id amd756_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
	  .driver_data = AMD756 },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
	  .driver_data = AMD766 },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443),
	  .driver_data = AMD768 },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS),
	  .driver_data = AMD8111 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS),
	  .driver_data = NFORCE },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, amd756_ids);

static int __devinit amd756_probe(struct pci_dev *pdev,
				  const struct pci_device_id *id)
{
	int nforce = (id->driver_data == NFORCE);
	int error;
	u8 temp;
	
	/* driver_data might come from user-space, so check it */
	if (id->driver_data >= ARRAY_SIZE(chipname))
		return -EINVAL;

	if (amd756_ioport) {
		dev_err(&pdev->dev, "Only one device supported "
		       "(you have a strange motherboard, btw)\n");
		return -ENODEV;
	}

	if (nforce) {
		if (PCI_FUNC(pdev->devfn) != 1)
			return -ENODEV;

		pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport);
		amd756_ioport &= 0xfffc;
	} else { /* amd */
		if (PCI_FUNC(pdev->devfn) != 3)
			return -ENODEV;

		pci_read_config_byte(pdev, SMBGCFG, &temp);
		if ((temp & 128) == 0) {
			dev_err(&pdev->dev,
				"Error: SMBus controller I/O not enabled!\n");
			return -ENODEV;
		}

		/* Determine the address of the SMBus areas */
		/* Technically it is a dword but... */
		pci_read_config_word(pdev, SMBBA, &amd756_ioport);
		amd756_ioport &= 0xff00;
		amd756_ioport += SMB_ADDR_OFFSET;
	}

	if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) {
		dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
			amd756_ioport);
		return -ENODEV;
	}

	pci_read_config_byte(pdev, SMBREV, &temp);
	dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
	dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport);

	/* set up the sysfs linkage to our parent device */
	amd756_smbus.dev.parent = &pdev->dev;

	sprintf(amd756_smbus.name, "SMBus %s adapter at %04x",
		chipname[id->driver_data], amd756_ioport);

	error = i2c_add_adapter(&amd756_smbus);
	if (error) {
		dev_err(&pdev->dev,
			"Adapter registration failed, module not inserted\n");
		goto out_err;
	}

	return 0;

 out_err:
	release_region(amd756_ioport, SMB_IOSIZE);
	return error;
}

static void __devexit amd756_remove(struct pci_dev *dev)
{
	i2c_del_adapter(&amd756_smbus);
	release_region(amd756_ioport, SMB_IOSIZE);
}

static struct pci_driver amd756_driver = {
	.name		= "amd756_smbus",
	.id_table	= amd756_ids,
	.probe		= amd756_probe,
	.remove		= __devexit_p(amd756_remove),
	.dynids.use_driver_data = 1,
};

static int __init amd756_init(void)
{
	return pci_register_driver(&amd756_driver);
}

static void __exit amd756_exit(void)
{
	pci_unregister_driver(&amd756_driver);
}

MODULE_AUTHOR("Merlin Hughes <merlin@merlin.org>");
MODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(amd756_smbus);

module_init(amd756_init)
module_exit(amd756_exit)
Commit	Line	Data
1da177e4 LT	1	/*
	2	amd756.c - Part of lm_sensors, Linux kernel modules for hardware
	3	monitoring
	4
	5	Copyright (c) 1999-2002 Merlin Hughes <merlin@merlin.org>
	6
	7	Shamelessly ripped from i2c-piix4.c:
	8
	9	Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl> and
	10	Philip Edelbrock <phil@netroedge.com>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the Free Software
	24	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*/
	26
	27	/*
	28	2002-04-08: Added nForce support. (Csaba Halasz)
	29	2002-10-03: Fixed nForce PnP I/O port. (Michael Steil)
	30	2002-12-28: Rewritten into something that resembles a Linux driver (hch)
	31	2003-11-29: Added back AMD8111 removed by the previous rewrite.
	32	(Philip Pokorny)
	33	*/
	34
	35	/*
	36	Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce
	37	Note: we assume there can only be one device, with one SMBus interface.
	38	*/
	39
1da177e4 LT	40	#include <linux/module.h>
	41	#include <linux/pci.h>
	42	#include <linux/kernel.h>
	43	#include <linux/delay.h>
	44	#include <linux/stddef.h>
1da177e4 LT	45	#include <linux/ioport.h>
	46	#include <linux/i2c.h>
	47	#include <linux/init.h>
	48	#include <asm/io.h>
	49
	50	/* AMD756 SMBus address offsets */
	51	#define SMB_ADDR_OFFSET 0xE0
	52	#define SMB_IOSIZE 16
	53	#define SMB_GLOBAL_STATUS (0x0 + amd756_ioport)
	54	#define SMB_GLOBAL_ENABLE (0x2 + amd756_ioport)
	55	#define SMB_HOST_ADDRESS (0x4 + amd756_ioport)
	56	#define SMB_HOST_DATA (0x6 + amd756_ioport)
	57	#define SMB_HOST_COMMAND (0x8 + amd756_ioport)
	58	#define SMB_HOST_BLOCK_DATA (0x9 + amd756_ioport)
	59	#define SMB_HAS_DATA (0xA + amd756_ioport)
	60	#define SMB_HAS_DEVICE_ADDRESS (0xC + amd756_ioport)
	61	#define SMB_HAS_HOST_ADDRESS (0xE + amd756_ioport)
	62	#define SMB_SNOOP_ADDRESS (0xF + amd756_ioport)
	63
	64	/* PCI Address Constants */
	65
	66	/* address of I/O space */
	67	#define SMBBA 0x058 /* mh */
	68	#define SMBBANFORCE 0x014
	69
	70	/* general configuration */
	71	#define SMBGCFG 0x041 /* mh */
	72
	73	/* silicon revision code */
	74	#define SMBREV 0x008
	75
	76	/* Other settings */
	77	#define MAX_TIMEOUT 500
	78
	79	/* AMD756 constants */
	80	#define AMD756_QUICK 0x00
	81	#define AMD756_BYTE 0x01
	82	#define AMD756_BYTE_DATA 0x02
	83	#define AMD756_WORD_DATA 0x03
	84	#define AMD756_PROCESS_CALL 0x04
	85	#define AMD756_BLOCK_DATA 0x05
	86
d6072f84	87	static struct pci_driver amd756_driver;
60507095	88	static unsigned short amd756_ioport;
1da177e4 LT	89
	90	/*
	91	SMBUS event = I/O 28-29 bit 11
	92	see E0 for the status bits and enabled in E2
	93
	94	*/
	95	#define GS_ABRT_STS (1 << 0)
	96	#define GS_COL_STS (1 << 1)
	97	#define GS_PRERR_STS (1 << 2)
	98	#define GS_HST_STS (1 << 3)
	99	#define GS_HCYC_STS (1 << 4)
	100	#define GS_TO_STS (1 << 5)
	101	#define GS_SMB_STS (1 << 11)
	102
	103	#define GS_CLEAR_STS (GS_ABRT_STS \| GS_COL_STS \| GS_PRERR_STS \| \
	104	GS_HCYC_STS \| GS_TO_STS )
	105
	106	#define GE_CYC_TYPE_MASK (7)
	107	#define GE_HOST_STC (1 << 3)
	108	#define GE_ABORT (1 << 5)
	109
	110
	111	static int amd756_transaction(struct i2c_adapter *adap)
	112	{
	113	int temp;
	114	int result = 0;
	115	int timeout = 0;
	116
	117	dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
	118	"DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
	119	inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
	120	inb_p(SMB_HOST_DATA));
	121
	122	/* Make sure the SMBus host is ready to start transmitting */
	123	if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS \| GS_SMB_STS)) {
	124	dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
	125	do {
	126	msleep(1);
	127	temp = inw_p(SMB_GLOBAL_STATUS);
	128	} while ((temp & (GS_HST_STS \| GS_SMB_STS)) &&
	129	(timeout++ < MAX_TIMEOUT));
	130	/* If the SMBus is still busy, we give up */
	131	if (timeout >= MAX_TIMEOUT) {
	132	dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
	133	goto abort;
	134	}
	135	timeout = 0;
	136	}
	137
	138	/* start the transaction by setting the start bit */
	139	outw_p(inw(SMB_GLOBAL_ENABLE) \| GE_HOST_STC, SMB_GLOBAL_ENABLE);
	140
	141	/* We will always wait for a fraction of a second! */
	142	do {
	143	msleep(1);
	144	temp = inw_p(SMB_GLOBAL_STATUS);
	145	} while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));
	146
	147	/* If the SMBus is still busy, we give up */
	148	if (timeout >= MAX_TIMEOUT) {
	149	dev_dbg(&adap->dev, "Completion timeout!\n");
	150	goto abort;
	151	}
	152
153	if (temp & GS_PRERR_STS) {
97140342	154	result = -ENXIO;
1da177e4 LT	155	dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
	156	}
	157
	158	if (temp & GS_COL_STS) {
97140342	159	result = -EIO;
1da177e4 LT	160	dev_warn(&adap->dev, "SMBus collision!\n");
	161	}
	162
	163	if (temp & GS_TO_STS) {
97140342	164	result = -ETIMEDOUT;
1da177e4 LT	165	dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
	166	}
	167
	168	if (temp & GS_HCYC_STS)
	169	dev_dbg(&adap->dev, "SMBus protocol success!\n");
	170
	171	outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
	172
	173	#ifdef DEBUG
	174	if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
	175	dev_dbg(&adap->dev,
	176	"Failed reset at end of transaction (%04x)\n", temp);
	177	}
	178	#endif
	179
	180	dev_dbg(&adap->dev,
	181	"Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
	182	inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
	183	inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));
	184
	185	return result;
	186
	187	abort:
	188	dev_warn(&adap->dev, "Sending abort\n");
	189	outw_p(inw(SMB_GLOBAL_ENABLE) \| GE_ABORT, SMB_GLOBAL_ENABLE);
	190	msleep(100);
	191	outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
97140342	192	return -EIO;
1da177e4 LT	193	}
1da177e4 LT	194
97140342	195	/* Return negative errno on error. */
1da177e4 LT	196	static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
	197	unsigned short flags, char read_write,
	198	u8 command, int size, union i2c_smbus_data * data)
	199	{
	200	int i, len;
97140342	201	int status;
1da177e4 LT	202
	203	/** TODO: Should I supporte the 10-bit transfers? */
	204	switch (size) {
	205	case I2C_SMBUS_PROC_CALL:
	206	dev_dbg(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
	207	/* TODO: Well... It is supported, I'm just not sure what to do here... */
97140342	208	return -EOPNOTSUPP;
1da177e4 LT	209	case I2C_SMBUS_QUICK:
	210	outw_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	211	SMB_HOST_ADDRESS);
	212	size = AMD756_QUICK;
	213	break;
	214	case I2C_SMBUS_BYTE:
	215	outw_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	216	SMB_HOST_ADDRESS);
	217	if (read_write == I2C_SMBUS_WRITE)
	218	outb_p(command, SMB_HOST_DATA);
	219	size = AMD756_BYTE;
	220	break;
	221	case I2C_SMBUS_BYTE_DATA:
	222	outw_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	223	SMB_HOST_ADDRESS);
	224	outb_p(command, SMB_HOST_COMMAND);
	225	if (read_write == I2C_SMBUS_WRITE)
	226	outw_p(data->byte, SMB_HOST_DATA);
	227	size = AMD756_BYTE_DATA;
	228	break;
	229	case I2C_SMBUS_WORD_DATA:
	230	outw_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	231	SMB_HOST_ADDRESS);
	232	outb_p(command, SMB_HOST_COMMAND);
	233	if (read_write == I2C_SMBUS_WRITE)
	234	outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */
	235	size = AMD756_WORD_DATA;
	236	break;
	237	case I2C_SMBUS_BLOCK_DATA:
	238	outw_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	239	SMB_HOST_ADDRESS);
	240	outb_p(command, SMB_HOST_COMMAND);
	241	if (read_write == I2C_SMBUS_WRITE) {
	242	len = data->block[0];
	243	if (len < 0)
	244	len = 0;
	245	if (len > 32)
	246	len = 32;
	247	outw_p(len, SMB_HOST_DATA);
	248	/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
	249	for (i = 1; i <= len; i++)
	250	outb_p(data->block[i],
	251	SMB_HOST_BLOCK_DATA);
	252	}
	253	size = AMD756_BLOCK_DATA;
	254	break;
	255	}
	256
	257	/* How about enabling interrupts... */
	258	outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
	259
97140342 DB	260	status = amd756_transaction(adap);
	261	if (status)
	262	return status;
1da177e4 LT	263
	264	if ((read_write == I2C_SMBUS_WRITE) \|\| (size == AMD756_QUICK))
	265	return 0;
	266
	267
	268	switch (size) {
	269	case AMD756_BYTE:
	270	data->byte = inw_p(SMB_HOST_DATA);
	271	break;
	272	case AMD756_BYTE_DATA:
	273	data->byte = inw_p(SMB_HOST_DATA);
	274	break;
	275	case AMD756_WORD_DATA:
	276	data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */
	277	break;
	278	case AMD756_BLOCK_DATA:
	279	data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
	280	if(data->block[0] > 32)
	281	data->block[0] = 32;
	282	/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
	283	for (i = 1; i <= data->block[0]; i++)
	284	data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
	285	break;
	286	}
	287
	288	return 0;
	289	}
	290
	291	static u32 amd756_func(struct i2c_adapter *adapter)
	292	{
	293	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	294	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
875b0a47	295	I2C_FUNC_SMBUS_BLOCK_DATA;
1da177e4 LT	296	}
1da177e4 LT	297
8f9082c5	298	static const struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	299	.smbus_xfer = amd756_access,
	300	.functionality = amd756_func,
	301	};
	302
	303	struct i2c_adapter amd756_smbus = {
	304	.owner = THIS_MODULE,
9ace555d	305	.id = I2C_HW_SMBUS_AMD756,
1da177e4 LT	306	.class = I2C_CLASS_HWMON,
1da177e4 LT	307	.algo = &smbus_algorithm,
1da177e4 LT	308	};
	309
	310	enum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 };
	311	static const char* chipname[] = {
	312	"AMD756", "AMD766", "AMD768",
	313	"nVidia nForce", "AMD8111",
	314	};
	315
	316	static struct pci_device_id amd756_ids[] = {
	317	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
	318	.driver_data = AMD756 },
	319	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
	320	.driver_data = AMD766 },
	321	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443),
	322	.driver_data = AMD768 },
	323	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS),
	324	.driver_data = AMD8111 },
	325	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS),
	326	.driver_data = NFORCE },
	327	{ 0, }
	328	};
	329
	330	MODULE_DEVICE_TABLE (pci, amd756_ids);
	331
	332	static int __devinit amd756_probe(struct pci_dev *pdev,
	333	const struct pci_device_id *id)
	334	{
	335	int nforce = (id->driver_data == NFORCE);
	336	int error;
	337	u8 temp;
	338
0f07a24b	339	/* driver_data might come from user-space, so check it */
5edc68b8	340	if (id->driver_data >= ARRAY_SIZE(chipname))
0f07a24b JD	341	return -EINVAL;
0f07a24b JD	342
1da177e4 LT	343	if (amd756_ioport) {
	344	dev_err(&pdev->dev, "Only one device supported "
	345	"(you have a strange motherboard, btw)\n");
	346	return -ENODEV;
	347	}
	348
	349	if (nforce) {
	350	if (PCI_FUNC(pdev->devfn) != 1)
	351	return -ENODEV;
	352
	353	pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport);
	354	amd756_ioport &= 0xfffc;
	355	} else { /* amd */
	356	if (PCI_FUNC(pdev->devfn) != 3)
	357	return -ENODEV;
	358
	359	pci_read_config_byte(pdev, SMBGCFG, &temp);
	360	if ((temp & 128) == 0) {
	361	dev_err(&pdev->dev,
	362	"Error: SMBus controller I/O not enabled!\n");
	363	return -ENODEV;
	364	}
	365
	366	/* Determine the address of the SMBus areas */
	367	/* Technically it is a dword but... */
	368	pci_read_config_word(pdev, SMBBA, &amd756_ioport);
	369	amd756_ioport &= 0xff00;
	370	amd756_ioport += SMB_ADDR_OFFSET;
	371	}
	372
d6072f84	373	if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) {
1da177e4 LT	374	dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
	375	amd756_ioport);
	376	return -ENODEV;
	377	}
	378
	379	pci_read_config_byte(pdev, SMBREV, &temp);
	380	dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
	381	dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport);
	382
405ae7d3	383	/* set up the sysfs linkage to our parent device */
1da177e4 LT	384	amd756_smbus.dev.parent = &pdev->dev;
	385
	386	sprintf(amd756_smbus.name, "SMBus %s adapter at %04x",
	387	chipname[id->driver_data], amd756_ioport);
	388
	389	error = i2c_add_adapter(&amd756_smbus);
	390	if (error) {
	391	dev_err(&pdev->dev,
	392	"Adapter registration failed, module not inserted\n");
	393	goto out_err;
	394	}
	395
	396	return 0;
	397
	398	out_err:
	399	release_region(amd756_ioport, SMB_IOSIZE);
	400	return error;
	401	}
	402
	403	static void __devexit amd756_remove(struct pci_dev *dev)
	404	{
	405	i2c_del_adapter(&amd756_smbus);
	406	release_region(amd756_ioport, SMB_IOSIZE);
	407	}
	408
	409	static struct pci_driver amd756_driver = {
	410	.name = "amd756_smbus",
	411	.id_table = amd756_ids,
	412	.probe = amd756_probe,
	413	.remove = __devexit_p(amd756_remove),
0f07a24b	414	.dynids.use_driver_data = 1,
1da177e4 LT	415	};
	416
	417	static int __init amd756_init(void)
	418	{
	419	return pci_register_driver(&amd756_driver);
	420	}
	421
	422	static void __exit amd756_exit(void)
	423	{
	424	pci_unregister_driver(&amd756_driver);
	425	}
	426
	427	MODULE_AUTHOR("Merlin Hughes <merlin@merlin.org>");
	428	MODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver");
	429	MODULE_LICENSE("GPL");
	430
	431	EXPORT_SYMBOL(amd756_smbus);
	432
	433	module_init(amd756_init)
	434	module_exit(amd756_exit)