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f327c686 BH |
1 | /* |
2 | * Aspeed 24XX/25XX I2C Controller. | |
3 | * | |
4 | * Copyright (C) 2012-2017 ASPEED Technology Inc. | |
5 | * Copyright 2017 IBM Corporation | |
6 | * Copyright 2017 Google, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/irqchip/chained_irq.h> | |
23 | #include <linux/irqdomain.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_platform.h> | |
29 | #include <linux/platform_device.h> | |
edd20e95 | 30 | #include <linux/reset.h> |
f327c686 BH |
31 | #include <linux/slab.h> |
32 | ||
33 | /* I2C Register */ | |
34 | #define ASPEED_I2C_FUN_CTRL_REG 0x00 | |
35 | #define ASPEED_I2C_AC_TIMING_REG1 0x04 | |
36 | #define ASPEED_I2C_AC_TIMING_REG2 0x08 | |
37 | #define ASPEED_I2C_INTR_CTRL_REG 0x0c | |
38 | #define ASPEED_I2C_INTR_STS_REG 0x10 | |
39 | #define ASPEED_I2C_CMD_REG 0x14 | |
40 | #define ASPEED_I2C_DEV_ADDR_REG 0x18 | |
41 | #define ASPEED_I2C_BYTE_BUF_REG 0x20 | |
42 | ||
43 | /* Global Register Definition */ | |
44 | /* 0x00 : I2C Interrupt Status Register */ | |
45 | /* 0x08 : I2C Interrupt Target Assignment */ | |
46 | ||
47 | /* Device Register Definition */ | |
48 | /* 0x00 : I2CD Function Control Register */ | |
49 | #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15) | |
50 | #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8) | |
51 | #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7) | |
52 | #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6) | |
f9eb9135 | 53 | #define ASPEED_I2CD_SLAVE_EN BIT(1) |
f327c686 BH |
54 | #define ASPEED_I2CD_MASTER_EN BIT(0) |
55 | ||
56 | /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ | |
95fd3ad9 AJ |
57 | #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28) |
58 | #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24) | |
59 | #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20) | |
f327c686 BH |
60 | #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16 |
61 | #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) | |
62 | #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 | |
63 | #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) | |
64 | #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) | |
65 | #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) | |
66 | /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ | |
67 | #define ASPEED_NO_TIMEOUT_CTRL 0 | |
68 | ||
69 | /* 0x0c : I2CD Interrupt Control Register & | |
70 | * 0x10 : I2CD Interrupt Status Register | |
71 | * | |
72 | * These share bit definitions, so use the same values for the enable & | |
73 | * status bits. | |
74 | */ | |
75 | #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14) | |
76 | #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13) | |
f9eb9135 | 77 | #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7) |
f327c686 BH |
78 | #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6) |
79 | #define ASPEED_I2CD_INTR_ABNORMAL BIT(5) | |
80 | #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4) | |
81 | #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3) | |
82 | #define ASPEED_I2CD_INTR_RX_DONE BIT(2) | |
83 | #define ASPEED_I2CD_INTR_TX_NAK BIT(1) | |
84 | #define ASPEED_I2CD_INTR_TX_ACK BIT(0) | |
85 | #define ASPEED_I2CD_INTR_ALL \ | |
86 | (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \ | |
87 | ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \ | |
88 | ASPEED_I2CD_INTR_SCL_TIMEOUT | \ | |
89 | ASPEED_I2CD_INTR_ABNORMAL | \ | |
90 | ASPEED_I2CD_INTR_NORMAL_STOP | \ | |
91 | ASPEED_I2CD_INTR_ARBIT_LOSS | \ | |
92 | ASPEED_I2CD_INTR_RX_DONE | \ | |
93 | ASPEED_I2CD_INTR_TX_NAK | \ | |
94 | ASPEED_I2CD_INTR_TX_ACK) | |
95 | ||
96 | /* 0x14 : I2CD Command/Status Register */ | |
97 | #define ASPEED_I2CD_SCL_LINE_STS BIT(18) | |
98 | #define ASPEED_I2CD_SDA_LINE_STS BIT(17) | |
99 | #define ASPEED_I2CD_BUS_BUSY_STS BIT(16) | |
100 | #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11) | |
101 | ||
102 | /* Command Bit */ | |
103 | #define ASPEED_I2CD_M_STOP_CMD BIT(5) | |
104 | #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4) | |
105 | #define ASPEED_I2CD_M_RX_CMD BIT(3) | |
106 | #define ASPEED_I2CD_S_TX_CMD BIT(2) | |
107 | #define ASPEED_I2CD_M_TX_CMD BIT(1) | |
108 | #define ASPEED_I2CD_M_START_CMD BIT(0) | |
109 | ||
f9eb9135 BH |
110 | /* 0x18 : I2CD Slave Device Address Register */ |
111 | #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0) | |
112 | ||
f327c686 BH |
113 | enum aspeed_i2c_master_state { |
114 | ASPEED_I2C_MASTER_START, | |
115 | ASPEED_I2C_MASTER_TX_FIRST, | |
116 | ASPEED_I2C_MASTER_TX, | |
117 | ASPEED_I2C_MASTER_RX_FIRST, | |
118 | ASPEED_I2C_MASTER_RX, | |
119 | ASPEED_I2C_MASTER_STOP, | |
120 | ASPEED_I2C_MASTER_INACTIVE, | |
121 | }; | |
122 | ||
f9eb9135 BH |
123 | enum aspeed_i2c_slave_state { |
124 | ASPEED_I2C_SLAVE_START, | |
125 | ASPEED_I2C_SLAVE_READ_REQUESTED, | |
126 | ASPEED_I2C_SLAVE_READ_PROCESSED, | |
127 | ASPEED_I2C_SLAVE_WRITE_REQUESTED, | |
128 | ASPEED_I2C_SLAVE_WRITE_RECEIVED, | |
129 | ASPEED_I2C_SLAVE_STOP, | |
130 | }; | |
131 | ||
f327c686 BH |
132 | struct aspeed_i2c_bus { |
133 | struct i2c_adapter adap; | |
134 | struct device *dev; | |
135 | void __iomem *base; | |
edd20e95 | 136 | struct reset_control *rst; |
f327c686 BH |
137 | /* Synchronizes I/O mem access to base. */ |
138 | spinlock_t lock; | |
139 | struct completion cmd_complete; | |
87b59ff8 | 140 | u32 (*get_clk_reg_val)(u32 divisor); |
f327c686 BH |
141 | unsigned long parent_clk_frequency; |
142 | u32 bus_frequency; | |
143 | /* Transaction state. */ | |
144 | enum aspeed_i2c_master_state master_state; | |
145 | struct i2c_msg *msgs; | |
146 | size_t buf_index; | |
147 | size_t msgs_index; | |
148 | size_t msgs_count; | |
149 | bool send_stop; | |
150 | int cmd_err; | |
151 | /* Protected only by i2c_lock_bus */ | |
152 | int master_xfer_result; | |
f9eb9135 BH |
153 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
154 | struct i2c_client *slave; | |
155 | enum aspeed_i2c_slave_state slave_state; | |
156 | #endif /* CONFIG_I2C_SLAVE */ | |
f327c686 BH |
157 | }; |
158 | ||
159 | static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus); | |
160 | ||
161 | static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus) | |
162 | { | |
163 | unsigned long time_left, flags; | |
164 | int ret = 0; | |
165 | u32 command; | |
166 | ||
167 | spin_lock_irqsave(&bus->lock, flags); | |
168 | command = readl(bus->base + ASPEED_I2C_CMD_REG); | |
169 | ||
170 | if (command & ASPEED_I2CD_SDA_LINE_STS) { | |
171 | /* Bus is idle: no recovery needed. */ | |
172 | if (command & ASPEED_I2CD_SCL_LINE_STS) | |
173 | goto out; | |
174 | dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n", | |
175 | command); | |
176 | ||
177 | reinit_completion(&bus->cmd_complete); | |
178 | writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); | |
179 | spin_unlock_irqrestore(&bus->lock, flags); | |
180 | ||
181 | time_left = wait_for_completion_timeout( | |
182 | &bus->cmd_complete, bus->adap.timeout); | |
183 | ||
184 | spin_lock_irqsave(&bus->lock, flags); | |
185 | if (time_left == 0) | |
186 | goto reset_out; | |
187 | else if (bus->cmd_err) | |
188 | goto reset_out; | |
189 | /* Recovery failed. */ | |
190 | else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & | |
191 | ASPEED_I2CD_SCL_LINE_STS)) | |
192 | goto reset_out; | |
193 | /* Bus error. */ | |
194 | } else { | |
195 | dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n", | |
196 | command); | |
197 | ||
198 | reinit_completion(&bus->cmd_complete); | |
199 | /* Writes 1 to 8 SCL clock cycles until SDA is released. */ | |
200 | writel(ASPEED_I2CD_BUS_RECOVER_CMD, | |
201 | bus->base + ASPEED_I2C_CMD_REG); | |
202 | spin_unlock_irqrestore(&bus->lock, flags); | |
203 | ||
204 | time_left = wait_for_completion_timeout( | |
205 | &bus->cmd_complete, bus->adap.timeout); | |
206 | ||
207 | spin_lock_irqsave(&bus->lock, flags); | |
208 | if (time_left == 0) | |
209 | goto reset_out; | |
210 | else if (bus->cmd_err) | |
211 | goto reset_out; | |
212 | /* Recovery failed. */ | |
213 | else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & | |
214 | ASPEED_I2CD_SDA_LINE_STS)) | |
215 | goto reset_out; | |
216 | } | |
217 | ||
218 | out: | |
219 | spin_unlock_irqrestore(&bus->lock, flags); | |
220 | ||
221 | return ret; | |
222 | ||
223 | reset_out: | |
224 | spin_unlock_irqrestore(&bus->lock, flags); | |
225 | ||
226 | return aspeed_i2c_reset(bus); | |
227 | } | |
228 | ||
f9eb9135 BH |
229 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
230 | static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus) | |
231 | { | |
232 | u32 command, irq_status, status_ack = 0; | |
233 | struct i2c_client *slave = bus->slave; | |
234 | bool irq_handled = true; | |
235 | u8 value; | |
236 | ||
237 | spin_lock(&bus->lock); | |
238 | if (!slave) { | |
239 | irq_handled = false; | |
240 | goto out; | |
241 | } | |
242 | ||
243 | command = readl(bus->base + ASPEED_I2C_CMD_REG); | |
244 | irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); | |
245 | ||
246 | /* Slave was requested, restart state machine. */ | |
247 | if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) { | |
248 | status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH; | |
249 | bus->slave_state = ASPEED_I2C_SLAVE_START; | |
250 | } | |
251 | ||
252 | /* Slave is not currently active, irq was for someone else. */ | |
253 | if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) { | |
254 | irq_handled = false; | |
255 | goto out; | |
256 | } | |
257 | ||
258 | dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n", | |
259 | irq_status, command); | |
260 | ||
261 | /* Slave was sent something. */ | |
262 | if (irq_status & ASPEED_I2CD_INTR_RX_DONE) { | |
263 | value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; | |
264 | /* Handle address frame. */ | |
265 | if (bus->slave_state == ASPEED_I2C_SLAVE_START) { | |
266 | if (value & 0x1) | |
267 | bus->slave_state = | |
268 | ASPEED_I2C_SLAVE_READ_REQUESTED; | |
269 | else | |
270 | bus->slave_state = | |
271 | ASPEED_I2C_SLAVE_WRITE_REQUESTED; | |
272 | } | |
273 | status_ack |= ASPEED_I2CD_INTR_RX_DONE; | |
274 | } | |
275 | ||
276 | /* Slave was asked to stop. */ | |
277 | if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) { | |
278 | status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; | |
279 | bus->slave_state = ASPEED_I2C_SLAVE_STOP; | |
280 | } | |
281 | if (irq_status & ASPEED_I2CD_INTR_TX_NAK) { | |
282 | status_ack |= ASPEED_I2CD_INTR_TX_NAK; | |
283 | bus->slave_state = ASPEED_I2C_SLAVE_STOP; | |
284 | } | |
285 | ||
286 | switch (bus->slave_state) { | |
287 | case ASPEED_I2C_SLAVE_READ_REQUESTED: | |
288 | if (irq_status & ASPEED_I2CD_INTR_TX_ACK) | |
289 | dev_err(bus->dev, "Unexpected ACK on read request.\n"); | |
290 | bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED; | |
291 | ||
292 | i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); | |
293 | writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); | |
294 | writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); | |
295 | break; | |
296 | case ASPEED_I2C_SLAVE_READ_PROCESSED: | |
297 | status_ack |= ASPEED_I2CD_INTR_TX_ACK; | |
298 | if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK)) | |
299 | dev_err(bus->dev, | |
300 | "Expected ACK after processed read.\n"); | |
301 | i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); | |
302 | writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); | |
303 | writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); | |
304 | break; | |
305 | case ASPEED_I2C_SLAVE_WRITE_REQUESTED: | |
306 | bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED; | |
307 | i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); | |
308 | break; | |
309 | case ASPEED_I2C_SLAVE_WRITE_RECEIVED: | |
310 | i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value); | |
311 | break; | |
312 | case ASPEED_I2C_SLAVE_STOP: | |
313 | i2c_slave_event(slave, I2C_SLAVE_STOP, &value); | |
314 | break; | |
315 | default: | |
316 | dev_err(bus->dev, "unhandled slave_state: %d\n", | |
317 | bus->slave_state); | |
318 | break; | |
319 | } | |
320 | ||
321 | if (status_ack != irq_status) | |
322 | dev_err(bus->dev, | |
323 | "irq handled != irq. expected %x, but was %x\n", | |
324 | irq_status, status_ack); | |
325 | writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG); | |
326 | ||
327 | out: | |
328 | spin_unlock(&bus->lock); | |
329 | return irq_handled; | |
330 | } | |
331 | #endif /* CONFIG_I2C_SLAVE */ | |
332 | ||
f327c686 BH |
333 | /* precondition: bus.lock has been acquired. */ |
334 | static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus) | |
335 | { | |
336 | u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD; | |
337 | struct i2c_msg *msg = &bus->msgs[bus->msgs_index]; | |
338 | u8 slave_addr = msg->addr << 1; | |
339 | ||
340 | bus->master_state = ASPEED_I2C_MASTER_START; | |
341 | bus->buf_index = 0; | |
342 | ||
343 | if (msg->flags & I2C_M_RD) { | |
344 | slave_addr |= 1; | |
345 | command |= ASPEED_I2CD_M_RX_CMD; | |
346 | /* Need to let the hardware know to NACK after RX. */ | |
347 | if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) | |
348 | command |= ASPEED_I2CD_M_S_RX_CMD_LAST; | |
349 | } | |
350 | ||
351 | writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG); | |
352 | writel(command, bus->base + ASPEED_I2C_CMD_REG); | |
353 | } | |
354 | ||
355 | /* precondition: bus.lock has been acquired. */ | |
356 | static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus) | |
357 | { | |
358 | bus->master_state = ASPEED_I2C_MASTER_STOP; | |
359 | writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); | |
360 | } | |
361 | ||
362 | /* precondition: bus.lock has been acquired. */ | |
363 | static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus) | |
364 | { | |
365 | if (bus->msgs_index + 1 < bus->msgs_count) { | |
366 | bus->msgs_index++; | |
367 | aspeed_i2c_do_start(bus); | |
368 | } else { | |
369 | aspeed_i2c_do_stop(bus); | |
370 | } | |
371 | } | |
372 | ||
373 | static int aspeed_i2c_is_irq_error(u32 irq_status) | |
374 | { | |
375 | if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS) | |
376 | return -EAGAIN; | |
377 | if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | | |
378 | ASPEED_I2CD_INTR_SCL_TIMEOUT)) | |
379 | return -EBUSY; | |
380 | if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL)) | |
381 | return -EPROTO; | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus) | |
387 | { | |
388 | u32 irq_status, status_ack = 0, command = 0; | |
389 | struct i2c_msg *msg; | |
390 | u8 recv_byte; | |
391 | int ret; | |
392 | ||
393 | spin_lock(&bus->lock); | |
394 | irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); | |
395 | /* Ack all interrupt bits. */ | |
396 | writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG); | |
397 | ||
398 | if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) { | |
399 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
400 | status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE; | |
401 | goto out_complete; | |
402 | } | |
403 | ||
404 | /* | |
405 | * We encountered an interrupt that reports an error: the hardware | |
406 | * should clear the command queue effectively taking us back to the | |
407 | * INACTIVE state. | |
408 | */ | |
409 | ret = aspeed_i2c_is_irq_error(irq_status); | |
410 | if (ret < 0) { | |
411 | dev_dbg(bus->dev, "received error interrupt: 0x%08x", | |
412 | irq_status); | |
413 | bus->cmd_err = ret; | |
414 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
415 | goto out_complete; | |
416 | } | |
417 | ||
418 | /* We are in an invalid state; reset bus to a known state. */ | |
f1c0b7e4 | 419 | if (!bus->msgs) { |
f327c686 BH |
420 | dev_err(bus->dev, "bus in unknown state"); |
421 | bus->cmd_err = -EIO; | |
f1c0b7e4 BH |
422 | if (bus->master_state != ASPEED_I2C_MASTER_STOP) |
423 | aspeed_i2c_do_stop(bus); | |
f327c686 BH |
424 | goto out_no_complete; |
425 | } | |
426 | msg = &bus->msgs[bus->msgs_index]; | |
427 | ||
428 | /* | |
429 | * START is a special case because we still have to handle a subsequent | |
430 | * TX or RX immediately after we handle it, so we handle it here and | |
431 | * then update the state and handle the new state below. | |
432 | */ | |
433 | if (bus->master_state == ASPEED_I2C_MASTER_START) { | |
434 | if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { | |
435 | pr_devel("no slave present at %02x", msg->addr); | |
436 | status_ack |= ASPEED_I2CD_INTR_TX_NAK; | |
437 | bus->cmd_err = -ENXIO; | |
438 | aspeed_i2c_do_stop(bus); | |
439 | goto out_no_complete; | |
440 | } | |
441 | status_ack |= ASPEED_I2CD_INTR_TX_ACK; | |
442 | if (msg->len == 0) { /* SMBUS_QUICK */ | |
443 | aspeed_i2c_do_stop(bus); | |
444 | goto out_no_complete; | |
445 | } | |
446 | if (msg->flags & I2C_M_RD) | |
447 | bus->master_state = ASPEED_I2C_MASTER_RX_FIRST; | |
448 | else | |
449 | bus->master_state = ASPEED_I2C_MASTER_TX_FIRST; | |
450 | } | |
451 | ||
452 | switch (bus->master_state) { | |
453 | case ASPEED_I2C_MASTER_TX: | |
454 | if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) { | |
455 | dev_dbg(bus->dev, "slave NACKed TX"); | |
456 | status_ack |= ASPEED_I2CD_INTR_TX_NAK; | |
457 | goto error_and_stop; | |
458 | } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { | |
459 | dev_err(bus->dev, "slave failed to ACK TX"); | |
460 | goto error_and_stop; | |
461 | } | |
462 | status_ack |= ASPEED_I2CD_INTR_TX_ACK; | |
463 | /* fallthrough intended */ | |
464 | case ASPEED_I2C_MASTER_TX_FIRST: | |
465 | if (bus->buf_index < msg->len) { | |
466 | bus->master_state = ASPEED_I2C_MASTER_TX; | |
467 | writel(msg->buf[bus->buf_index++], | |
468 | bus->base + ASPEED_I2C_BYTE_BUF_REG); | |
469 | writel(ASPEED_I2CD_M_TX_CMD, | |
470 | bus->base + ASPEED_I2C_CMD_REG); | |
471 | } else { | |
472 | aspeed_i2c_next_msg_or_stop(bus); | |
473 | } | |
474 | goto out_no_complete; | |
475 | case ASPEED_I2C_MASTER_RX_FIRST: | |
476 | /* RX may not have completed yet (only address cycle) */ | |
477 | if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE)) | |
478 | goto out_no_complete; | |
479 | /* fallthrough intended */ | |
480 | case ASPEED_I2C_MASTER_RX: | |
481 | if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) { | |
482 | dev_err(bus->dev, "master failed to RX"); | |
483 | goto error_and_stop; | |
484 | } | |
485 | status_ack |= ASPEED_I2CD_INTR_RX_DONE; | |
486 | ||
487 | recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; | |
488 | msg->buf[bus->buf_index++] = recv_byte; | |
489 | ||
490 | if (msg->flags & I2C_M_RECV_LEN) { | |
491 | if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) { | |
492 | bus->cmd_err = -EPROTO; | |
493 | aspeed_i2c_do_stop(bus); | |
494 | goto out_no_complete; | |
495 | } | |
496 | msg->len = recv_byte + | |
497 | ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1); | |
498 | msg->flags &= ~I2C_M_RECV_LEN; | |
499 | } | |
500 | ||
501 | if (bus->buf_index < msg->len) { | |
502 | bus->master_state = ASPEED_I2C_MASTER_RX; | |
503 | command = ASPEED_I2CD_M_RX_CMD; | |
504 | if (bus->buf_index + 1 == msg->len) | |
505 | command |= ASPEED_I2CD_M_S_RX_CMD_LAST; | |
506 | writel(command, bus->base + ASPEED_I2C_CMD_REG); | |
507 | } else { | |
508 | aspeed_i2c_next_msg_or_stop(bus); | |
509 | } | |
510 | goto out_no_complete; | |
511 | case ASPEED_I2C_MASTER_STOP: | |
512 | if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) { | |
513 | dev_err(bus->dev, "master failed to STOP"); | |
514 | bus->cmd_err = -EIO; | |
515 | /* Do not STOP as we have already tried. */ | |
516 | } else { | |
517 | status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; | |
518 | } | |
519 | ||
520 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
521 | goto out_complete; | |
522 | case ASPEED_I2C_MASTER_INACTIVE: | |
523 | dev_err(bus->dev, | |
524 | "master received interrupt 0x%08x, but is inactive", | |
525 | irq_status); | |
526 | bus->cmd_err = -EIO; | |
527 | /* Do not STOP as we should be inactive. */ | |
528 | goto out_complete; | |
529 | default: | |
530 | WARN(1, "unknown master state\n"); | |
531 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
532 | bus->cmd_err = -EINVAL; | |
533 | goto out_complete; | |
534 | } | |
535 | error_and_stop: | |
536 | bus->cmd_err = -EIO; | |
537 | aspeed_i2c_do_stop(bus); | |
538 | goto out_no_complete; | |
539 | out_complete: | |
540 | bus->msgs = NULL; | |
541 | if (bus->cmd_err) | |
542 | bus->master_xfer_result = bus->cmd_err; | |
543 | else | |
544 | bus->master_xfer_result = bus->msgs_index + 1; | |
545 | complete(&bus->cmd_complete); | |
546 | out_no_complete: | |
547 | if (irq_status != status_ack) | |
548 | dev_err(bus->dev, | |
549 | "irq handled != irq. expected 0x%08x, but was 0x%08x\n", | |
550 | irq_status, status_ack); | |
551 | spin_unlock(&bus->lock); | |
552 | return !!irq_status; | |
553 | } | |
554 | ||
555 | static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) | |
556 | { | |
557 | struct aspeed_i2c_bus *bus = dev_id; | |
558 | ||
f9eb9135 BH |
559 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
560 | if (aspeed_i2c_slave_irq(bus)) { | |
561 | dev_dbg(bus->dev, "irq handled by slave.\n"); | |
562 | return IRQ_HANDLED; | |
563 | } | |
564 | #endif /* CONFIG_I2C_SLAVE */ | |
565 | ||
f327c686 BH |
566 | return aspeed_i2c_master_irq(bus) ? IRQ_HANDLED : IRQ_NONE; |
567 | } | |
568 | ||
569 | static int aspeed_i2c_master_xfer(struct i2c_adapter *adap, | |
570 | struct i2c_msg *msgs, int num) | |
571 | { | |
572 | struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap); | |
573 | unsigned long time_left, flags; | |
574 | int ret = 0; | |
575 | ||
576 | spin_lock_irqsave(&bus->lock, flags); | |
577 | bus->cmd_err = 0; | |
578 | ||
579 | /* If bus is busy, attempt recovery. We assume a single master | |
580 | * environment. | |
581 | */ | |
582 | if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) { | |
583 | spin_unlock_irqrestore(&bus->lock, flags); | |
584 | ret = aspeed_i2c_recover_bus(bus); | |
585 | if (ret) | |
586 | return ret; | |
587 | spin_lock_irqsave(&bus->lock, flags); | |
588 | } | |
589 | ||
590 | bus->cmd_err = 0; | |
591 | bus->msgs = msgs; | |
592 | bus->msgs_index = 0; | |
593 | bus->msgs_count = num; | |
594 | ||
595 | reinit_completion(&bus->cmd_complete); | |
596 | aspeed_i2c_do_start(bus); | |
597 | spin_unlock_irqrestore(&bus->lock, flags); | |
598 | ||
599 | time_left = wait_for_completion_timeout(&bus->cmd_complete, | |
600 | bus->adap.timeout); | |
601 | ||
602 | if (time_left == 0) | |
603 | return -ETIMEDOUT; | |
604 | else | |
605 | return bus->master_xfer_result; | |
606 | } | |
607 | ||
608 | static u32 aspeed_i2c_functionality(struct i2c_adapter *adap) | |
609 | { | |
610 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; | |
611 | } | |
612 | ||
f9eb9135 BH |
613 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
614 | /* precondition: bus.lock has been acquired. */ | |
615 | static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr) | |
616 | { | |
617 | u32 addr_reg_val, func_ctrl_reg_val; | |
618 | ||
619 | /* Set slave addr. */ | |
620 | addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG); | |
621 | addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK; | |
622 | addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK; | |
623 | writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG); | |
624 | ||
625 | /* Turn on slave mode. */ | |
626 | func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
627 | func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN; | |
628 | writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
629 | } | |
630 | ||
631 | static int aspeed_i2c_reg_slave(struct i2c_client *client) | |
632 | { | |
633 | struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter); | |
634 | unsigned long flags; | |
635 | ||
636 | spin_lock_irqsave(&bus->lock, flags); | |
637 | if (bus->slave) { | |
638 | spin_unlock_irqrestore(&bus->lock, flags); | |
639 | return -EINVAL; | |
640 | } | |
641 | ||
642 | __aspeed_i2c_reg_slave(bus, client->addr); | |
643 | ||
644 | bus->slave = client; | |
645 | bus->slave_state = ASPEED_I2C_SLAVE_STOP; | |
646 | spin_unlock_irqrestore(&bus->lock, flags); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static int aspeed_i2c_unreg_slave(struct i2c_client *client) | |
652 | { | |
653 | struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter); | |
654 | u32 func_ctrl_reg_val; | |
655 | unsigned long flags; | |
656 | ||
657 | spin_lock_irqsave(&bus->lock, flags); | |
658 | if (!bus->slave) { | |
659 | spin_unlock_irqrestore(&bus->lock, flags); | |
660 | return -EINVAL; | |
661 | } | |
662 | ||
663 | /* Turn off slave mode. */ | |
664 | func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
665 | func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN; | |
666 | writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
667 | ||
668 | bus->slave = NULL; | |
669 | spin_unlock_irqrestore(&bus->lock, flags); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | #endif /* CONFIG_I2C_SLAVE */ | |
674 | ||
f327c686 BH |
675 | static const struct i2c_algorithm aspeed_i2c_algo = { |
676 | .master_xfer = aspeed_i2c_master_xfer, | |
677 | .functionality = aspeed_i2c_functionality, | |
f9eb9135 BH |
678 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
679 | .reg_slave = aspeed_i2c_reg_slave, | |
680 | .unreg_slave = aspeed_i2c_unreg_slave, | |
681 | #endif /* CONFIG_I2C_SLAVE */ | |
f327c686 BH |
682 | }; |
683 | ||
87b59ff8 | 684 | static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor) |
f327c686 BH |
685 | { |
686 | u32 base_clk, clk_high, clk_low, tmp; | |
687 | ||
688 | /* | |
689 | * The actual clock frequency of SCL is: | |
690 | * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low)) | |
691 | * = APB_freq / divisor | |
692 | * where base_freq is a programmable clock divider; its value is | |
693 | * base_freq = 1 << base_clk | |
694 | * SCL_high is the number of base_freq clock cycles that SCL stays high | |
695 | * and SCL_low is the number of base_freq clock cycles that SCL stays | |
696 | * low for a period of SCL. | |
697 | * The actual register has a minimum SCL_high and SCL_low minimum of 1; | |
698 | * thus, they start counting at zero. So | |
699 | * SCL_high = clk_high + 1 | |
700 | * SCL_low = clk_low + 1 | |
701 | * Thus, | |
702 | * SCL_freq = APB_freq / | |
703 | * ((1 << base_clk) * (clk_high + 1 + clk_low + 1)) | |
87b59ff8 BH |
704 | * The documentation recommends clk_high >= clk_high_max / 2 and |
705 | * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint | |
706 | * gives us the following solution: | |
f327c686 | 707 | */ |
87b59ff8 BH |
708 | base_clk = divisor > clk_high_low_max ? |
709 | ilog2((divisor - 1) / clk_high_low_max) + 1 : 0; | |
710 | tmp = (divisor + (1 << base_clk) - 1) >> base_clk; | |
711 | clk_low = tmp / 2; | |
712 | clk_high = tmp - clk_low; | |
713 | ||
714 | if (clk_high) | |
715 | clk_high--; | |
716 | ||
717 | if (clk_low) | |
718 | clk_low--; | |
f327c686 | 719 | |
f327c686 BH |
720 | |
721 | return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) | |
722 | & ASPEED_I2CD_TIME_SCL_HIGH_MASK) | |
723 | | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT) | |
724 | & ASPEED_I2CD_TIME_SCL_LOW_MASK) | |
725 | | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK); | |
726 | } | |
727 | ||
87b59ff8 BH |
728 | static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor) |
729 | { | |
730 | /* | |
731 | * clk_high and clk_low are each 3 bits wide, so each can hold a max | |
732 | * value of 8 giving a clk_high_low_max of 16. | |
733 | */ | |
734 | return aspeed_i2c_get_clk_reg_val(16, divisor); | |
735 | } | |
736 | ||
737 | static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor) | |
738 | { | |
739 | /* | |
740 | * clk_high and clk_low are each 4 bits wide, so each can hold a max | |
741 | * value of 16 giving a clk_high_low_max of 32. | |
742 | */ | |
743 | return aspeed_i2c_get_clk_reg_val(32, divisor); | |
744 | } | |
745 | ||
f327c686 BH |
746 | /* precondition: bus.lock has been acquired. */ |
747 | static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) | |
748 | { | |
749 | u32 divisor, clk_reg_val; | |
750 | ||
87b59ff8 | 751 | divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency); |
95fd3ad9 AJ |
752 | clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); |
753 | clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | | |
754 | ASPEED_I2CD_TIME_THDSTA_MASK | | |
755 | ASPEED_I2CD_TIME_TACST_MASK); | |
756 | clk_reg_val |= bus->get_clk_reg_val(divisor); | |
f327c686 BH |
757 | writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); |
758 | writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | /* precondition: bus.lock has been acquired. */ | |
764 | static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, | |
765 | struct platform_device *pdev) | |
766 | { | |
767 | u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN; | |
768 | int ret; | |
769 | ||
770 | /* Disable everything. */ | |
771 | writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
772 | ||
773 | ret = aspeed_i2c_init_clk(bus); | |
774 | if (ret < 0) | |
775 | return ret; | |
776 | ||
777 | if (!of_property_read_bool(pdev->dev.of_node, "multi-master")) | |
778 | fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS; | |
779 | ||
780 | /* Enable Master Mode */ | |
781 | writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg, | |
782 | bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
783 | ||
f9eb9135 BH |
784 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
785 | /* If slave has already been registered, re-enable it. */ | |
786 | if (bus->slave) | |
787 | __aspeed_i2c_reg_slave(bus, bus->slave->addr); | |
788 | #endif /* CONFIG_I2C_SLAVE */ | |
789 | ||
f327c686 BH |
790 | /* Set interrupt generation of I2C controller */ |
791 | writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus) | |
797 | { | |
798 | struct platform_device *pdev = to_platform_device(bus->dev); | |
799 | unsigned long flags; | |
800 | int ret; | |
801 | ||
802 | spin_lock_irqsave(&bus->lock, flags); | |
803 | ||
804 | /* Disable and ack all interrupts. */ | |
805 | writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
806 | writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); | |
807 | ||
808 | ret = aspeed_i2c_init(bus, pdev); | |
809 | ||
810 | spin_unlock_irqrestore(&bus->lock, flags); | |
811 | ||
812 | return ret; | |
813 | } | |
814 | ||
87b59ff8 BH |
815 | static const struct of_device_id aspeed_i2c_bus_of_table[] = { |
816 | { | |
817 | .compatible = "aspeed,ast2400-i2c-bus", | |
818 | .data = aspeed_i2c_24xx_get_clk_reg_val, | |
819 | }, | |
820 | { | |
821 | .compatible = "aspeed,ast2500-i2c-bus", | |
822 | .data = aspeed_i2c_25xx_get_clk_reg_val, | |
823 | }, | |
824 | { }, | |
825 | }; | |
826 | MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); | |
827 | ||
f327c686 BH |
828 | static int aspeed_i2c_probe_bus(struct platform_device *pdev) |
829 | { | |
87b59ff8 | 830 | const struct of_device_id *match; |
f327c686 BH |
831 | struct aspeed_i2c_bus *bus; |
832 | struct clk *parent_clk; | |
833 | struct resource *res; | |
834 | int irq, ret; | |
835 | ||
836 | bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); | |
837 | if (!bus) | |
838 | return -ENOMEM; | |
839 | ||
840 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
841 | bus->base = devm_ioremap_resource(&pdev->dev, res); | |
842 | if (IS_ERR(bus->base)) | |
843 | return PTR_ERR(bus->base); | |
844 | ||
845 | parent_clk = devm_clk_get(&pdev->dev, NULL); | |
846 | if (IS_ERR(parent_clk)) | |
847 | return PTR_ERR(parent_clk); | |
848 | bus->parent_clk_frequency = clk_get_rate(parent_clk); | |
849 | /* We just need the clock rate, we don't actually use the clk object. */ | |
850 | devm_clk_put(&pdev->dev, parent_clk); | |
851 | ||
edd20e95 JS |
852 | bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL); |
853 | if (IS_ERR(bus->rst)) { | |
854 | dev_err(&pdev->dev, | |
855 | "missing or invalid reset controller device tree entry"); | |
856 | return PTR_ERR(bus->rst); | |
857 | } | |
858 | reset_control_deassert(bus->rst); | |
859 | ||
f327c686 BH |
860 | ret = of_property_read_u32(pdev->dev.of_node, |
861 | "bus-frequency", &bus->bus_frequency); | |
862 | if (ret < 0) { | |
863 | dev_err(&pdev->dev, | |
864 | "Could not read bus-frequency property\n"); | |
865 | bus->bus_frequency = 100000; | |
866 | } | |
867 | ||
87b59ff8 BH |
868 | match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node); |
869 | if (!match) | |
870 | bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val; | |
871 | else | |
872 | bus->get_clk_reg_val = match->data; | |
873 | ||
f327c686 BH |
874 | /* Initialize the I2C adapter */ |
875 | spin_lock_init(&bus->lock); | |
876 | init_completion(&bus->cmd_complete); | |
877 | bus->adap.owner = THIS_MODULE; | |
878 | bus->adap.retries = 0; | |
879 | bus->adap.timeout = 5 * HZ; | |
880 | bus->adap.algo = &aspeed_i2c_algo; | |
881 | bus->adap.dev.parent = &pdev->dev; | |
882 | bus->adap.dev.of_node = pdev->dev.of_node; | |
883 | strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); | |
884 | i2c_set_adapdata(&bus->adap, bus); | |
885 | ||
886 | bus->dev = &pdev->dev; | |
887 | ||
888 | /* Clean up any left over interrupt state. */ | |
889 | writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
890 | writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); | |
891 | /* | |
892 | * bus.lock does not need to be held because the interrupt handler has | |
893 | * not been enabled yet. | |
894 | */ | |
895 | ret = aspeed_i2c_init(bus, pdev); | |
896 | if (ret < 0) | |
897 | return ret; | |
898 | ||
899 | irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
900 | ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq, | |
901 | 0, dev_name(&pdev->dev), bus); | |
902 | if (ret < 0) | |
903 | return ret; | |
904 | ||
905 | ret = i2c_add_adapter(&bus->adap); | |
906 | if (ret < 0) | |
907 | return ret; | |
908 | ||
909 | platform_set_drvdata(pdev, bus); | |
910 | ||
911 | dev_info(bus->dev, "i2c bus %d registered, irq %d\n", | |
912 | bus->adap.nr, irq); | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static int aspeed_i2c_remove_bus(struct platform_device *pdev) | |
918 | { | |
919 | struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev); | |
920 | unsigned long flags; | |
921 | ||
922 | spin_lock_irqsave(&bus->lock, flags); | |
923 | ||
924 | /* Disable everything. */ | |
925 | writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
926 | writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
927 | ||
928 | spin_unlock_irqrestore(&bus->lock, flags); | |
929 | ||
edd20e95 JS |
930 | reset_control_assert(bus->rst); |
931 | ||
f327c686 BH |
932 | i2c_del_adapter(&bus->adap); |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
f327c686 BH |
937 | static struct platform_driver aspeed_i2c_bus_driver = { |
938 | .probe = aspeed_i2c_probe_bus, | |
939 | .remove = aspeed_i2c_remove_bus, | |
940 | .driver = { | |
941 | .name = "aspeed-i2c-bus", | |
942 | .of_match_table = aspeed_i2c_bus_of_table, | |
943 | }, | |
944 | }; | |
945 | module_platform_driver(aspeed_i2c_bus_driver); | |
946 | ||
947 | MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>"); | |
948 | MODULE_DESCRIPTION("Aspeed I2C Bus Driver"); | |
949 | MODULE_LICENSE("GPL v2"); |