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f327c686 BH |
1 | /* |
2 | * Aspeed 24XX/25XX I2C Controller. | |
3 | * | |
4 | * Copyright (C) 2012-2017 ASPEED Technology Inc. | |
5 | * Copyright 2017 IBM Corporation | |
6 | * Copyright 2017 Google, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/irqchip/chained_irq.h> | |
23 | #include <linux/irqdomain.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_platform.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/slab.h> | |
31 | ||
32 | /* I2C Register */ | |
33 | #define ASPEED_I2C_FUN_CTRL_REG 0x00 | |
34 | #define ASPEED_I2C_AC_TIMING_REG1 0x04 | |
35 | #define ASPEED_I2C_AC_TIMING_REG2 0x08 | |
36 | #define ASPEED_I2C_INTR_CTRL_REG 0x0c | |
37 | #define ASPEED_I2C_INTR_STS_REG 0x10 | |
38 | #define ASPEED_I2C_CMD_REG 0x14 | |
39 | #define ASPEED_I2C_DEV_ADDR_REG 0x18 | |
40 | #define ASPEED_I2C_BYTE_BUF_REG 0x20 | |
41 | ||
42 | /* Global Register Definition */ | |
43 | /* 0x00 : I2C Interrupt Status Register */ | |
44 | /* 0x08 : I2C Interrupt Target Assignment */ | |
45 | ||
46 | /* Device Register Definition */ | |
47 | /* 0x00 : I2CD Function Control Register */ | |
48 | #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15) | |
49 | #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8) | |
50 | #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7) | |
51 | #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6) | |
52 | #define ASPEED_I2CD_MASTER_EN BIT(0) | |
53 | ||
54 | /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ | |
55 | #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16 | |
56 | #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) | |
57 | #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 | |
58 | #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) | |
59 | #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) | |
60 | #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) | |
61 | /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ | |
62 | #define ASPEED_NO_TIMEOUT_CTRL 0 | |
63 | ||
64 | /* 0x0c : I2CD Interrupt Control Register & | |
65 | * 0x10 : I2CD Interrupt Status Register | |
66 | * | |
67 | * These share bit definitions, so use the same values for the enable & | |
68 | * status bits. | |
69 | */ | |
70 | #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14) | |
71 | #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13) | |
72 | #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6) | |
73 | #define ASPEED_I2CD_INTR_ABNORMAL BIT(5) | |
74 | #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4) | |
75 | #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3) | |
76 | #define ASPEED_I2CD_INTR_RX_DONE BIT(2) | |
77 | #define ASPEED_I2CD_INTR_TX_NAK BIT(1) | |
78 | #define ASPEED_I2CD_INTR_TX_ACK BIT(0) | |
79 | #define ASPEED_I2CD_INTR_ALL \ | |
80 | (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \ | |
81 | ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \ | |
82 | ASPEED_I2CD_INTR_SCL_TIMEOUT | \ | |
83 | ASPEED_I2CD_INTR_ABNORMAL | \ | |
84 | ASPEED_I2CD_INTR_NORMAL_STOP | \ | |
85 | ASPEED_I2CD_INTR_ARBIT_LOSS | \ | |
86 | ASPEED_I2CD_INTR_RX_DONE | \ | |
87 | ASPEED_I2CD_INTR_TX_NAK | \ | |
88 | ASPEED_I2CD_INTR_TX_ACK) | |
89 | ||
90 | /* 0x14 : I2CD Command/Status Register */ | |
91 | #define ASPEED_I2CD_SCL_LINE_STS BIT(18) | |
92 | #define ASPEED_I2CD_SDA_LINE_STS BIT(17) | |
93 | #define ASPEED_I2CD_BUS_BUSY_STS BIT(16) | |
94 | #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11) | |
95 | ||
96 | /* Command Bit */ | |
97 | #define ASPEED_I2CD_M_STOP_CMD BIT(5) | |
98 | #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4) | |
99 | #define ASPEED_I2CD_M_RX_CMD BIT(3) | |
100 | #define ASPEED_I2CD_S_TX_CMD BIT(2) | |
101 | #define ASPEED_I2CD_M_TX_CMD BIT(1) | |
102 | #define ASPEED_I2CD_M_START_CMD BIT(0) | |
103 | ||
104 | enum aspeed_i2c_master_state { | |
105 | ASPEED_I2C_MASTER_START, | |
106 | ASPEED_I2C_MASTER_TX_FIRST, | |
107 | ASPEED_I2C_MASTER_TX, | |
108 | ASPEED_I2C_MASTER_RX_FIRST, | |
109 | ASPEED_I2C_MASTER_RX, | |
110 | ASPEED_I2C_MASTER_STOP, | |
111 | ASPEED_I2C_MASTER_INACTIVE, | |
112 | }; | |
113 | ||
114 | struct aspeed_i2c_bus { | |
115 | struct i2c_adapter adap; | |
116 | struct device *dev; | |
117 | void __iomem *base; | |
118 | /* Synchronizes I/O mem access to base. */ | |
119 | spinlock_t lock; | |
120 | struct completion cmd_complete; | |
121 | unsigned long parent_clk_frequency; | |
122 | u32 bus_frequency; | |
123 | /* Transaction state. */ | |
124 | enum aspeed_i2c_master_state master_state; | |
125 | struct i2c_msg *msgs; | |
126 | size_t buf_index; | |
127 | size_t msgs_index; | |
128 | size_t msgs_count; | |
129 | bool send_stop; | |
130 | int cmd_err; | |
131 | /* Protected only by i2c_lock_bus */ | |
132 | int master_xfer_result; | |
133 | }; | |
134 | ||
135 | static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus); | |
136 | ||
137 | static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus) | |
138 | { | |
139 | unsigned long time_left, flags; | |
140 | int ret = 0; | |
141 | u32 command; | |
142 | ||
143 | spin_lock_irqsave(&bus->lock, flags); | |
144 | command = readl(bus->base + ASPEED_I2C_CMD_REG); | |
145 | ||
146 | if (command & ASPEED_I2CD_SDA_LINE_STS) { | |
147 | /* Bus is idle: no recovery needed. */ | |
148 | if (command & ASPEED_I2CD_SCL_LINE_STS) | |
149 | goto out; | |
150 | dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n", | |
151 | command); | |
152 | ||
153 | reinit_completion(&bus->cmd_complete); | |
154 | writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); | |
155 | spin_unlock_irqrestore(&bus->lock, flags); | |
156 | ||
157 | time_left = wait_for_completion_timeout( | |
158 | &bus->cmd_complete, bus->adap.timeout); | |
159 | ||
160 | spin_lock_irqsave(&bus->lock, flags); | |
161 | if (time_left == 0) | |
162 | goto reset_out; | |
163 | else if (bus->cmd_err) | |
164 | goto reset_out; | |
165 | /* Recovery failed. */ | |
166 | else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & | |
167 | ASPEED_I2CD_SCL_LINE_STS)) | |
168 | goto reset_out; | |
169 | /* Bus error. */ | |
170 | } else { | |
171 | dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n", | |
172 | command); | |
173 | ||
174 | reinit_completion(&bus->cmd_complete); | |
175 | /* Writes 1 to 8 SCL clock cycles until SDA is released. */ | |
176 | writel(ASPEED_I2CD_BUS_RECOVER_CMD, | |
177 | bus->base + ASPEED_I2C_CMD_REG); | |
178 | spin_unlock_irqrestore(&bus->lock, flags); | |
179 | ||
180 | time_left = wait_for_completion_timeout( | |
181 | &bus->cmd_complete, bus->adap.timeout); | |
182 | ||
183 | spin_lock_irqsave(&bus->lock, flags); | |
184 | if (time_left == 0) | |
185 | goto reset_out; | |
186 | else if (bus->cmd_err) | |
187 | goto reset_out; | |
188 | /* Recovery failed. */ | |
189 | else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & | |
190 | ASPEED_I2CD_SDA_LINE_STS)) | |
191 | goto reset_out; | |
192 | } | |
193 | ||
194 | out: | |
195 | spin_unlock_irqrestore(&bus->lock, flags); | |
196 | ||
197 | return ret; | |
198 | ||
199 | reset_out: | |
200 | spin_unlock_irqrestore(&bus->lock, flags); | |
201 | ||
202 | return aspeed_i2c_reset(bus); | |
203 | } | |
204 | ||
205 | /* precondition: bus.lock has been acquired. */ | |
206 | static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus) | |
207 | { | |
208 | u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD; | |
209 | struct i2c_msg *msg = &bus->msgs[bus->msgs_index]; | |
210 | u8 slave_addr = msg->addr << 1; | |
211 | ||
212 | bus->master_state = ASPEED_I2C_MASTER_START; | |
213 | bus->buf_index = 0; | |
214 | ||
215 | if (msg->flags & I2C_M_RD) { | |
216 | slave_addr |= 1; | |
217 | command |= ASPEED_I2CD_M_RX_CMD; | |
218 | /* Need to let the hardware know to NACK after RX. */ | |
219 | if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) | |
220 | command |= ASPEED_I2CD_M_S_RX_CMD_LAST; | |
221 | } | |
222 | ||
223 | writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG); | |
224 | writel(command, bus->base + ASPEED_I2C_CMD_REG); | |
225 | } | |
226 | ||
227 | /* precondition: bus.lock has been acquired. */ | |
228 | static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus) | |
229 | { | |
230 | bus->master_state = ASPEED_I2C_MASTER_STOP; | |
231 | writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); | |
232 | } | |
233 | ||
234 | /* precondition: bus.lock has been acquired. */ | |
235 | static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus) | |
236 | { | |
237 | if (bus->msgs_index + 1 < bus->msgs_count) { | |
238 | bus->msgs_index++; | |
239 | aspeed_i2c_do_start(bus); | |
240 | } else { | |
241 | aspeed_i2c_do_stop(bus); | |
242 | } | |
243 | } | |
244 | ||
245 | static int aspeed_i2c_is_irq_error(u32 irq_status) | |
246 | { | |
247 | if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS) | |
248 | return -EAGAIN; | |
249 | if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | | |
250 | ASPEED_I2CD_INTR_SCL_TIMEOUT)) | |
251 | return -EBUSY; | |
252 | if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL)) | |
253 | return -EPROTO; | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
258 | static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus) | |
259 | { | |
260 | u32 irq_status, status_ack = 0, command = 0; | |
261 | struct i2c_msg *msg; | |
262 | u8 recv_byte; | |
263 | int ret; | |
264 | ||
265 | spin_lock(&bus->lock); | |
266 | irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); | |
267 | /* Ack all interrupt bits. */ | |
268 | writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG); | |
269 | ||
270 | if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) { | |
271 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
272 | status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE; | |
273 | goto out_complete; | |
274 | } | |
275 | ||
276 | /* | |
277 | * We encountered an interrupt that reports an error: the hardware | |
278 | * should clear the command queue effectively taking us back to the | |
279 | * INACTIVE state. | |
280 | */ | |
281 | ret = aspeed_i2c_is_irq_error(irq_status); | |
282 | if (ret < 0) { | |
283 | dev_dbg(bus->dev, "received error interrupt: 0x%08x", | |
284 | irq_status); | |
285 | bus->cmd_err = ret; | |
286 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
287 | goto out_complete; | |
288 | } | |
289 | ||
290 | /* We are in an invalid state; reset bus to a known state. */ | |
291 | if (!bus->msgs && bus->master_state != ASPEED_I2C_MASTER_STOP) { | |
292 | dev_err(bus->dev, "bus in unknown state"); | |
293 | bus->cmd_err = -EIO; | |
294 | aspeed_i2c_do_stop(bus); | |
295 | goto out_no_complete; | |
296 | } | |
297 | msg = &bus->msgs[bus->msgs_index]; | |
298 | ||
299 | /* | |
300 | * START is a special case because we still have to handle a subsequent | |
301 | * TX or RX immediately after we handle it, so we handle it here and | |
302 | * then update the state and handle the new state below. | |
303 | */ | |
304 | if (bus->master_state == ASPEED_I2C_MASTER_START) { | |
305 | if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { | |
306 | pr_devel("no slave present at %02x", msg->addr); | |
307 | status_ack |= ASPEED_I2CD_INTR_TX_NAK; | |
308 | bus->cmd_err = -ENXIO; | |
309 | aspeed_i2c_do_stop(bus); | |
310 | goto out_no_complete; | |
311 | } | |
312 | status_ack |= ASPEED_I2CD_INTR_TX_ACK; | |
313 | if (msg->len == 0) { /* SMBUS_QUICK */ | |
314 | aspeed_i2c_do_stop(bus); | |
315 | goto out_no_complete; | |
316 | } | |
317 | if (msg->flags & I2C_M_RD) | |
318 | bus->master_state = ASPEED_I2C_MASTER_RX_FIRST; | |
319 | else | |
320 | bus->master_state = ASPEED_I2C_MASTER_TX_FIRST; | |
321 | } | |
322 | ||
323 | switch (bus->master_state) { | |
324 | case ASPEED_I2C_MASTER_TX: | |
325 | if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) { | |
326 | dev_dbg(bus->dev, "slave NACKed TX"); | |
327 | status_ack |= ASPEED_I2CD_INTR_TX_NAK; | |
328 | goto error_and_stop; | |
329 | } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { | |
330 | dev_err(bus->dev, "slave failed to ACK TX"); | |
331 | goto error_and_stop; | |
332 | } | |
333 | status_ack |= ASPEED_I2CD_INTR_TX_ACK; | |
334 | /* fallthrough intended */ | |
335 | case ASPEED_I2C_MASTER_TX_FIRST: | |
336 | if (bus->buf_index < msg->len) { | |
337 | bus->master_state = ASPEED_I2C_MASTER_TX; | |
338 | writel(msg->buf[bus->buf_index++], | |
339 | bus->base + ASPEED_I2C_BYTE_BUF_REG); | |
340 | writel(ASPEED_I2CD_M_TX_CMD, | |
341 | bus->base + ASPEED_I2C_CMD_REG); | |
342 | } else { | |
343 | aspeed_i2c_next_msg_or_stop(bus); | |
344 | } | |
345 | goto out_no_complete; | |
346 | case ASPEED_I2C_MASTER_RX_FIRST: | |
347 | /* RX may not have completed yet (only address cycle) */ | |
348 | if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE)) | |
349 | goto out_no_complete; | |
350 | /* fallthrough intended */ | |
351 | case ASPEED_I2C_MASTER_RX: | |
352 | if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) { | |
353 | dev_err(bus->dev, "master failed to RX"); | |
354 | goto error_and_stop; | |
355 | } | |
356 | status_ack |= ASPEED_I2CD_INTR_RX_DONE; | |
357 | ||
358 | recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; | |
359 | msg->buf[bus->buf_index++] = recv_byte; | |
360 | ||
361 | if (msg->flags & I2C_M_RECV_LEN) { | |
362 | if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) { | |
363 | bus->cmd_err = -EPROTO; | |
364 | aspeed_i2c_do_stop(bus); | |
365 | goto out_no_complete; | |
366 | } | |
367 | msg->len = recv_byte + | |
368 | ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1); | |
369 | msg->flags &= ~I2C_M_RECV_LEN; | |
370 | } | |
371 | ||
372 | if (bus->buf_index < msg->len) { | |
373 | bus->master_state = ASPEED_I2C_MASTER_RX; | |
374 | command = ASPEED_I2CD_M_RX_CMD; | |
375 | if (bus->buf_index + 1 == msg->len) | |
376 | command |= ASPEED_I2CD_M_S_RX_CMD_LAST; | |
377 | writel(command, bus->base + ASPEED_I2C_CMD_REG); | |
378 | } else { | |
379 | aspeed_i2c_next_msg_or_stop(bus); | |
380 | } | |
381 | goto out_no_complete; | |
382 | case ASPEED_I2C_MASTER_STOP: | |
383 | if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) { | |
384 | dev_err(bus->dev, "master failed to STOP"); | |
385 | bus->cmd_err = -EIO; | |
386 | /* Do not STOP as we have already tried. */ | |
387 | } else { | |
388 | status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; | |
389 | } | |
390 | ||
391 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
392 | goto out_complete; | |
393 | case ASPEED_I2C_MASTER_INACTIVE: | |
394 | dev_err(bus->dev, | |
395 | "master received interrupt 0x%08x, but is inactive", | |
396 | irq_status); | |
397 | bus->cmd_err = -EIO; | |
398 | /* Do not STOP as we should be inactive. */ | |
399 | goto out_complete; | |
400 | default: | |
401 | WARN(1, "unknown master state\n"); | |
402 | bus->master_state = ASPEED_I2C_MASTER_INACTIVE; | |
403 | bus->cmd_err = -EINVAL; | |
404 | goto out_complete; | |
405 | } | |
406 | error_and_stop: | |
407 | bus->cmd_err = -EIO; | |
408 | aspeed_i2c_do_stop(bus); | |
409 | goto out_no_complete; | |
410 | out_complete: | |
411 | bus->msgs = NULL; | |
412 | if (bus->cmd_err) | |
413 | bus->master_xfer_result = bus->cmd_err; | |
414 | else | |
415 | bus->master_xfer_result = bus->msgs_index + 1; | |
416 | complete(&bus->cmd_complete); | |
417 | out_no_complete: | |
418 | if (irq_status != status_ack) | |
419 | dev_err(bus->dev, | |
420 | "irq handled != irq. expected 0x%08x, but was 0x%08x\n", | |
421 | irq_status, status_ack); | |
422 | spin_unlock(&bus->lock); | |
423 | return !!irq_status; | |
424 | } | |
425 | ||
426 | static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) | |
427 | { | |
428 | struct aspeed_i2c_bus *bus = dev_id; | |
429 | ||
430 | return aspeed_i2c_master_irq(bus) ? IRQ_HANDLED : IRQ_NONE; | |
431 | } | |
432 | ||
433 | static int aspeed_i2c_master_xfer(struct i2c_adapter *adap, | |
434 | struct i2c_msg *msgs, int num) | |
435 | { | |
436 | struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap); | |
437 | unsigned long time_left, flags; | |
438 | int ret = 0; | |
439 | ||
440 | spin_lock_irqsave(&bus->lock, flags); | |
441 | bus->cmd_err = 0; | |
442 | ||
443 | /* If bus is busy, attempt recovery. We assume a single master | |
444 | * environment. | |
445 | */ | |
446 | if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) { | |
447 | spin_unlock_irqrestore(&bus->lock, flags); | |
448 | ret = aspeed_i2c_recover_bus(bus); | |
449 | if (ret) | |
450 | return ret; | |
451 | spin_lock_irqsave(&bus->lock, flags); | |
452 | } | |
453 | ||
454 | bus->cmd_err = 0; | |
455 | bus->msgs = msgs; | |
456 | bus->msgs_index = 0; | |
457 | bus->msgs_count = num; | |
458 | ||
459 | reinit_completion(&bus->cmd_complete); | |
460 | aspeed_i2c_do_start(bus); | |
461 | spin_unlock_irqrestore(&bus->lock, flags); | |
462 | ||
463 | time_left = wait_for_completion_timeout(&bus->cmd_complete, | |
464 | bus->adap.timeout); | |
465 | ||
466 | if (time_left == 0) | |
467 | return -ETIMEDOUT; | |
468 | else | |
469 | return bus->master_xfer_result; | |
470 | } | |
471 | ||
472 | static u32 aspeed_i2c_functionality(struct i2c_adapter *adap) | |
473 | { | |
474 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; | |
475 | } | |
476 | ||
477 | static const struct i2c_algorithm aspeed_i2c_algo = { | |
478 | .master_xfer = aspeed_i2c_master_xfer, | |
479 | .functionality = aspeed_i2c_functionality, | |
480 | }; | |
481 | ||
482 | static u32 aspeed_i2c_get_clk_reg_val(u32 divisor) | |
483 | { | |
484 | u32 base_clk, clk_high, clk_low, tmp; | |
485 | ||
486 | /* | |
487 | * The actual clock frequency of SCL is: | |
488 | * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low)) | |
489 | * = APB_freq / divisor | |
490 | * where base_freq is a programmable clock divider; its value is | |
491 | * base_freq = 1 << base_clk | |
492 | * SCL_high is the number of base_freq clock cycles that SCL stays high | |
493 | * and SCL_low is the number of base_freq clock cycles that SCL stays | |
494 | * low for a period of SCL. | |
495 | * The actual register has a minimum SCL_high and SCL_low minimum of 1; | |
496 | * thus, they start counting at zero. So | |
497 | * SCL_high = clk_high + 1 | |
498 | * SCL_low = clk_low + 1 | |
499 | * Thus, | |
500 | * SCL_freq = APB_freq / | |
501 | * ((1 << base_clk) * (clk_high + 1 + clk_low + 1)) | |
502 | * The documentation recommends clk_high >= 8 and clk_low >= 7 when | |
503 | * possible; this last constraint gives us the following solution: | |
504 | */ | |
505 | base_clk = divisor > 33 ? ilog2((divisor - 1) / 32) + 1 : 0; | |
506 | tmp = divisor / (1 << base_clk); | |
507 | clk_high = tmp / 2 + tmp % 2; | |
508 | clk_low = tmp - clk_high; | |
509 | ||
510 | clk_high -= 1; | |
511 | clk_low -= 1; | |
512 | ||
513 | return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) | |
514 | & ASPEED_I2CD_TIME_SCL_HIGH_MASK) | |
515 | | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT) | |
516 | & ASPEED_I2CD_TIME_SCL_LOW_MASK) | |
517 | | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK); | |
518 | } | |
519 | ||
520 | /* precondition: bus.lock has been acquired. */ | |
521 | static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) | |
522 | { | |
523 | u32 divisor, clk_reg_val; | |
524 | ||
525 | divisor = bus->parent_clk_frequency / bus->bus_frequency; | |
526 | clk_reg_val = aspeed_i2c_get_clk_reg_val(divisor); | |
527 | writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); | |
528 | writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
533 | /* precondition: bus.lock has been acquired. */ | |
534 | static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, | |
535 | struct platform_device *pdev) | |
536 | { | |
537 | u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN; | |
538 | int ret; | |
539 | ||
540 | /* Disable everything. */ | |
541 | writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
542 | ||
543 | ret = aspeed_i2c_init_clk(bus); | |
544 | if (ret < 0) | |
545 | return ret; | |
546 | ||
547 | if (!of_property_read_bool(pdev->dev.of_node, "multi-master")) | |
548 | fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS; | |
549 | ||
550 | /* Enable Master Mode */ | |
551 | writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg, | |
552 | bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
553 | ||
554 | /* Set interrupt generation of I2C controller */ | |
555 | writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus) | |
561 | { | |
562 | struct platform_device *pdev = to_platform_device(bus->dev); | |
563 | unsigned long flags; | |
564 | int ret; | |
565 | ||
566 | spin_lock_irqsave(&bus->lock, flags); | |
567 | ||
568 | /* Disable and ack all interrupts. */ | |
569 | writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
570 | writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); | |
571 | ||
572 | ret = aspeed_i2c_init(bus, pdev); | |
573 | ||
574 | spin_unlock_irqrestore(&bus->lock, flags); | |
575 | ||
576 | return ret; | |
577 | } | |
578 | ||
579 | static int aspeed_i2c_probe_bus(struct platform_device *pdev) | |
580 | { | |
581 | struct aspeed_i2c_bus *bus; | |
582 | struct clk *parent_clk; | |
583 | struct resource *res; | |
584 | int irq, ret; | |
585 | ||
586 | bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); | |
587 | if (!bus) | |
588 | return -ENOMEM; | |
589 | ||
590 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
591 | bus->base = devm_ioremap_resource(&pdev->dev, res); | |
592 | if (IS_ERR(bus->base)) | |
593 | return PTR_ERR(bus->base); | |
594 | ||
595 | parent_clk = devm_clk_get(&pdev->dev, NULL); | |
596 | if (IS_ERR(parent_clk)) | |
597 | return PTR_ERR(parent_clk); | |
598 | bus->parent_clk_frequency = clk_get_rate(parent_clk); | |
599 | /* We just need the clock rate, we don't actually use the clk object. */ | |
600 | devm_clk_put(&pdev->dev, parent_clk); | |
601 | ||
602 | ret = of_property_read_u32(pdev->dev.of_node, | |
603 | "bus-frequency", &bus->bus_frequency); | |
604 | if (ret < 0) { | |
605 | dev_err(&pdev->dev, | |
606 | "Could not read bus-frequency property\n"); | |
607 | bus->bus_frequency = 100000; | |
608 | } | |
609 | ||
610 | /* Initialize the I2C adapter */ | |
611 | spin_lock_init(&bus->lock); | |
612 | init_completion(&bus->cmd_complete); | |
613 | bus->adap.owner = THIS_MODULE; | |
614 | bus->adap.retries = 0; | |
615 | bus->adap.timeout = 5 * HZ; | |
616 | bus->adap.algo = &aspeed_i2c_algo; | |
617 | bus->adap.dev.parent = &pdev->dev; | |
618 | bus->adap.dev.of_node = pdev->dev.of_node; | |
619 | strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); | |
620 | i2c_set_adapdata(&bus->adap, bus); | |
621 | ||
622 | bus->dev = &pdev->dev; | |
623 | ||
624 | /* Clean up any left over interrupt state. */ | |
625 | writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
626 | writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); | |
627 | /* | |
628 | * bus.lock does not need to be held because the interrupt handler has | |
629 | * not been enabled yet. | |
630 | */ | |
631 | ret = aspeed_i2c_init(bus, pdev); | |
632 | if (ret < 0) | |
633 | return ret; | |
634 | ||
635 | irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
636 | ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq, | |
637 | 0, dev_name(&pdev->dev), bus); | |
638 | if (ret < 0) | |
639 | return ret; | |
640 | ||
641 | ret = i2c_add_adapter(&bus->adap); | |
642 | if (ret < 0) | |
643 | return ret; | |
644 | ||
645 | platform_set_drvdata(pdev, bus); | |
646 | ||
647 | dev_info(bus->dev, "i2c bus %d registered, irq %d\n", | |
648 | bus->adap.nr, irq); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | static int aspeed_i2c_remove_bus(struct platform_device *pdev) | |
654 | { | |
655 | struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev); | |
656 | unsigned long flags; | |
657 | ||
658 | spin_lock_irqsave(&bus->lock, flags); | |
659 | ||
660 | /* Disable everything. */ | |
661 | writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); | |
662 | writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); | |
663 | ||
664 | spin_unlock_irqrestore(&bus->lock, flags); | |
665 | ||
666 | i2c_del_adapter(&bus->adap); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static const struct of_device_id aspeed_i2c_bus_of_table[] = { | |
672 | { .compatible = "aspeed,ast2400-i2c-bus", }, | |
673 | { .compatible = "aspeed,ast2500-i2c-bus", }, | |
674 | { }, | |
675 | }; | |
676 | MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); | |
677 | ||
678 | static struct platform_driver aspeed_i2c_bus_driver = { | |
679 | .probe = aspeed_i2c_probe_bus, | |
680 | .remove = aspeed_i2c_remove_bus, | |
681 | .driver = { | |
682 | .name = "aspeed-i2c-bus", | |
683 | .of_match_table = aspeed_i2c_bus_of_table, | |
684 | }, | |
685 | }; | |
686 | module_platform_driver(aspeed_i2c_bus_driver); | |
687 | ||
688 | MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>"); | |
689 | MODULE_DESCRIPTION("Aspeed I2C Bus Driver"); | |
690 | MODULE_LICENSE("GPL v2"); |