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fac368a0 NV |
1 | /* |
2 | * i2c Support for Atmel's AT91 Two-Wire Interface (TWI) | |
3 | * | |
4 | * Copyright (C) 2011 Weinmann Medical GmbH | |
5 | * Author: Nikolaus Voss <n.voss@weinmann.de> | |
6 | * | |
7 | * Evolved from original work by: | |
8 | * Copyright (C) 2004 Rick Bronson | |
9 | * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com> | |
10 | * | |
11 | * Borrowed heavily from original work by: | |
12 | * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #include <linux/clk.h> | |
21 | #include <linux/completion.h> | |
60937b2c LD |
22 | #include <linux/dma-mapping.h> |
23 | #include <linux/dmaengine.h> | |
fac368a0 NV |
24 | #include <linux/err.h> |
25 | #include <linux/i2c.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
70d46a24 LD |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
fac368a0 NV |
31 | #include <linux/platform_device.h> |
32 | #include <linux/slab.h> | |
60937b2c | 33 | #include <linux/platform_data/dma-atmel.h> |
d64a8188 | 34 | #include <linux/pm_runtime.h> |
62d10c40 | 35 | #include <linux/pinctrl/consumer.h> |
fac368a0 | 36 | |
75b6c4b6 | 37 | #define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */ |
fac368a0 | 38 | #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ |
60937b2c | 39 | #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */ |
d64a8188 | 40 | #define AUTOSUSPEND_TIMEOUT 2000 |
fac368a0 NV |
41 | |
42 | /* AT91 TWI register definitions */ | |
43 | #define AT91_TWI_CR 0x0000 /* Control Register */ | |
e84cf8f0 CP |
44 | #define AT91_TWI_START BIT(0) /* Send a Start Condition */ |
45 | #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */ | |
46 | #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */ | |
47 | #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */ | |
48 | #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */ | |
49 | #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */ | |
50 | #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */ | |
51 | #define AT91_TWI_SWRST BIT(7) /* Software Reset */ | |
0ef6f321 CP |
52 | #define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */ |
53 | #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */ | |
54 | #define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */ | |
55 | #define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */ | |
56 | #define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */ | |
5e3cfc6c CP |
57 | #define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */ |
58 | #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */ | |
fac368a0 NV |
59 | |
60 | #define AT91_TWI_MMR 0x0004 /* Master Mode Register */ | |
61 | #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ | |
e84cf8f0 | 62 | #define AT91_TWI_MREAD BIT(12) /* Master Read Direction */ |
fac368a0 NV |
63 | |
64 | #define AT91_TWI_IADR 0x000c /* Internal Address Register */ | |
65 | ||
66 | #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ | |
cc018e36 LD |
67 | #define AT91_TWI_CWGR_HOLD_MAX 0x1f |
68 | #define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24) | |
fac368a0 NV |
69 | |
70 | #define AT91_TWI_SR 0x0020 /* Status Register */ | |
e84cf8f0 CP |
71 | #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */ |
72 | #define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */ | |
73 | #define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */ | |
74 | #define AT91_TWI_OVRE BIT(6) /* Overrun Error */ | |
75 | #define AT91_TWI_UNRE BIT(7) /* Underrun Error */ | |
76 | #define AT91_TWI_NACK BIT(8) /* Not Acknowledged */ | |
0ef6f321 | 77 | #define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */ |
fac368a0 | 78 | |
93563a6a CP |
79 | #define AT91_TWI_INT_MASK \ |
80 | (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK) | |
81 | ||
fac368a0 NV |
82 | #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ |
83 | #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ | |
84 | #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */ | |
85 | #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ | |
86 | #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ | |
87 | ||
0ef6f321 CP |
88 | #define AT91_TWI_ACR 0x0040 /* Alternative Command Register */ |
89 | #define AT91_TWI_ACR_DATAL(len) ((len) & 0xff) | |
90 | #define AT91_TWI_ACR_DIR BIT(8) | |
91 | ||
5e3cfc6c CP |
92 | #define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */ |
93 | #define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0) | |
94 | #define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0) | |
95 | #define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4) | |
96 | #define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4) | |
97 | #define AT91_TWI_ONE_DATA 0x0 | |
98 | #define AT91_TWI_TWO_DATA 0x1 | |
99 | #define AT91_TWI_FOUR_DATA 0x2 | |
100 | ||
101 | #define AT91_TWI_FLR 0x0054 /* FIFO Level Register */ | |
102 | ||
103 | #define AT91_TWI_FSR 0x0060 /* FIFO Status Register */ | |
104 | #define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */ | |
105 | #define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */ | |
106 | #define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */ | |
107 | ||
6ce461ea CP |
108 | #define AT91_TWI_VER 0x00fc /* Version Register */ |
109 | ||
fac368a0 | 110 | struct at91_twi_pdata { |
5f433819 LD |
111 | unsigned clk_max_div; |
112 | unsigned clk_offset; | |
113 | bool has_unre_flag; | |
0ef6f321 | 114 | bool has_alt_cmd; |
cc018e36 | 115 | bool has_hold_field; |
60937b2c LD |
116 | struct at_dma_slave dma_slave; |
117 | }; | |
118 | ||
119 | struct at91_twi_dma { | |
120 | struct dma_chan *chan_rx; | |
121 | struct dma_chan *chan_tx; | |
5e3cfc6c | 122 | struct scatterlist sg[2]; |
60937b2c LD |
123 | struct dma_async_tx_descriptor *data_desc; |
124 | enum dma_data_direction direction; | |
125 | bool buf_mapped; | |
126 | bool xfer_in_progress; | |
fac368a0 NV |
127 | }; |
128 | ||
129 | struct at91_twi_dev { | |
5f433819 LD |
130 | struct device *dev; |
131 | void __iomem *base; | |
132 | struct completion cmd_complete; | |
133 | struct clk *clk; | |
134 | u8 *buf; | |
135 | size_t buf_len; | |
136 | struct i2c_msg *msg; | |
137 | int irq; | |
60937b2c | 138 | unsigned imr; |
5f433819 LD |
139 | unsigned transfer_status; |
140 | struct i2c_adapter adapter; | |
141 | unsigned twi_cwgr_reg; | |
142 | struct at91_twi_pdata *pdata; | |
60937b2c | 143 | bool use_dma; |
75b81f33 | 144 | bool recv_len_abort; |
5e3cfc6c | 145 | u32 fifo_size; |
60937b2c | 146 | struct at91_twi_dma dma; |
fac368a0 NV |
147 | }; |
148 | ||
149 | static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) | |
150 | { | |
151 | return readl_relaxed(dev->base + reg); | |
152 | } | |
153 | ||
154 | static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) | |
155 | { | |
156 | writel_relaxed(val, dev->base + reg); | |
157 | } | |
158 | ||
159 | static void at91_disable_twi_interrupts(struct at91_twi_dev *dev) | |
160 | { | |
93563a6a | 161 | at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK); |
fac368a0 NV |
162 | } |
163 | ||
60937b2c LD |
164 | static void at91_twi_irq_save(struct at91_twi_dev *dev) |
165 | { | |
93563a6a | 166 | dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK; |
60937b2c LD |
167 | at91_disable_twi_interrupts(dev); |
168 | } | |
169 | ||
170 | static void at91_twi_irq_restore(struct at91_twi_dev *dev) | |
171 | { | |
172 | at91_twi_write(dev, AT91_TWI_IER, dev->imr); | |
173 | } | |
174 | ||
fac368a0 NV |
175 | static void at91_init_twi_bus(struct at91_twi_dev *dev) |
176 | { | |
177 | at91_disable_twi_interrupts(dev); | |
178 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST); | |
5e3cfc6c CP |
179 | /* FIFO should be enabled immediately after the software reset */ |
180 | if (dev->fifo_size) | |
181 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN); | |
fac368a0 NV |
182 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN); |
183 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS); | |
184 | at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); | |
185 | } | |
186 | ||
187 | /* | |
188 | * Calculate symmetric clock as stated in datasheet: | |
189 | * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) | |
190 | */ | |
0b255e92 | 191 | static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) |
fac368a0 | 192 | { |
cc018e36 | 193 | int ckdiv, cdiv, div, hold = 0; |
fac368a0 NV |
194 | struct at91_twi_pdata *pdata = dev->pdata; |
195 | int offset = pdata->clk_offset; | |
196 | int max_ckdiv = pdata->clk_max_div; | |
cc018e36 | 197 | u32 twd_hold_time_ns = 0; |
fac368a0 NV |
198 | |
199 | div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), | |
200 | 2 * twi_clk) - offset); | |
201 | ckdiv = fls(div >> 8); | |
202 | cdiv = div >> ckdiv; | |
203 | ||
204 | if (ckdiv > max_ckdiv) { | |
205 | dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n", | |
206 | ckdiv, max_ckdiv); | |
207 | ckdiv = max_ckdiv; | |
208 | cdiv = 255; | |
209 | } | |
210 | ||
cc018e36 LD |
211 | if (pdata->has_hold_field) { |
212 | of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns", | |
213 | &twd_hold_time_ns); | |
214 | ||
215 | /* | |
216 | * hold time = HOLD + 3 x T_peripheral_clock | |
217 | * Use clk rate in kHz to prevent overflows when computing | |
218 | * hold. | |
219 | */ | |
220 | hold = DIV_ROUND_UP(twd_hold_time_ns | |
221 | * (clk_get_rate(dev->clk) / 1000), 1000000); | |
222 | hold -= 3; | |
223 | if (hold < 0) | |
224 | hold = 0; | |
225 | if (hold > AT91_TWI_CWGR_HOLD_MAX) { | |
226 | dev_warn(dev->dev, | |
227 | "HOLD field set to its maximum value (%d instead of %d)\n", | |
228 | AT91_TWI_CWGR_HOLD_MAX, hold); | |
229 | hold = AT91_TWI_CWGR_HOLD_MAX; | |
230 | } | |
231 | } | |
232 | ||
233 | dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv | |
234 | | AT91_TWI_CWGR_HOLD(hold); | |
235 | ||
236 | dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n", | |
237 | cdiv, ckdiv, hold, twd_hold_time_ns); | |
fac368a0 NV |
238 | } |
239 | ||
60937b2c LD |
240 | static void at91_twi_dma_cleanup(struct at91_twi_dev *dev) |
241 | { | |
242 | struct at91_twi_dma *dma = &dev->dma; | |
243 | ||
244 | at91_twi_irq_save(dev); | |
245 | ||
246 | if (dma->xfer_in_progress) { | |
247 | if (dma->direction == DMA_FROM_DEVICE) | |
248 | dmaengine_terminate_all(dma->chan_rx); | |
249 | else | |
250 | dmaengine_terminate_all(dma->chan_tx); | |
251 | dma->xfer_in_progress = false; | |
252 | } | |
253 | if (dma->buf_mapped) { | |
5e3cfc6c | 254 | dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]), |
60937b2c LD |
255 | dev->buf_len, dma->direction); |
256 | dma->buf_mapped = false; | |
257 | } | |
258 | ||
259 | at91_twi_irq_restore(dev); | |
260 | } | |
261 | ||
fac368a0 NV |
262 | static void at91_twi_write_next_byte(struct at91_twi_dev *dev) |
263 | { | |
f30dc520 | 264 | if (!dev->buf_len) |
fac368a0 NV |
265 | return; |
266 | ||
5e3cfc6c CP |
267 | /* 8bit write works with and without FIFO */ |
268 | writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR); | |
fac368a0 NV |
269 | |
270 | /* send stop when last byte has been written */ | |
271 | if (--dev->buf_len == 0) | |
0ef6f321 CP |
272 | if (!dev->pdata->has_alt_cmd) |
273 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
fac368a0 NV |
274 | |
275 | dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
276 | ||
277 | ++dev->buf; | |
278 | } | |
279 | ||
60937b2c LD |
280 | static void at91_twi_write_data_dma_callback(void *data) |
281 | { | |
282 | struct at91_twi_dev *dev = (struct at91_twi_dev *)data; | |
283 | ||
5e3cfc6c | 284 | dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]), |
28772ac8 | 285 | dev->buf_len, DMA_TO_DEVICE); |
60937b2c | 286 | |
93563a6a CP |
287 | /* |
288 | * When this callback is called, THR/TX FIFO is likely not to be empty | |
289 | * yet. So we have to wait for TXCOMP or NACK bits to be set into the | |
290 | * Status Register to be sure that the STOP bit has been sent and the | |
291 | * transfer is completed. The NACK interrupt has already been enabled, | |
292 | * we just have to enable TXCOMP one. | |
293 | */ | |
294 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
0ef6f321 CP |
295 | if (!dev->pdata->has_alt_cmd) |
296 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
60937b2c LD |
297 | } |
298 | ||
299 | static void at91_twi_write_data_dma(struct at91_twi_dev *dev) | |
300 | { | |
301 | dma_addr_t dma_addr; | |
302 | struct dma_async_tx_descriptor *txdesc; | |
303 | struct at91_twi_dma *dma = &dev->dma; | |
304 | struct dma_chan *chan_tx = dma->chan_tx; | |
5e3cfc6c | 305 | unsigned int sg_len = 1; |
60937b2c | 306 | |
f30dc520 | 307 | if (!dev->buf_len) |
60937b2c LD |
308 | return; |
309 | ||
310 | dma->direction = DMA_TO_DEVICE; | |
311 | ||
312 | at91_twi_irq_save(dev); | |
313 | dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len, | |
314 | DMA_TO_DEVICE); | |
315 | if (dma_mapping_error(dev->dev, dma_addr)) { | |
316 | dev_err(dev->dev, "dma map failed\n"); | |
317 | return; | |
318 | } | |
319 | dma->buf_mapped = true; | |
320 | at91_twi_irq_restore(dev); | |
60937b2c | 321 | |
5e3cfc6c CP |
322 | if (dev->fifo_size) { |
323 | size_t part1_len, part2_len; | |
324 | struct scatterlist *sg; | |
325 | unsigned fifo_mr; | |
326 | ||
327 | sg_len = 0; | |
328 | ||
329 | part1_len = dev->buf_len & ~0x3; | |
330 | if (part1_len) { | |
331 | sg = &dma->sg[sg_len++]; | |
332 | sg_dma_len(sg) = part1_len; | |
333 | sg_dma_address(sg) = dma_addr; | |
334 | } | |
335 | ||
336 | part2_len = dev->buf_len & 0x3; | |
337 | if (part2_len) { | |
338 | sg = &dma->sg[sg_len++]; | |
339 | sg_dma_len(sg) = part2_len; | |
340 | sg_dma_address(sg) = dma_addr + part1_len; | |
341 | } | |
342 | ||
343 | /* | |
344 | * DMA controller is triggered when at least 4 data can be | |
345 | * written into the TX FIFO | |
346 | */ | |
347 | fifo_mr = at91_twi_read(dev, AT91_TWI_FMR); | |
348 | fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK; | |
349 | fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA); | |
350 | at91_twi_write(dev, AT91_TWI_FMR, fifo_mr); | |
351 | } else { | |
352 | sg_dma_len(&dma->sg[0]) = dev->buf_len; | |
353 | sg_dma_address(&dma->sg[0]) = dma_addr; | |
354 | } | |
355 | ||
356 | txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len, | |
357 | DMA_MEM_TO_DEV, | |
60937b2c LD |
358 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
359 | if (!txdesc) { | |
360 | dev_err(dev->dev, "dma prep slave sg failed\n"); | |
361 | goto error; | |
362 | } | |
363 | ||
364 | txdesc->callback = at91_twi_write_data_dma_callback; | |
365 | txdesc->callback_param = dev; | |
366 | ||
367 | dma->xfer_in_progress = true; | |
368 | dmaengine_submit(txdesc); | |
369 | dma_async_issue_pending(chan_tx); | |
370 | ||
371 | return; | |
372 | ||
373 | error: | |
374 | at91_twi_dma_cleanup(dev); | |
375 | } | |
376 | ||
fac368a0 NV |
377 | static void at91_twi_read_next_byte(struct at91_twi_dev *dev) |
378 | { | |
a9bed6b1 LD |
379 | /* |
380 | * If we are in this case, it means there is garbage data in RHR, so | |
381 | * delete them. | |
382 | */ | |
383 | if (!dev->buf_len) { | |
384 | at91_twi_read(dev, AT91_TWI_RHR); | |
fac368a0 | 385 | return; |
a9bed6b1 | 386 | } |
fac368a0 | 387 | |
5e3cfc6c CP |
388 | /* 8bit read works with and without FIFO */ |
389 | *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR); | |
fac368a0 NV |
390 | --dev->buf_len; |
391 | ||
75b81f33 MR |
392 | /* return if aborting, we only needed to read RHR to clear RXRDY*/ |
393 | if (dev->recv_len_abort) | |
394 | return; | |
395 | ||
fac368a0 NV |
396 | /* handle I2C_SMBUS_BLOCK_DATA */ |
397 | if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) { | |
75b81f33 MR |
398 | /* ensure length byte is a valid value */ |
399 | if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) { | |
400 | dev->msg->flags &= ~I2C_M_RECV_LEN; | |
401 | dev->buf_len += *dev->buf; | |
402 | dev->msg->len = dev->buf_len + 1; | |
403 | dev_dbg(dev->dev, "received block length %d\n", | |
404 | dev->buf_len); | |
405 | } else { | |
406 | /* abort and send the stop by reading one more byte */ | |
407 | dev->recv_len_abort = true; | |
408 | dev->buf_len = 1; | |
409 | } | |
fac368a0 NV |
410 | } |
411 | ||
412 | /* send stop if second but last byte has been read */ | |
0ef6f321 | 413 | if (!dev->pdata->has_alt_cmd && dev->buf_len == 1) |
fac368a0 NV |
414 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); |
415 | ||
416 | dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
417 | ||
418 | ++dev->buf; | |
419 | } | |
420 | ||
60937b2c LD |
421 | static void at91_twi_read_data_dma_callback(void *data) |
422 | { | |
423 | struct at91_twi_dev *dev = (struct at91_twi_dev *)data; | |
0ef6f321 | 424 | unsigned ier = AT91_TWI_TXCOMP; |
60937b2c | 425 | |
5e3cfc6c | 426 | dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]), |
28772ac8 | 427 | dev->buf_len, DMA_FROM_DEVICE); |
60937b2c | 428 | |
0ef6f321 CP |
429 | if (!dev->pdata->has_alt_cmd) { |
430 | /* The last two bytes have to be read without using dma */ | |
431 | dev->buf += dev->buf_len - 2; | |
432 | dev->buf_len = 2; | |
433 | ier |= AT91_TWI_RXRDY; | |
434 | } | |
435 | at91_twi_write(dev, AT91_TWI_IER, ier); | |
60937b2c LD |
436 | } |
437 | ||
438 | static void at91_twi_read_data_dma(struct at91_twi_dev *dev) | |
439 | { | |
440 | dma_addr_t dma_addr; | |
441 | struct dma_async_tx_descriptor *rxdesc; | |
442 | struct at91_twi_dma *dma = &dev->dma; | |
443 | struct dma_chan *chan_rx = dma->chan_rx; | |
0ef6f321 | 444 | size_t buf_len; |
60937b2c | 445 | |
0ef6f321 | 446 | buf_len = (dev->pdata->has_alt_cmd) ? dev->buf_len : dev->buf_len - 2; |
60937b2c LD |
447 | dma->direction = DMA_FROM_DEVICE; |
448 | ||
449 | /* Keep in mind that we won't use dma to read the last two bytes */ | |
450 | at91_twi_irq_save(dev); | |
0ef6f321 | 451 | dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE); |
60937b2c LD |
452 | if (dma_mapping_error(dev->dev, dma_addr)) { |
453 | dev_err(dev->dev, "dma map failed\n"); | |
454 | return; | |
455 | } | |
456 | dma->buf_mapped = true; | |
457 | at91_twi_irq_restore(dev); | |
60937b2c | 458 | |
5e3cfc6c CP |
459 | if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) { |
460 | unsigned fifo_mr; | |
461 | ||
462 | /* | |
463 | * DMA controller is triggered when at least 4 data can be | |
464 | * read from the RX FIFO | |
465 | */ | |
466 | fifo_mr = at91_twi_read(dev, AT91_TWI_FMR); | |
467 | fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK; | |
468 | fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA); | |
469 | at91_twi_write(dev, AT91_TWI_FMR, fifo_mr); | |
470 | } | |
471 | ||
472 | sg_dma_len(&dma->sg[0]) = buf_len; | |
473 | sg_dma_address(&dma->sg[0]) = dma_addr; | |
474 | ||
475 | rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM, | |
60937b2c LD |
476 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
477 | if (!rxdesc) { | |
478 | dev_err(dev->dev, "dma prep slave sg failed\n"); | |
479 | goto error; | |
480 | } | |
481 | ||
482 | rxdesc->callback = at91_twi_read_data_dma_callback; | |
483 | rxdesc->callback_param = dev; | |
484 | ||
485 | dma->xfer_in_progress = true; | |
486 | dmaengine_submit(rxdesc); | |
487 | dma_async_issue_pending(dma->chan_rx); | |
488 | ||
489 | return; | |
490 | ||
491 | error: | |
492 | at91_twi_dma_cleanup(dev); | |
493 | } | |
494 | ||
fac368a0 NV |
495 | static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id) |
496 | { | |
497 | struct at91_twi_dev *dev = dev_id; | |
498 | const unsigned status = at91_twi_read(dev, AT91_TWI_SR); | |
499 | const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR); | |
500 | ||
501 | if (!irqstatus) | |
502 | return IRQ_NONE; | |
a9bed6b1 LD |
503 | /* |
504 | * In reception, the behavior of the twi device (before sama5d2) is | |
505 | * weird. There is some magic about RXRDY flag! When a data has been | |
506 | * almost received, the reception of a new one is anticipated if there | |
507 | * is no stop command to send. That is the reason why ask for sending | |
508 | * the stop command not on the last data but on the second last one. | |
509 | * | |
510 | * Unfortunately, we could still have the RXRDY flag set even if the | |
511 | * transfer is done and we have read the last data. It might happen | |
512 | * when the i2c slave device sends too quickly data after receiving the | |
513 | * ack from the master. The data has been almost received before having | |
514 | * the order to send stop. In this case, sending the stop command could | |
515 | * cause a RXRDY interrupt with a TXCOMP one. It is better to manage | |
516 | * the RXRDY interrupt first in order to not keep garbage data in the | |
517 | * Receive Holding Register for the next transfer. | |
518 | */ | |
519 | if (irqstatus & AT91_TWI_RXRDY) | |
520 | at91_twi_read_next_byte(dev); | |
fac368a0 | 521 | |
6f6ddbb0 CP |
522 | /* |
523 | * When a NACK condition is detected, the I2C controller sets the NACK, | |
524 | * TXCOMP and TXRDY bits all together in the Status Register (SR). | |
525 | * | |
526 | * 1 - Handling NACK errors with CPU write transfer. | |
527 | * | |
528 | * In such case, we should not write the next byte into the Transmit | |
529 | * Holding Register (THR) otherwise the I2C controller would start a new | |
530 | * transfer and the I2C slave is likely to reply by another NACK. | |
531 | * | |
532 | * 2 - Handling NACK errors with DMA write transfer. | |
533 | * | |
534 | * By setting the TXRDY bit in the SR, the I2C controller also triggers | |
535 | * the DMA controller to write the next data into the THR. Then the | |
536 | * result depends on the hardware version of the I2C controller. | |
537 | * | |
538 | * 2a - Without support of the Alternative Command mode. | |
539 | * | |
540 | * This is the worst case: the DMA controller is triggered to write the | |
541 | * next data into the THR, hence starting a new transfer: the I2C slave | |
542 | * is likely to reply by another NACK. | |
543 | * Concurrently, this interrupt handler is likely to be called to manage | |
544 | * the first NACK before the I2C controller detects the second NACK and | |
545 | * sets once again the NACK bit into the SR. | |
546 | * When handling the first NACK, this interrupt handler disables the I2C | |
547 | * controller interruptions, especially the NACK interrupt. | |
548 | * Hence, the NACK bit is pending into the SR. This is why we should | |
549 | * read the SR to clear all pending interrupts at the beginning of | |
550 | * at91_do_twi_transfer() before actually starting a new transfer. | |
551 | * | |
552 | * 2b - With support of the Alternative Command mode. | |
553 | * | |
554 | * When a NACK condition is detected, the I2C controller also locks the | |
555 | * THR (and sets the LOCK bit in the SR): even though the DMA controller | |
556 | * is triggered by the TXRDY bit to write the next data into the THR, | |
557 | * this data actually won't go on the I2C bus hence a second NACK is not | |
558 | * generated. | |
559 | */ | |
93563a6a | 560 | if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) { |
fac368a0 NV |
561 | at91_disable_twi_interrupts(dev); |
562 | complete(&dev->cmd_complete); | |
6f6ddbb0 CP |
563 | } else if (irqstatus & AT91_TWI_TXRDY) { |
564 | at91_twi_write_next_byte(dev); | |
fac368a0 NV |
565 | } |
566 | ||
6f6ddbb0 CP |
567 | /* catch error flags */ |
568 | dev->transfer_status |= status; | |
569 | ||
fac368a0 NV |
570 | return IRQ_HANDLED; |
571 | } | |
572 | ||
573 | static int at91_do_twi_transfer(struct at91_twi_dev *dev) | |
574 | { | |
575 | int ret; | |
1c42aca5 | 576 | unsigned long time_left; |
fac368a0 | 577 | bool has_unre_flag = dev->pdata->has_unre_flag; |
0ef6f321 | 578 | bool has_alt_cmd = dev->pdata->has_alt_cmd; |
fac368a0 | 579 | |
93563a6a CP |
580 | /* |
581 | * WARNING: the TXCOMP bit in the Status Register is NOT a clear on | |
582 | * read flag but shows the state of the transmission at the time the | |
583 | * Status Register is read. According to the programmer datasheet, | |
584 | * TXCOMP is set when both holding register and internal shifter are | |
585 | * empty and STOP condition has been sent. | |
586 | * Consequently, we should enable NACK interrupt rather than TXCOMP to | |
587 | * detect transmission failure. | |
0ef6f321 CP |
588 | * Indeed let's take the case of an i2c write command using DMA. |
589 | * Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and | |
590 | * TXCOMP bits are set together into the Status Register. | |
591 | * LOCK is a clear on write bit, which is set to prevent the DMA | |
592 | * controller from sending new data on the i2c bus after a NACK | |
593 | * condition has happened. Once locked, this i2c peripheral stops | |
594 | * triggering the DMA controller for new data but it is more than | |
595 | * likely that a new DMA transaction is already in progress, writing | |
596 | * into the Transmit Holding Register. Since the peripheral is locked, | |
597 | * these new data won't be sent to the i2c bus but they will remain | |
598 | * into the Transmit Holding Register, so TXCOMP bit is cleared. | |
599 | * Then when the interrupt handler is called, the Status Register is | |
600 | * read: the TXCOMP bit is clear but NACK bit is still set. The driver | |
601 | * manage the error properly, without waiting for timeout. | |
602 | * This case can be reproduced easyly when writing into an at24 eeprom. | |
93563a6a CP |
603 | * |
604 | * Besides, the TXCOMP bit is already set before the i2c transaction | |
605 | * has been started. For read transactions, this bit is cleared when | |
606 | * writing the START bit into the Control Register. So the | |
607 | * corresponding interrupt can safely be enabled just after. | |
608 | * However for write transactions managed by the CPU, we first write | |
609 | * into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP | |
610 | * interrupt. If TXCOMP interrupt were enabled before writing into THR, | |
611 | * the interrupt handler would be called immediately and the i2c command | |
612 | * would be reported as completed. | |
613 | * Also when a write transaction is managed by the DMA controller, | |
614 | * enabling the TXCOMP interrupt in this function may lead to a race | |
615 | * condition since we don't know whether the TXCOMP interrupt is enabled | |
616 | * before or after the DMA has started to write into THR. So the TXCOMP | |
617 | * interrupt is enabled later by at91_twi_write_data_dma_callback(). | |
0ef6f321 CP |
618 | * Immediately after in that DMA callback, if the alternative command |
619 | * mode is not used, we still need to send the STOP condition manually | |
620 | * writing the corresponding bit into the Control Register. | |
93563a6a CP |
621 | */ |
622 | ||
fac368a0 NV |
623 | dev_dbg(dev->dev, "transfer: %s %d bytes.\n", |
624 | (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); | |
625 | ||
16735d02 | 626 | reinit_completion(&dev->cmd_complete); |
fac368a0 | 627 | dev->transfer_status = 0; |
7c3fe64d | 628 | |
6f6ddbb0 | 629 | /* Clear pending interrupts, such as NACK. */ |
a9bed6b1 | 630 | at91_twi_read(dev, AT91_TWI_SR); |
6f6ddbb0 | 631 | |
5e3cfc6c CP |
632 | if (dev->fifo_size) { |
633 | unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR); | |
634 | ||
635 | /* Reset FIFO mode register */ | |
636 | fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK | | |
637 | AT91_TWI_FMR_RXRDYM_MASK); | |
638 | fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA); | |
639 | fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA); | |
640 | at91_twi_write(dev, AT91_TWI_FMR, fifo_mr); | |
641 | ||
642 | /* Flush FIFOs */ | |
643 | at91_twi_write(dev, AT91_TWI_CR, | |
644 | AT91_TWI_THRCLR | AT91_TWI_RHRCLR); | |
645 | } | |
646 | ||
7c3fe64d LD |
647 | if (!dev->buf_len) { |
648 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK); | |
649 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
650 | } else if (dev->msg->flags & I2C_M_RD) { | |
fac368a0 NV |
651 | unsigned start_flags = AT91_TWI_START; |
652 | ||
fac368a0 | 653 | /* if only one byte is to be read, immediately stop transfer */ |
0ef6f321 CP |
654 | if (!has_alt_cmd && dev->buf_len <= 1 && |
655 | !(dev->msg->flags & I2C_M_RECV_LEN)) | |
fac368a0 NV |
656 | start_flags |= AT91_TWI_STOP; |
657 | at91_twi_write(dev, AT91_TWI_CR, start_flags); | |
60937b2c | 658 | /* |
0ef6f321 CP |
659 | * When using dma without alternative command mode, the last |
660 | * byte has to be read manually in order to not send the stop | |
661 | * command too late and then to receive extra data. | |
662 | * In practice, there are some issues if you use the dma to | |
663 | * read n-1 bytes because of latency. | |
60937b2c LD |
664 | * Reading n-2 bytes with dma and the two last ones manually |
665 | * seems to be the best solution. | |
666 | */ | |
667 | if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { | |
93563a6a | 668 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK); |
60937b2c | 669 | at91_twi_read_data_dma(dev); |
93563a6a | 670 | } else { |
60937b2c | 671 | at91_twi_write(dev, AT91_TWI_IER, |
93563a6a CP |
672 | AT91_TWI_TXCOMP | |
673 | AT91_TWI_NACK | | |
674 | AT91_TWI_RXRDY); | |
675 | } | |
fac368a0 | 676 | } else { |
60937b2c | 677 | if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { |
93563a6a | 678 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK); |
60937b2c | 679 | at91_twi_write_data_dma(dev); |
60937b2c LD |
680 | } else { |
681 | at91_twi_write_next_byte(dev); | |
682 | at91_twi_write(dev, AT91_TWI_IER, | |
93563a6a CP |
683 | AT91_TWI_TXCOMP | |
684 | AT91_TWI_NACK | | |
685 | AT91_TWI_TXRDY); | |
60937b2c | 686 | } |
fac368a0 NV |
687 | } |
688 | ||
1c42aca5 NMG |
689 | time_left = wait_for_completion_timeout(&dev->cmd_complete, |
690 | dev->adapter.timeout); | |
691 | if (time_left == 0) { | |
0ef6f321 | 692 | dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR); |
fac368a0 NV |
693 | dev_err(dev->dev, "controller timed out\n"); |
694 | at91_init_twi_bus(dev); | |
60937b2c LD |
695 | ret = -ETIMEDOUT; |
696 | goto error; | |
fac368a0 NV |
697 | } |
698 | if (dev->transfer_status & AT91_TWI_NACK) { | |
699 | dev_dbg(dev->dev, "received nack\n"); | |
60937b2c LD |
700 | ret = -EREMOTEIO; |
701 | goto error; | |
fac368a0 NV |
702 | } |
703 | if (dev->transfer_status & AT91_TWI_OVRE) { | |
704 | dev_err(dev->dev, "overrun while reading\n"); | |
60937b2c LD |
705 | ret = -EIO; |
706 | goto error; | |
fac368a0 NV |
707 | } |
708 | if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) { | |
709 | dev_err(dev->dev, "underrun while writing\n"); | |
60937b2c LD |
710 | ret = -EIO; |
711 | goto error; | |
fac368a0 | 712 | } |
5e3cfc6c CP |
713 | if ((has_alt_cmd || dev->fifo_size) && |
714 | (dev->transfer_status & AT91_TWI_LOCK)) { | |
0ef6f321 CP |
715 | dev_err(dev->dev, "tx locked\n"); |
716 | ret = -EIO; | |
717 | goto error; | |
718 | } | |
75b81f33 MR |
719 | if (dev->recv_len_abort) { |
720 | dev_err(dev->dev, "invalid smbus block length recvd\n"); | |
721 | ret = -EPROTO; | |
722 | goto error; | |
723 | } | |
724 | ||
fac368a0 NV |
725 | dev_dbg(dev->dev, "transfer complete\n"); |
726 | ||
727 | return 0; | |
60937b2c LD |
728 | |
729 | error: | |
0ef6f321 | 730 | /* first stop DMA transfer if still in progress */ |
60937b2c | 731 | at91_twi_dma_cleanup(dev); |
0ef6f321 | 732 | /* then flush THR/FIFO and unlock TX if locked */ |
5e3cfc6c CP |
733 | if ((has_alt_cmd || dev->fifo_size) && |
734 | (dev->transfer_status & AT91_TWI_LOCK)) { | |
0ef6f321 CP |
735 | dev_dbg(dev->dev, "unlock tx\n"); |
736 | at91_twi_write(dev, AT91_TWI_CR, | |
737 | AT91_TWI_THRCLR | AT91_TWI_LOCKCLR); | |
738 | } | |
60937b2c | 739 | return ret; |
fac368a0 NV |
740 | } |
741 | ||
742 | static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) | |
743 | { | |
744 | struct at91_twi_dev *dev = i2c_get_adapdata(adap); | |
745 | int ret; | |
746 | unsigned int_addr_flag = 0; | |
747 | struct i2c_msg *m_start = msg; | |
0ef6f321 | 748 | bool is_read, use_alt_cmd = false; |
fac368a0 NV |
749 | |
750 | dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); | |
751 | ||
d64a8188 WY |
752 | ret = pm_runtime_get_sync(dev->dev); |
753 | if (ret < 0) | |
754 | goto out; | |
755 | ||
a7405844 | 756 | if (num == 2) { |
fac368a0 NV |
757 | int internal_address = 0; |
758 | int i; | |
759 | ||
fac368a0 NV |
760 | /* 1st msg is put into the internal address, start with 2nd */ |
761 | m_start = &msg[1]; | |
762 | for (i = 0; i < msg->len; ++i) { | |
763 | const unsigned addr = msg->buf[msg->len - 1 - i]; | |
764 | ||
765 | internal_address |= addr << (8 * i); | |
766 | int_addr_flag += AT91_TWI_IADRSZ_1; | |
767 | } | |
768 | at91_twi_write(dev, AT91_TWI_IADR, internal_address); | |
769 | } | |
770 | ||
0ef6f321 CP |
771 | is_read = (m_start->flags & I2C_M_RD); |
772 | if (dev->pdata->has_alt_cmd) { | |
773 | if (m_start->len > 0) { | |
774 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN); | |
775 | at91_twi_write(dev, AT91_TWI_ACR, | |
776 | AT91_TWI_ACR_DATAL(m_start->len) | | |
777 | ((is_read) ? AT91_TWI_ACR_DIR : 0)); | |
778 | use_alt_cmd = true; | |
779 | } else { | |
780 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS); | |
781 | } | |
782 | } | |
783 | ||
784 | at91_twi_write(dev, AT91_TWI_MMR, | |
785 | (m_start->addr << 16) | | |
786 | int_addr_flag | | |
787 | ((!use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0)); | |
fac368a0 NV |
788 | |
789 | dev->buf_len = m_start->len; | |
790 | dev->buf = m_start->buf; | |
791 | dev->msg = m_start; | |
75b81f33 | 792 | dev->recv_len_abort = false; |
fac368a0 NV |
793 | |
794 | ret = at91_do_twi_transfer(dev); | |
795 | ||
d64a8188 WY |
796 | ret = (ret < 0) ? ret : num; |
797 | out: | |
798 | pm_runtime_mark_last_busy(dev->dev); | |
799 | pm_runtime_put_autosuspend(dev->dev); | |
800 | ||
801 | return ret; | |
fac368a0 NV |
802 | } |
803 | ||
a7405844 WS |
804 | /* |
805 | * The hardware can handle at most two messages concatenated by a | |
806 | * repeated start via it's internal address feature. | |
807 | */ | |
808 | static struct i2c_adapter_quirks at91_twi_quirks = { | |
809 | .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR, | |
810 | .max_comb_1st_msg_len = 3, | |
811 | }; | |
812 | ||
fac368a0 NV |
813 | static u32 at91_twi_func(struct i2c_adapter *adapter) |
814 | { | |
815 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
816 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA; | |
817 | } | |
818 | ||
819 | static struct i2c_algorithm at91_twi_algorithm = { | |
820 | .master_xfer = at91_twi_xfer, | |
821 | .functionality = at91_twi_func, | |
822 | }; | |
823 | ||
824 | static struct at91_twi_pdata at91rm9200_config = { | |
825 | .clk_max_div = 5, | |
826 | .clk_offset = 3, | |
827 | .has_unre_flag = true, | |
0ef6f321 | 828 | .has_alt_cmd = false, |
cc018e36 | 829 | .has_hold_field = false, |
fac368a0 NV |
830 | }; |
831 | ||
832 | static struct at91_twi_pdata at91sam9261_config = { | |
833 | .clk_max_div = 5, | |
834 | .clk_offset = 4, | |
835 | .has_unre_flag = false, | |
0ef6f321 | 836 | .has_alt_cmd = false, |
cc018e36 | 837 | .has_hold_field = false, |
fac368a0 NV |
838 | }; |
839 | ||
840 | static struct at91_twi_pdata at91sam9260_config = { | |
841 | .clk_max_div = 7, | |
842 | .clk_offset = 4, | |
843 | .has_unre_flag = false, | |
0ef6f321 | 844 | .has_alt_cmd = false, |
cc018e36 | 845 | .has_hold_field = false, |
fac368a0 NV |
846 | }; |
847 | ||
848 | static struct at91_twi_pdata at91sam9g20_config = { | |
849 | .clk_max_div = 7, | |
850 | .clk_offset = 4, | |
851 | .has_unre_flag = false, | |
0ef6f321 | 852 | .has_alt_cmd = false, |
cc018e36 | 853 | .has_hold_field = false, |
fac368a0 NV |
854 | }; |
855 | ||
856 | static struct at91_twi_pdata at91sam9g10_config = { | |
857 | .clk_max_div = 7, | |
858 | .clk_offset = 4, | |
859 | .has_unre_flag = false, | |
0ef6f321 | 860 | .has_alt_cmd = false, |
cc018e36 | 861 | .has_hold_field = false, |
fac368a0 NV |
862 | }; |
863 | ||
864 | static const struct platform_device_id at91_twi_devtypes[] = { | |
865 | { | |
866 | .name = "i2c-at91rm9200", | |
867 | .driver_data = (unsigned long) &at91rm9200_config, | |
868 | }, { | |
869 | .name = "i2c-at91sam9261", | |
870 | .driver_data = (unsigned long) &at91sam9261_config, | |
871 | }, { | |
872 | .name = "i2c-at91sam9260", | |
873 | .driver_data = (unsigned long) &at91sam9260_config, | |
874 | }, { | |
875 | .name = "i2c-at91sam9g20", | |
876 | .driver_data = (unsigned long) &at91sam9g20_config, | |
877 | }, { | |
878 | .name = "i2c-at91sam9g10", | |
879 | .driver_data = (unsigned long) &at91sam9g10_config, | |
880 | }, { | |
881 | /* sentinel */ | |
882 | } | |
883 | }; | |
884 | ||
70d46a24 | 885 | #if defined(CONFIG_OF) |
4182b434 JE |
886 | static struct at91_twi_pdata at91sam9x5_config = { |
887 | .clk_max_div = 7, | |
888 | .clk_offset = 4, | |
889 | .has_unre_flag = false, | |
0ef6f321 | 890 | .has_alt_cmd = false, |
cc018e36 LD |
891 | .has_hold_field = false, |
892 | }; | |
893 | ||
894 | static struct at91_twi_pdata sama5d4_config = { | |
895 | .clk_max_div = 7, | |
896 | .clk_offset = 4, | |
897 | .has_unre_flag = false, | |
898 | .has_alt_cmd = false, | |
899 | .has_hold_field = true, | |
0ef6f321 CP |
900 | }; |
901 | ||
902 | static struct at91_twi_pdata sama5d2_config = { | |
903 | .clk_max_div = 7, | |
904 | .clk_offset = 4, | |
905 | .has_unre_flag = true, | |
906 | .has_alt_cmd = true, | |
cc018e36 | 907 | .has_hold_field = true, |
4182b434 JE |
908 | }; |
909 | ||
70d46a24 LD |
910 | static const struct of_device_id atmel_twi_dt_ids[] = { |
911 | { | |
631056c3 JE |
912 | .compatible = "atmel,at91rm9200-i2c", |
913 | .data = &at91rm9200_config, | |
914 | } , { | |
70d46a24 LD |
915 | .compatible = "atmel,at91sam9260-i2c", |
916 | .data = &at91sam9260_config, | |
d9a3afc2 | 917 | } , { |
918 | .compatible = "atmel,at91sam9261-i2c", | |
919 | .data = &at91sam9261_config, | |
70d46a24 LD |
920 | } , { |
921 | .compatible = "atmel,at91sam9g20-i2c", | |
922 | .data = &at91sam9g20_config, | |
923 | } , { | |
924 | .compatible = "atmel,at91sam9g10-i2c", | |
925 | .data = &at91sam9g10_config, | |
926 | }, { | |
927 | .compatible = "atmel,at91sam9x5-i2c", | |
928 | .data = &at91sam9x5_config, | |
cc018e36 LD |
929 | }, { |
930 | .compatible = "atmel,sama5d4-i2c", | |
931 | .data = &sama5d4_config, | |
0ef6f321 CP |
932 | }, { |
933 | .compatible = "atmel,sama5d2-i2c", | |
934 | .data = &sama5d2_config, | |
70d46a24 LD |
935 | }, { |
936 | /* sentinel */ | |
937 | } | |
938 | }; | |
939 | MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids); | |
70d46a24 LD |
940 | #endif |
941 | ||
0b255e92 | 942 | static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr) |
60937b2c LD |
943 | { |
944 | int ret = 0; | |
60937b2c LD |
945 | struct dma_slave_config slave_config; |
946 | struct at91_twi_dma *dma = &dev->dma; | |
5e3cfc6c CP |
947 | enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
948 | ||
949 | /* | |
950 | * The actual width of the access will be chosen in | |
951 | * dmaengine_prep_slave_sg(): | |
952 | * for each buffer in the scatter-gather list, if its size is aligned | |
953 | * to addr_width then addr_width accesses will be performed to transfer | |
954 | * the buffer. On the other hand, if the buffer size is not aligned to | |
955 | * addr_width then the buffer is transferred using single byte accesses. | |
956 | * Please refer to the Atmel eXtended DMA controller driver. | |
957 | * When FIFOs are used, the TXRDYM threshold can always be set to | |
958 | * trigger the XDMAC when at least 4 data can be written into the TX | |
959 | * FIFO, even if single byte accesses are performed. | |
960 | * However the RXRDYM threshold must be set to fit the access width, | |
961 | * deduced from buffer length, so the XDMAC is triggered properly to | |
962 | * read data from the RX FIFO. | |
963 | */ | |
964 | if (dev->fifo_size) | |
965 | addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
60937b2c LD |
966 | |
967 | memset(&slave_config, 0, sizeof(slave_config)); | |
968 | slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR; | |
5e3cfc6c | 969 | slave_config.src_addr_width = addr_width; |
60937b2c LD |
970 | slave_config.src_maxburst = 1; |
971 | slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR; | |
5e3cfc6c | 972 | slave_config.dst_addr_width = addr_width; |
60937b2c LD |
973 | slave_config.dst_maxburst = 1; |
974 | slave_config.device_fc = false; | |
975 | ||
727f9c2d LD |
976 | dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx"); |
977 | if (IS_ERR(dma->chan_tx)) { | |
978 | ret = PTR_ERR(dma->chan_tx); | |
979 | dma->chan_tx = NULL; | |
d877a721 LD |
980 | goto error; |
981 | } | |
982 | ||
727f9c2d LD |
983 | dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx"); |
984 | if (IS_ERR(dma->chan_rx)) { | |
985 | ret = PTR_ERR(dma->chan_rx); | |
986 | dma->chan_rx = NULL; | |
60937b2c LD |
987 | goto error; |
988 | } | |
989 | ||
990 | slave_config.direction = DMA_MEM_TO_DEV; | |
991 | if (dmaengine_slave_config(dma->chan_tx, &slave_config)) { | |
992 | dev_err(dev->dev, "failed to configure tx channel\n"); | |
993 | ret = -EINVAL; | |
994 | goto error; | |
995 | } | |
996 | ||
997 | slave_config.direction = DMA_DEV_TO_MEM; | |
998 | if (dmaengine_slave_config(dma->chan_rx, &slave_config)) { | |
999 | dev_err(dev->dev, "failed to configure rx channel\n"); | |
1000 | ret = -EINVAL; | |
1001 | goto error; | |
1002 | } | |
1003 | ||
5e3cfc6c | 1004 | sg_init_table(dma->sg, 2); |
60937b2c LD |
1005 | dma->buf_mapped = false; |
1006 | dma->xfer_in_progress = false; | |
727f9c2d | 1007 | dev->use_dma = true; |
60937b2c LD |
1008 | |
1009 | dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n", | |
1010 | dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); | |
1011 | ||
1012 | return ret; | |
1013 | ||
1014 | error: | |
727f9c2d | 1015 | if (ret != -EPROBE_DEFER) |
67fed0da | 1016 | dev_info(dev->dev, "can't get DMA channel, continue without DMA support\n"); |
60937b2c LD |
1017 | if (dma->chan_rx) |
1018 | dma_release_channel(dma->chan_rx); | |
1019 | if (dma->chan_tx) | |
1020 | dma_release_channel(dma->chan_tx); | |
1021 | return ret; | |
1022 | } | |
1023 | ||
0b255e92 | 1024 | static struct at91_twi_pdata *at91_twi_get_driver_data( |
70d46a24 LD |
1025 | struct platform_device *pdev) |
1026 | { | |
1027 | if (pdev->dev.of_node) { | |
1028 | const struct of_device_id *match; | |
1029 | match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node); | |
1030 | if (!match) | |
1031 | return NULL; | |
cd32e6cc | 1032 | return (struct at91_twi_pdata *)match->data; |
70d46a24 LD |
1033 | } |
1034 | return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data; | |
1035 | } | |
1036 | ||
0b255e92 | 1037 | static int at91_twi_probe(struct platform_device *pdev) |
fac368a0 NV |
1038 | { |
1039 | struct at91_twi_dev *dev; | |
1040 | struct resource *mem; | |
1041 | int rc; | |
60937b2c | 1042 | u32 phy_addr; |
75b6c4b6 | 1043 | u32 bus_clk_rate; |
fac368a0 NV |
1044 | |
1045 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); | |
1046 | if (!dev) | |
1047 | return -ENOMEM; | |
1048 | init_completion(&dev->cmd_complete); | |
1049 | dev->dev = &pdev->dev; | |
1050 | ||
1051 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1052 | if (!mem) | |
1053 | return -ENODEV; | |
60937b2c | 1054 | phy_addr = mem->start; |
fac368a0 NV |
1055 | |
1056 | dev->pdata = at91_twi_get_driver_data(pdev); | |
1057 | if (!dev->pdata) | |
1058 | return -ENODEV; | |
1059 | ||
84dbf809 TR |
1060 | dev->base = devm_ioremap_resource(&pdev->dev, mem); |
1061 | if (IS_ERR(dev->base)) | |
1062 | return PTR_ERR(dev->base); | |
fac368a0 NV |
1063 | |
1064 | dev->irq = platform_get_irq(pdev, 0); | |
1065 | if (dev->irq < 0) | |
1066 | return dev->irq; | |
1067 | ||
1068 | rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0, | |
1069 | dev_name(dev->dev), dev); | |
1070 | if (rc) { | |
1071 | dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc); | |
1072 | return rc; | |
1073 | } | |
1074 | ||
1075 | platform_set_drvdata(pdev, dev); | |
1076 | ||
1077 | dev->clk = devm_clk_get(dev->dev, NULL); | |
1078 | if (IS_ERR(dev->clk)) { | |
1079 | dev_err(dev->dev, "no clock defined\n"); | |
1080 | return -ENODEV; | |
1081 | } | |
1082 | clk_prepare_enable(dev->clk); | |
1083 | ||
dc6df6e9 | 1084 | if (dev->dev->of_node) { |
727f9c2d LD |
1085 | rc = at91_twi_configure_dma(dev, phy_addr); |
1086 | if (rc == -EPROBE_DEFER) | |
1087 | return rc; | |
60937b2c LD |
1088 | } |
1089 | ||
5e3cfc6c CP |
1090 | if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", |
1091 | &dev->fifo_size)) { | |
1092 | dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size); | |
1093 | } | |
1094 | ||
75b6c4b6 MR |
1095 | rc = of_property_read_u32(dev->dev->of_node, "clock-frequency", |
1096 | &bus_clk_rate); | |
1097 | if (rc) | |
1098 | bus_clk_rate = DEFAULT_TWI_CLK_HZ; | |
1099 | ||
1100 | at91_calc_twi_clock(dev, bus_clk_rate); | |
fac368a0 NV |
1101 | at91_init_twi_bus(dev); |
1102 | ||
1103 | snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91"); | |
1104 | i2c_set_adapdata(&dev->adapter, dev); | |
1105 | dev->adapter.owner = THIS_MODULE; | |
b850579a | 1106 | dev->adapter.class = I2C_CLASS_DEPRECATED; |
fac368a0 | 1107 | dev->adapter.algo = &at91_twi_algorithm; |
a7405844 | 1108 | dev->adapter.quirks = &at91_twi_quirks; |
fac368a0 NV |
1109 | dev->adapter.dev.parent = dev->dev; |
1110 | dev->adapter.nr = pdev->id; | |
1111 | dev->adapter.timeout = AT91_I2C_TIMEOUT; | |
70d46a24 | 1112 | dev->adapter.dev.of_node = pdev->dev.of_node; |
fac368a0 | 1113 | |
d64a8188 WY |
1114 | pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT); |
1115 | pm_runtime_use_autosuspend(dev->dev); | |
1116 | pm_runtime_set_active(dev->dev); | |
1117 | pm_runtime_enable(dev->dev); | |
1118 | ||
fac368a0 NV |
1119 | rc = i2c_add_numbered_adapter(&dev->adapter); |
1120 | if (rc) { | |
1121 | dev_err(dev->dev, "Adapter %s registration failed\n", | |
1122 | dev->adapter.name); | |
1123 | clk_disable_unprepare(dev->clk); | |
d64a8188 WY |
1124 | |
1125 | pm_runtime_disable(dev->dev); | |
1126 | pm_runtime_set_suspended(dev->dev); | |
1127 | ||
fac368a0 NV |
1128 | return rc; |
1129 | } | |
1130 | ||
6ce461ea CP |
1131 | dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n", |
1132 | at91_twi_read(dev, AT91_TWI_VER)); | |
fac368a0 NV |
1133 | return 0; |
1134 | } | |
1135 | ||
0b255e92 | 1136 | static int at91_twi_remove(struct platform_device *pdev) |
fac368a0 NV |
1137 | { |
1138 | struct at91_twi_dev *dev = platform_get_drvdata(pdev); | |
fac368a0 | 1139 | |
bf51a8c5 | 1140 | i2c_del_adapter(&dev->adapter); |
fac368a0 NV |
1141 | clk_disable_unprepare(dev->clk); |
1142 | ||
d64a8188 WY |
1143 | pm_runtime_disable(dev->dev); |
1144 | pm_runtime_set_suspended(dev->dev); | |
1145 | ||
bf51a8c5 | 1146 | return 0; |
fac368a0 NV |
1147 | } |
1148 | ||
1149 | #ifdef CONFIG_PM | |
1150 | ||
1151 | static int at91_twi_runtime_suspend(struct device *dev) | |
1152 | { | |
1153 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
1154 | ||
d64a8188 | 1155 | clk_disable_unprepare(twi_dev->clk); |
fac368a0 | 1156 | |
62d10c40 WY |
1157 | pinctrl_pm_select_sleep_state(dev); |
1158 | ||
fac368a0 NV |
1159 | return 0; |
1160 | } | |
1161 | ||
1162 | static int at91_twi_runtime_resume(struct device *dev) | |
1163 | { | |
1164 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
1165 | ||
62d10c40 WY |
1166 | pinctrl_pm_select_default_state(dev); |
1167 | ||
d64a8188 | 1168 | return clk_prepare_enable(twi_dev->clk); |
fac368a0 NV |
1169 | } |
1170 | ||
36765293 WY |
1171 | static int at91_twi_suspend_noirq(struct device *dev) |
1172 | { | |
1173 | if (!pm_runtime_status_suspended(dev)) | |
1174 | at91_twi_runtime_suspend(dev); | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | static int at91_twi_resume_noirq(struct device *dev) | |
1180 | { | |
1181 | int ret; | |
1182 | ||
1183 | if (!pm_runtime_status_suspended(dev)) { | |
1184 | ret = at91_twi_runtime_resume(dev); | |
1185 | if (ret) | |
1186 | return ret; | |
1187 | } | |
1188 | ||
1189 | pm_runtime_mark_last_busy(dev); | |
1190 | pm_request_autosuspend(dev); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
fac368a0 | 1195 | static const struct dev_pm_ops at91_twi_pm = { |
36765293 WY |
1196 | .suspend_noirq = at91_twi_suspend_noirq, |
1197 | .resume_noirq = at91_twi_resume_noirq, | |
fac368a0 NV |
1198 | .runtime_suspend = at91_twi_runtime_suspend, |
1199 | .runtime_resume = at91_twi_runtime_resume, | |
1200 | }; | |
1201 | ||
1202 | #define at91_twi_pm_ops (&at91_twi_pm) | |
1203 | #else | |
1204 | #define at91_twi_pm_ops NULL | |
1205 | #endif | |
1206 | ||
1207 | static struct platform_driver at91_twi_driver = { | |
1208 | .probe = at91_twi_probe, | |
0b255e92 | 1209 | .remove = at91_twi_remove, |
fac368a0 NV |
1210 | .id_table = at91_twi_devtypes, |
1211 | .driver = { | |
1212 | .name = "at91_i2c", | |
600abead | 1213 | .of_match_table = of_match_ptr(atmel_twi_dt_ids), |
fac368a0 NV |
1214 | .pm = at91_twi_pm_ops, |
1215 | }, | |
1216 | }; | |
1217 | ||
1218 | static int __init at91_twi_init(void) | |
1219 | { | |
1220 | return platform_driver_register(&at91_twi_driver); | |
1221 | } | |
1222 | ||
1223 | static void __exit at91_twi_exit(void) | |
1224 | { | |
1225 | platform_driver_unregister(&at91_twi_driver); | |
1226 | } | |
1227 | ||
1228 | subsys_initcall(at91_twi_init); | |
1229 | module_exit(at91_twi_exit); | |
1230 | ||
1231 | MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>"); | |
1232 | MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91"); | |
1233 | MODULE_LICENSE("GPL"); | |
1234 | MODULE_ALIAS("platform:at91_i2c"); |