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fac368a0 NV |
1 | /* |
2 | * i2c Support for Atmel's AT91 Two-Wire Interface (TWI) | |
3 | * | |
4 | * Copyright (C) 2011 Weinmann Medical GmbH | |
5 | * Author: Nikolaus Voss <n.voss@weinmann.de> | |
6 | * | |
7 | * Evolved from original work by: | |
8 | * Copyright (C) 2004 Rick Bronson | |
9 | * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com> | |
10 | * | |
11 | * Borrowed heavily from original work by: | |
12 | * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #include <linux/clk.h> | |
21 | #include <linux/completion.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/module.h> | |
70d46a24 LD |
27 | #include <linux/of.h> |
28 | #include <linux/of_device.h> | |
29 | #include <linux/of_i2c.h> | |
fac368a0 NV |
30 | #include <linux/platform_device.h> |
31 | #include <linux/slab.h> | |
32 | ||
33 | #define TWI_CLK_HZ 100000 /* max 400 Kbits/s */ | |
34 | #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ | |
35 | ||
36 | /* AT91 TWI register definitions */ | |
37 | #define AT91_TWI_CR 0x0000 /* Control Register */ | |
38 | #define AT91_TWI_START 0x0001 /* Send a Start Condition */ | |
39 | #define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */ | |
40 | #define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */ | |
41 | #define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */ | |
7c3fe64d | 42 | #define AT91_TWI_QUICK 0x0040 /* SMBus quick command */ |
fac368a0 NV |
43 | #define AT91_TWI_SWRST 0x0080 /* Software Reset */ |
44 | ||
45 | #define AT91_TWI_MMR 0x0004 /* Master Mode Register */ | |
46 | #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ | |
47 | #define AT91_TWI_MREAD 0x1000 /* Master Read Direction */ | |
48 | ||
49 | #define AT91_TWI_IADR 0x000c /* Internal Address Register */ | |
50 | ||
51 | #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ | |
52 | ||
53 | #define AT91_TWI_SR 0x0020 /* Status Register */ | |
54 | #define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */ | |
55 | #define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */ | |
56 | #define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */ | |
57 | ||
58 | #define AT91_TWI_OVRE 0x0040 /* Overrun Error */ | |
59 | #define AT91_TWI_UNRE 0x0080 /* Underrun Error */ | |
60 | #define AT91_TWI_NACK 0x0100 /* Not Acknowledged */ | |
61 | ||
62 | #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ | |
63 | #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ | |
64 | #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */ | |
65 | #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ | |
66 | #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ | |
67 | ||
68 | struct at91_twi_pdata { | |
69 | unsigned clk_max_div; | |
70 | unsigned clk_offset; | |
71 | bool has_unre_flag; | |
72 | }; | |
73 | ||
74 | struct at91_twi_dev { | |
75 | struct device *dev; | |
76 | void __iomem *base; | |
77 | struct completion cmd_complete; | |
78 | struct clk *clk; | |
79 | u8 *buf; | |
80 | size_t buf_len; | |
81 | struct i2c_msg *msg; | |
82 | int irq; | |
83 | unsigned transfer_status; | |
84 | struct i2c_adapter adapter; | |
85 | unsigned twi_cwgr_reg; | |
86 | struct at91_twi_pdata *pdata; | |
87 | }; | |
88 | ||
89 | static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) | |
90 | { | |
91 | return readl_relaxed(dev->base + reg); | |
92 | } | |
93 | ||
94 | static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) | |
95 | { | |
96 | writel_relaxed(val, dev->base + reg); | |
97 | } | |
98 | ||
99 | static void at91_disable_twi_interrupts(struct at91_twi_dev *dev) | |
100 | { | |
101 | at91_twi_write(dev, AT91_TWI_IDR, | |
102 | AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY); | |
103 | } | |
104 | ||
105 | static void at91_init_twi_bus(struct at91_twi_dev *dev) | |
106 | { | |
107 | at91_disable_twi_interrupts(dev); | |
108 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST); | |
109 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN); | |
110 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS); | |
111 | at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); | |
112 | } | |
113 | ||
114 | /* | |
115 | * Calculate symmetric clock as stated in datasheet: | |
116 | * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) | |
117 | */ | |
118 | static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) | |
119 | { | |
120 | int ckdiv, cdiv, div; | |
121 | struct at91_twi_pdata *pdata = dev->pdata; | |
122 | int offset = pdata->clk_offset; | |
123 | int max_ckdiv = pdata->clk_max_div; | |
124 | ||
125 | div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), | |
126 | 2 * twi_clk) - offset); | |
127 | ckdiv = fls(div >> 8); | |
128 | cdiv = div >> ckdiv; | |
129 | ||
130 | if (ckdiv > max_ckdiv) { | |
131 | dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n", | |
132 | ckdiv, max_ckdiv); | |
133 | ckdiv = max_ckdiv; | |
134 | cdiv = 255; | |
135 | } | |
136 | ||
137 | dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv; | |
138 | dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv); | |
139 | } | |
140 | ||
141 | static void at91_twi_write_next_byte(struct at91_twi_dev *dev) | |
142 | { | |
143 | if (dev->buf_len <= 0) | |
144 | return; | |
145 | ||
146 | at91_twi_write(dev, AT91_TWI_THR, *dev->buf); | |
147 | ||
148 | /* send stop when last byte has been written */ | |
149 | if (--dev->buf_len == 0) | |
150 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
151 | ||
152 | dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
153 | ||
154 | ++dev->buf; | |
155 | } | |
156 | ||
157 | static void at91_twi_read_next_byte(struct at91_twi_dev *dev) | |
158 | { | |
159 | if (dev->buf_len <= 0) | |
160 | return; | |
161 | ||
162 | *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff; | |
163 | --dev->buf_len; | |
164 | ||
165 | /* handle I2C_SMBUS_BLOCK_DATA */ | |
166 | if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) { | |
167 | dev->msg->flags &= ~I2C_M_RECV_LEN; | |
168 | dev->buf_len += *dev->buf; | |
169 | dev->msg->len = dev->buf_len + 1; | |
170 | dev_dbg(dev->dev, "received block length %d\n", dev->buf_len); | |
171 | } | |
172 | ||
173 | /* send stop if second but last byte has been read */ | |
174 | if (dev->buf_len == 1) | |
175 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
176 | ||
177 | dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
178 | ||
179 | ++dev->buf; | |
180 | } | |
181 | ||
182 | static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id) | |
183 | { | |
184 | struct at91_twi_dev *dev = dev_id; | |
185 | const unsigned status = at91_twi_read(dev, AT91_TWI_SR); | |
186 | const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR); | |
187 | ||
188 | if (!irqstatus) | |
189 | return IRQ_NONE; | |
190 | else if (irqstatus & AT91_TWI_RXRDY) | |
191 | at91_twi_read_next_byte(dev); | |
192 | else if (irqstatus & AT91_TWI_TXRDY) | |
193 | at91_twi_write_next_byte(dev); | |
194 | ||
195 | /* catch error flags */ | |
196 | dev->transfer_status |= status; | |
197 | ||
198 | if (irqstatus & AT91_TWI_TXCOMP) { | |
199 | at91_disable_twi_interrupts(dev); | |
200 | complete(&dev->cmd_complete); | |
201 | } | |
202 | ||
203 | return IRQ_HANDLED; | |
204 | } | |
205 | ||
206 | static int at91_do_twi_transfer(struct at91_twi_dev *dev) | |
207 | { | |
208 | int ret; | |
209 | bool has_unre_flag = dev->pdata->has_unre_flag; | |
210 | ||
211 | dev_dbg(dev->dev, "transfer: %s %d bytes.\n", | |
212 | (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); | |
213 | ||
214 | INIT_COMPLETION(dev->cmd_complete); | |
215 | dev->transfer_status = 0; | |
7c3fe64d LD |
216 | |
217 | if (!dev->buf_len) { | |
218 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK); | |
219 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
220 | } else if (dev->msg->flags & I2C_M_RD) { | |
fac368a0 NV |
221 | unsigned start_flags = AT91_TWI_START; |
222 | ||
223 | if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) { | |
224 | dev_err(dev->dev, "RXRDY still set!"); | |
225 | at91_twi_read(dev, AT91_TWI_RHR); | |
226 | } | |
227 | ||
228 | /* if only one byte is to be read, immediately stop transfer */ | |
229 | if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN)) | |
230 | start_flags |= AT91_TWI_STOP; | |
231 | at91_twi_write(dev, AT91_TWI_CR, start_flags); | |
232 | at91_twi_write(dev, AT91_TWI_IER, | |
233 | AT91_TWI_TXCOMP | AT91_TWI_RXRDY); | |
234 | } else { | |
235 | at91_twi_write_next_byte(dev); | |
236 | at91_twi_write(dev, AT91_TWI_IER, | |
237 | AT91_TWI_TXCOMP | AT91_TWI_TXRDY); | |
238 | } | |
239 | ||
240 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, | |
241 | dev->adapter.timeout); | |
242 | if (ret == 0) { | |
243 | dev_err(dev->dev, "controller timed out\n"); | |
244 | at91_init_twi_bus(dev); | |
245 | return -ETIMEDOUT; | |
246 | } | |
247 | if (dev->transfer_status & AT91_TWI_NACK) { | |
248 | dev_dbg(dev->dev, "received nack\n"); | |
249 | return -EREMOTEIO; | |
250 | } | |
251 | if (dev->transfer_status & AT91_TWI_OVRE) { | |
252 | dev_err(dev->dev, "overrun while reading\n"); | |
253 | return -EIO; | |
254 | } | |
255 | if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) { | |
256 | dev_err(dev->dev, "underrun while writing\n"); | |
257 | return -EIO; | |
258 | } | |
259 | dev_dbg(dev->dev, "transfer complete\n"); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) | |
265 | { | |
266 | struct at91_twi_dev *dev = i2c_get_adapdata(adap); | |
267 | int ret; | |
268 | unsigned int_addr_flag = 0; | |
269 | struct i2c_msg *m_start = msg; | |
270 | ||
271 | dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); | |
272 | ||
273 | /* | |
274 | * The hardware can handle at most two messages concatenated by a | |
275 | * repeated start via it's internal address feature. | |
276 | */ | |
277 | if (num > 2) { | |
278 | dev_err(dev->dev, | |
279 | "cannot handle more than two concatenated messages.\n"); | |
280 | return 0; | |
281 | } else if (num == 2) { | |
282 | int internal_address = 0; | |
283 | int i; | |
284 | ||
285 | if (msg->flags & I2C_M_RD) { | |
286 | dev_err(dev->dev, "first transfer must be write.\n"); | |
287 | return -EINVAL; | |
288 | } | |
289 | if (msg->len > 3) { | |
290 | dev_err(dev->dev, "first message size must be <= 3.\n"); | |
291 | return -EINVAL; | |
292 | } | |
293 | ||
294 | /* 1st msg is put into the internal address, start with 2nd */ | |
295 | m_start = &msg[1]; | |
296 | for (i = 0; i < msg->len; ++i) { | |
297 | const unsigned addr = msg->buf[msg->len - 1 - i]; | |
298 | ||
299 | internal_address |= addr << (8 * i); | |
300 | int_addr_flag += AT91_TWI_IADRSZ_1; | |
301 | } | |
302 | at91_twi_write(dev, AT91_TWI_IADR, internal_address); | |
303 | } | |
304 | ||
305 | at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag | |
306 | | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0)); | |
307 | ||
308 | dev->buf_len = m_start->len; | |
309 | dev->buf = m_start->buf; | |
310 | dev->msg = m_start; | |
311 | ||
312 | ret = at91_do_twi_transfer(dev); | |
313 | ||
314 | return (ret < 0) ? ret : num; | |
315 | } | |
316 | ||
317 | static u32 at91_twi_func(struct i2c_adapter *adapter) | |
318 | { | |
319 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
320 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA; | |
321 | } | |
322 | ||
323 | static struct i2c_algorithm at91_twi_algorithm = { | |
324 | .master_xfer = at91_twi_xfer, | |
325 | .functionality = at91_twi_func, | |
326 | }; | |
327 | ||
328 | static struct at91_twi_pdata at91rm9200_config = { | |
329 | .clk_max_div = 5, | |
330 | .clk_offset = 3, | |
331 | .has_unre_flag = true, | |
332 | }; | |
333 | ||
334 | static struct at91_twi_pdata at91sam9261_config = { | |
335 | .clk_max_div = 5, | |
336 | .clk_offset = 4, | |
337 | .has_unre_flag = false, | |
338 | }; | |
339 | ||
340 | static struct at91_twi_pdata at91sam9260_config = { | |
341 | .clk_max_div = 7, | |
342 | .clk_offset = 4, | |
343 | .has_unre_flag = false, | |
344 | }; | |
345 | ||
346 | static struct at91_twi_pdata at91sam9g20_config = { | |
347 | .clk_max_div = 7, | |
348 | .clk_offset = 4, | |
349 | .has_unre_flag = false, | |
350 | }; | |
351 | ||
352 | static struct at91_twi_pdata at91sam9g10_config = { | |
353 | .clk_max_div = 7, | |
354 | .clk_offset = 4, | |
355 | .has_unre_flag = false, | |
356 | }; | |
357 | ||
70d46a24 LD |
358 | static struct at91_twi_pdata at91sam9x5_config = { |
359 | .clk_max_div = 7, | |
360 | .clk_offset = 4, | |
361 | .has_unre_flag = false, | |
362 | }; | |
363 | ||
fac368a0 NV |
364 | static const struct platform_device_id at91_twi_devtypes[] = { |
365 | { | |
366 | .name = "i2c-at91rm9200", | |
367 | .driver_data = (unsigned long) &at91rm9200_config, | |
368 | }, { | |
369 | .name = "i2c-at91sam9261", | |
370 | .driver_data = (unsigned long) &at91sam9261_config, | |
371 | }, { | |
372 | .name = "i2c-at91sam9260", | |
373 | .driver_data = (unsigned long) &at91sam9260_config, | |
374 | }, { | |
375 | .name = "i2c-at91sam9g20", | |
376 | .driver_data = (unsigned long) &at91sam9g20_config, | |
377 | }, { | |
378 | .name = "i2c-at91sam9g10", | |
379 | .driver_data = (unsigned long) &at91sam9g10_config, | |
380 | }, { | |
381 | /* sentinel */ | |
382 | } | |
383 | }; | |
384 | ||
70d46a24 LD |
385 | #if defined(CONFIG_OF) |
386 | static const struct of_device_id atmel_twi_dt_ids[] = { | |
387 | { | |
388 | .compatible = "atmel,at91sam9260-i2c", | |
389 | .data = &at91sam9260_config, | |
390 | } , { | |
391 | .compatible = "atmel,at91sam9g20-i2c", | |
392 | .data = &at91sam9g20_config, | |
393 | } , { | |
394 | .compatible = "atmel,at91sam9g10-i2c", | |
395 | .data = &at91sam9g10_config, | |
396 | }, { | |
397 | .compatible = "atmel,at91sam9x5-i2c", | |
398 | .data = &at91sam9x5_config, | |
399 | }, { | |
400 | /* sentinel */ | |
401 | } | |
402 | }; | |
403 | MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids); | |
404 | #else | |
405 | #define atmel_twi_dt_ids NULL | |
406 | #endif | |
407 | ||
408 | static struct at91_twi_pdata * __devinit at91_twi_get_driver_data( | |
409 | struct platform_device *pdev) | |
410 | { | |
411 | if (pdev->dev.of_node) { | |
412 | const struct of_device_id *match; | |
413 | match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node); | |
414 | if (!match) | |
415 | return NULL; | |
416 | return match->data; | |
417 | } | |
418 | return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data; | |
419 | } | |
420 | ||
fac368a0 NV |
421 | static int __devinit at91_twi_probe(struct platform_device *pdev) |
422 | { | |
423 | struct at91_twi_dev *dev; | |
424 | struct resource *mem; | |
425 | int rc; | |
426 | ||
427 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); | |
428 | if (!dev) | |
429 | return -ENOMEM; | |
430 | init_completion(&dev->cmd_complete); | |
431 | dev->dev = &pdev->dev; | |
432 | ||
433 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
434 | if (!mem) | |
435 | return -ENODEV; | |
436 | ||
437 | dev->pdata = at91_twi_get_driver_data(pdev); | |
438 | if (!dev->pdata) | |
439 | return -ENODEV; | |
440 | ||
441 | dev->base = devm_request_and_ioremap(&pdev->dev, mem); | |
442 | if (!dev->base) | |
443 | return -EBUSY; | |
444 | ||
445 | dev->irq = platform_get_irq(pdev, 0); | |
446 | if (dev->irq < 0) | |
447 | return dev->irq; | |
448 | ||
449 | rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0, | |
450 | dev_name(dev->dev), dev); | |
451 | if (rc) { | |
452 | dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc); | |
453 | return rc; | |
454 | } | |
455 | ||
456 | platform_set_drvdata(pdev, dev); | |
457 | ||
458 | dev->clk = devm_clk_get(dev->dev, NULL); | |
459 | if (IS_ERR(dev->clk)) { | |
460 | dev_err(dev->dev, "no clock defined\n"); | |
461 | return -ENODEV; | |
462 | } | |
463 | clk_prepare_enable(dev->clk); | |
464 | ||
465 | at91_calc_twi_clock(dev, TWI_CLK_HZ); | |
466 | at91_init_twi_bus(dev); | |
467 | ||
468 | snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91"); | |
469 | i2c_set_adapdata(&dev->adapter, dev); | |
470 | dev->adapter.owner = THIS_MODULE; | |
471 | dev->adapter.class = I2C_CLASS_HWMON; | |
472 | dev->adapter.algo = &at91_twi_algorithm; | |
473 | dev->adapter.dev.parent = dev->dev; | |
474 | dev->adapter.nr = pdev->id; | |
475 | dev->adapter.timeout = AT91_I2C_TIMEOUT; | |
70d46a24 | 476 | dev->adapter.dev.of_node = pdev->dev.of_node; |
fac368a0 NV |
477 | |
478 | rc = i2c_add_numbered_adapter(&dev->adapter); | |
479 | if (rc) { | |
480 | dev_err(dev->dev, "Adapter %s registration failed\n", | |
481 | dev->adapter.name); | |
482 | clk_disable_unprepare(dev->clk); | |
483 | return rc; | |
484 | } | |
485 | ||
70d46a24 LD |
486 | of_i2c_register_devices(&dev->adapter); |
487 | ||
fac368a0 NV |
488 | dev_info(dev->dev, "AT91 i2c bus driver.\n"); |
489 | return 0; | |
490 | } | |
491 | ||
492 | static int __devexit at91_twi_remove(struct platform_device *pdev) | |
493 | { | |
494 | struct at91_twi_dev *dev = platform_get_drvdata(pdev); | |
495 | int rc; | |
496 | ||
497 | rc = i2c_del_adapter(&dev->adapter); | |
498 | clk_disable_unprepare(dev->clk); | |
499 | ||
500 | return rc; | |
501 | } | |
502 | ||
503 | #ifdef CONFIG_PM | |
504 | ||
505 | static int at91_twi_runtime_suspend(struct device *dev) | |
506 | { | |
507 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
508 | ||
509 | clk_disable(twi_dev->clk); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | static int at91_twi_runtime_resume(struct device *dev) | |
515 | { | |
516 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
517 | ||
518 | return clk_enable(twi_dev->clk); | |
519 | } | |
520 | ||
521 | static const struct dev_pm_ops at91_twi_pm = { | |
522 | .runtime_suspend = at91_twi_runtime_suspend, | |
523 | .runtime_resume = at91_twi_runtime_resume, | |
524 | }; | |
525 | ||
526 | #define at91_twi_pm_ops (&at91_twi_pm) | |
527 | #else | |
528 | #define at91_twi_pm_ops NULL | |
529 | #endif | |
530 | ||
531 | static struct platform_driver at91_twi_driver = { | |
532 | .probe = at91_twi_probe, | |
533 | .remove = __devexit_p(at91_twi_remove), | |
534 | .id_table = at91_twi_devtypes, | |
535 | .driver = { | |
536 | .name = "at91_i2c", | |
537 | .owner = THIS_MODULE, | |
70d46a24 | 538 | .of_match_table = atmel_twi_dt_ids, |
fac368a0 NV |
539 | .pm = at91_twi_pm_ops, |
540 | }, | |
541 | }; | |
542 | ||
543 | static int __init at91_twi_init(void) | |
544 | { | |
545 | return platform_driver_register(&at91_twi_driver); | |
546 | } | |
547 | ||
548 | static void __exit at91_twi_exit(void) | |
549 | { | |
550 | platform_driver_unregister(&at91_twi_driver); | |
551 | } | |
552 | ||
553 | subsys_initcall(at91_twi_init); | |
554 | module_exit(at91_twi_exit); | |
555 | ||
556 | MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>"); | |
557 | MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91"); | |
558 | MODULE_LICENSE("GPL"); | |
559 | MODULE_ALIAS("platform:at91_i2c"); |