[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-au1550.c

/*
 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
 *
 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
 *
 * The documentation describes this as an SMBus controller, but it doesn't
 * understand any of the SMBus protocol in hardware.  It's really an I2C
 * controller that could emulate most of the SMBus in software.
 *
 * This is just a skeleton adapter to use with the Au1550 PSC
 * algorithm.  It was developed for the Pb1550, but will work with
 * any Au1550 board that has a similar PSC configuration.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/slab.h>

#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#define PSC_SEL		0x00
#define PSC_CTRL	0x04
#define PSC_SMBCFG	0x08
#define PSC_SMBMSK	0x0C
#define PSC_SMBPCR	0x10
#define PSC_SMBSTAT	0x14
#define PSC_SMBEVNT	0x18
#define PSC_SMBTXRX	0x1C
#define PSC_SMBTMR	0x20

struct i2c_au1550_data {
	void __iomem *psc_base;
	int	xfer_timeout;
	struct i2c_adapter adap;
	struct resource *ioarea;
};

static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
{
	__raw_writel(v, a->psc_base + r);
	wmb();
}

static inline unsigned long RD(struct i2c_au1550_data *a, int r)
{
	return __raw_readl(a->psc_base + r);
}

static int wait_xfer_done(struct i2c_au1550_data *adap)
{
	int i;

	/* Wait for Tx Buffer Empty */
	for (i = 0; i < adap->xfer_timeout; i++) {
		if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
			return 0;

		udelay(1);
	}

	return -ETIMEDOUT;
}

static int wait_ack(struct i2c_au1550_data *adap)
{
	unsigned long stat;

	if (wait_xfer_done(adap))
		return -ETIMEDOUT;

	stat = RD(adap, PSC_SMBEVNT);
	if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
		return -ETIMEDOUT;

	return 0;
}

static int wait_master_done(struct i2c_au1550_data *adap)
{
	int i;

	/* Wait for Master Done. */
	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
		if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
			return 0;
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
{
	unsigned long stat;

	/* Reset the FIFOs, clear events. */
	stat = RD(adap, PSC_SMBSTAT);
	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);

	if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
		WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
		while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
			cpu_relax();
		udelay(50);
	}

	/* Write out the i2c chip address and specify operation */
	addr <<= 1;
	if (rd)
		addr |= 1;

	/* zero-byte xfers stop immediately */
	if (q)
		addr |= PSC_SMBTXRX_STP;

	/* Put byte into fifo, start up master. */
	WR(adap, PSC_SMBTXRX, addr);
	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
	if (wait_ack(adap))
		return -EIO;
	return (q) ? wait_master_done(adap) : 0;
}

static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
{
	int j;

	if (wait_xfer_done(adap))
		return -EIO;

	j =  adap->xfer_timeout * 100;
	do {
		j--;
		if (j <= 0)
			return -EIO;

		if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
			j = 0;
		else
			udelay(1);
	} while (j > 0);

	*out = RD(adap, PSC_SMBTXRX);

	return 0;
}

static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
		    unsigned int len)
{
	int i;

	if (len == 0)
		return 0;

	/* A read is performed by stuffing the transmit fifo with
	 * zero bytes for timing, waiting for bytes to appear in the
	 * receive fifo, then reading the bytes.
	 */
	i = 0;
	while (i < (len - 1)) {
		WR(adap, PSC_SMBTXRX, 0);
		if (wait_for_rx_byte(adap, &buf[i]))
			return -EIO;

		i++;
	}

	/* The last byte has to indicate transfer done. */
	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
	if (wait_master_done(adap))
		return -EIO;

	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
	return 0;
}

static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
		     unsigned int len)
{
	int i;
	unsigned long data;

	if (len == 0)
		return 0;

	i = 0;
	while (i < (len-1)) {
		data = buf[i];
		WR(adap, PSC_SMBTXRX, data);
		if (wait_ack(adap))
			return -EIO;
		i++;
	}

	/* The last byte has to indicate transfer done. */
	data = buf[i];
	data |= PSC_SMBTXRX_STP;
	WR(adap, PSC_SMBTXRX, data);
	if (wait_master_done(adap))
		return -EIO;
	return 0;
}

static int
au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
{
	struct i2c_au1550_data *adap = i2c_adap->algo_data;
	struct i2c_msg *p;
	int i, err = 0;

	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);

	for (i = 0; !err && i < num; i++) {
		p = &msgs[i];
		err = do_address(adap, p->addr, p->flags & I2C_M_RD,
				 (p->len == 0));
		if (err || !p->len)
			continue;
		if (p->flags & I2C_M_RD)
			err = i2c_read(adap, p->buf, p->len);
		else
			err = i2c_write(adap, p->buf, p->len);
	}

	/* Return the number of messages processed, or the error code.
	*/
	if (err == 0)
		err = num;

	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);

	return err;
}

static u32 au1550_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm au1550_algo = {
	.master_xfer	= au1550_xfer,
	.functionality	= au1550_func,
};

static void i2c_au1550_setup(struct i2c_au1550_data *priv)
{
	unsigned long cfg;

	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
	WR(priv, PSC_SMBCFG, 0);
	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
		cpu_relax();

	cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
	WR(priv, PSC_SMBCFG, cfg);

	/* Divide by 8 to get a 6.25 MHz clock.  The later protocol
	 * timings are based on this clock.
	 */
	cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
	WR(priv, PSC_SMBCFG, cfg);
	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);

	/* Set the protocol timer values.  See Table 71 in the
	 * Au1550 Data Book for standard timing values.
	 */
	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
		PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
		PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
		PSC_SMBTMR_SET_CH(15));

	cfg |= PSC_SMBCFG_DE_ENABLE;
	WR(priv, PSC_SMBCFG, cfg);
	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
		cpu_relax();

	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
}

static void i2c_au1550_disable(struct i2c_au1550_data *priv)
{
	WR(priv, PSC_SMBCFG, 0);
	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
}

/*
 * registering functions to load algorithms at runtime
 * Prior to calling us, the 50MHz clock frequency and routing
 * must have been set up for the PSC indicated by the adapter.
 */
static int __devinit
i2c_au1550_probe(struct platform_device *pdev)
{
	struct i2c_au1550_data *priv;
	struct resource *r;
	int ret;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		ret = -ENODEV;
		goto out;
	}

	priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL);
	if (!priv) {
		ret = -ENOMEM;
		goto out;
	}

	priv->ioarea = request_mem_region(r->start, resource_size(r),
					  pdev->name);
	if (!priv->ioarea) {
		ret = -EBUSY;
		goto out_mem;
	}

	priv->psc_base = ioremap(r->start, resource_size(r));
	if (!priv->psc_base) {
		ret = -EIO;
		goto out_map;
	}
	priv->xfer_timeout = 200;

	priv->adap.nr = pdev->id;
	priv->adap.algo = &au1550_algo;
	priv->adap.algo_data = priv;
	priv->adap.dev.parent = &pdev->dev;
	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));

	/* Now, set up the PSC for SMBus PIO mode. */
	i2c_au1550_setup(priv);

	ret = i2c_add_numbered_adapter(&priv->adap);
	if (ret == 0) {
		platform_set_drvdata(pdev, priv);
		return 0;
	}

	i2c_au1550_disable(priv);
	iounmap(priv->psc_base);
out_map:
	release_resource(priv->ioarea);
	kfree(priv->ioarea);
out_mem:
	kfree(priv);
out:
	return ret;
}

static int __devexit i2c_au1550_remove(struct platform_device *pdev)
{
	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);

	platform_set_drvdata(pdev, NULL);
	i2c_del_adapter(&priv->adap);
	i2c_au1550_disable(priv);
	iounmap(priv->psc_base);
	release_resource(priv->ioarea);
	kfree(priv->ioarea);
	kfree(priv);
	return 0;
}

#ifdef CONFIG_PM
static int i2c_au1550_suspend(struct device *dev)
{
	struct i2c_au1550_data *priv = dev_get_drvdata(dev);

	i2c_au1550_disable(priv);

	return 0;
}

static int i2c_au1550_resume(struct device *dev)
{
	struct i2c_au1550_data *priv = dev_get_drvdata(dev);

	i2c_au1550_setup(priv);

	return 0;
}

static const struct dev_pm_ops i2c_au1550_pmops = {
	.suspend	= i2c_au1550_suspend,
	.resume		= i2c_au1550_resume,
};

#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)

#else
#define AU1XPSC_SMBUS_PMOPS NULL
#endif

static struct platform_driver au1xpsc_smbus_driver = {
	.driver = {
		.name	= "au1xpsc_smbus",
		.owner	= THIS_MODULE,
		.pm	= AU1XPSC_SMBUS_PMOPS,
	},
	.probe		= i2c_au1550_probe,
	.remove		= __devexit_p(i2c_au1550_remove),
};

module_platform_driver(au1xpsc_smbus_driver);

MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:au1xpsc_smbus");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
	3	* Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
	4	*
	5	* 2.6 port by Matt Porter <mporter@kernel.crashing.org>
	6	*
	7	* The documentation describes this as an SMBus controller, but it doesn't
	8	* understand any of the SMBus protocol in hardware. It's really an I2C
	9	* controller that could emulate most of the SMBus in software.
	10	*
	11	* This is just a skeleton adapter to use with the Au1550 PSC
	12	* algorithm. It was developed for the Pb1550, but will work with
	13	* any Au1550 board that has a similar PSC configuration.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	28	*/
	29
1da177e4 LT	30	#include <linux/delay.h>
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
8b798c4d	33	#include <linux/platform_device.h>
1da177e4 LT	34	#include <linux/init.h>
	35	#include <linux/errno.h>
	36	#include <linux/i2c.h>
8b798c4d	37	#include <linux/slab.h>
1da177e4	38
50d5676e	39	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	40	#include <asm/mach-au1x00/au1xxx_psc.h>
1da177e4 LT	41
c5de6467 ML	42	#define PSC_SEL 0x00
	43	#define PSC_CTRL 0x04
	44	#define PSC_SMBCFG 0x08
	45	#define PSC_SMBMSK 0x0C
	46	#define PSC_SMBPCR 0x10
	47	#define PSC_SMBSTAT 0x14
	48	#define PSC_SMBEVNT 0x18
	49	#define PSC_SMBTXRX 0x1C
	50	#define PSC_SMBTMR 0x20
	51
8b798c4d	52	struct i2c_au1550_data {
c5de6467	53	void __iomem *psc_base;
8b798c4d	54	int xfer_timeout;
8b798c4d ML	55	struct i2c_adapter adap;
	56	struct resource *ioarea;
	57	};
1da177e4	58
c5de6467	59	static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
1da177e4	60	{
c5de6467 ML	61	__raw_writel(v, a->psc_base + r);
	62	wmb();
	63	}
1da177e4	64
c5de6467 ML	65	static inline unsigned long RD(struct i2c_au1550_data *a, int r)
	66	{
	67	return __raw_readl(a->psc_base + r);
	68	}
1da177e4	69
c5de6467 ML	70	static int wait_xfer_done(struct i2c_au1550_data *adap)
	71	{
	72	int i;
	73
	74	/* Wait for Tx Buffer Empty */
1da177e4	75	for (i = 0; i < adap->xfer_timeout; i++) {
c5de6467	76	if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
1da177e4	77	return 0;
a202707e	78
1da177e4 LT	79	udelay(1);
	80	}
	81
	82	return -ETIMEDOUT;
	83	}
	84
c5de6467	85	static int wait_ack(struct i2c_au1550_data *adap)
1da177e4	86	{
c5de6467	87	unsigned long stat;
1da177e4 LT	88
	89	if (wait_xfer_done(adap))
	90	return -ETIMEDOUT;
	91
c5de6467	92	stat = RD(adap, PSC_SMBEVNT);
1da177e4 LT	93	if ((stat & (PSC_SMBEVNT_DN \| PSC_SMBEVNT_AN \| PSC_SMBEVNT_AL)) != 0)
	94	return -ETIMEDOUT;
	95
	96	return 0;
	97	}
	98
c5de6467	99	static int wait_master_done(struct i2c_au1550_data *adap)
1da177e4	100	{
c5de6467	101	int i;
1da177e4	102
c5de6467	103	/* Wait for Master Done. */
84785f12	104	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
c5de6467	105	if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
1da177e4 LT	106	return 0;
	107	udelay(1);
	108	}
	109
	110	return -ETIMEDOUT;
	111	}
	112
	113	static int
91f27958	114	do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
1da177e4	115	{
c5de6467	116	unsigned long stat;
1da177e4	117
c5de6467 ML	118	/* Reset the FIFOs, clear events. */
	119	stat = RD(adap, PSC_SMBSTAT);
	120	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
8859942e DP	121
8859942e DP	122	if (!(stat & PSC_SMBSTAT_TE) \|\| !(stat & PSC_SMBSTAT_RE)) {
c5de6467 ML	123	WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
	124	while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
	125	cpu_relax();
8859942e DP	126	udelay(50);
8859942e DP	127	}
1da177e4	128
c5de6467	129	/* Write out the i2c chip address and specify operation */
1da177e4 LT	130	addr <<= 1;
	131	if (rd)
	132	addr \|= 1;
	133
91f27958 ML	134	/* zero-byte xfers stop immediately */
	135	if (q)
	136	addr \|= PSC_SMBTXRX_STP;
	137
c5de6467 ML	138	/* Put byte into fifo, start up master. */
	139	WR(adap, PSC_SMBTXRX, addr);
	140	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
1da177e4 LT	141	if (wait_ack(adap))
1da177e4 LT	142	return -EIO;
91f27958	143	return (q) ? wait_master_done(adap) : 0;
1da177e4 LT	144	}
1da177e4 LT	145
c5de6467	146	static int wait_for_rx_byte(struct i2c_au1550_data adap, unsigned char out)
1da177e4	147	{
c5de6467	148	int j;
1da177e4 LT	149
	150	if (wait_xfer_done(adap))
	151	return -EIO;
	152
1da177e4 LT	153	j = adap->xfer_timeout * 100;
	154	do {
	155	j--;
	156	if (j <= 0)
	157	return -EIO;
	158
c5de6467	159	if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
1da177e4 LT	160	j = 0;
	161	else
	162	udelay(1);
	163	} while (j > 0);
c5de6467 ML	164
c5de6467 ML	165	*out = RD(adap, PSC_SMBTXRX);
1da177e4 LT	166
	167	return 0;
	168	}
	169
c5de6467	170	static int i2c_read(struct i2c_au1550_data adap, unsigned char buf,
1da177e4 LT	171	unsigned int len)
1da177e4 LT	172	{
c5de6467	173	int i;
1da177e4 LT	174
	175	if (len == 0)
	176	return 0;
	177
	178	/* A read is performed by stuffing the transmit fifo with
	179	* zero bytes for timing, waiting for bytes to appear in the
	180	* receive fifo, then reading the bytes.
	181	*/
1da177e4	182	i = 0;
c5de6467 ML	183	while (i < (len - 1)) {
	184	WR(adap, PSC_SMBTXRX, 0);
	185	if (wait_for_rx_byte(adap, &buf[i]))
1da177e4 LT	186	return -EIO;
1da177e4 LT	187
1da177e4 LT	188	i++;
	189	}
	190
c5de6467 ML	191	/* The last byte has to indicate transfer done. */
c5de6467 ML	192	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
1da177e4 LT	193	if (wait_master_done(adap))
	194	return -EIO;
	195
c5de6467	196	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
1da177e4 LT	197	return 0;
	198	}
	199
c5de6467	200	static int i2c_write(struct i2c_au1550_data adap, unsigned char buf,
1da177e4 LT	201	unsigned int len)
1da177e4 LT	202	{
c5de6467 ML	203	int i;
c5de6467 ML	204	unsigned long data;
1da177e4 LT	205
	206	if (len == 0)
	207	return 0;
	208
1da177e4 LT	209	i = 0;
	210	while (i < (len-1)) {
	211	data = buf[i];
c5de6467	212	WR(adap, PSC_SMBTXRX, data);
1da177e4 LT	213	if (wait_ack(adap))
	214	return -EIO;
	215	i++;
	216	}
	217
c5de6467	218	/* The last byte has to indicate transfer done. */
1da177e4 LT	219	data = buf[i];
1da177e4 LT	220	data \|= PSC_SMBTXRX_STP;
c5de6467	221	WR(adap, PSC_SMBTXRX, data);
1da177e4 LT	222	if (wait_master_done(adap))
	223	return -EIO;
	224	return 0;
	225	}
	226
	227	static int
	228	au1550_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs, int num)
	229	{
	230	struct i2c_au1550_data *adap = i2c_adap->algo_data;
	231	struct i2c_msg *p;
	232	int i, err = 0;
	233
c5de6467	234	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
f09f71b2	235
1da177e4 LT	236	for (i = 0; !err && i < num; i++) {
1da177e4 LT	237	p = &msgs[i];
91f27958 ML	238	err = do_address(adap, p->addr, p->flags & I2C_M_RD,
91f27958 ML	239	(p->len == 0));
1da177e4 LT	240	if (err \|\| !p->len)
	241	continue;
	242	if (p->flags & I2C_M_RD)
	243	err = i2c_read(adap, p->buf, p->len);
	244	else
	245	err = i2c_write(adap, p->buf, p->len);
	246	}
	247
	248	/* Return the number of messages processed, or the error code.
	249	*/
	250	if (err == 0)
	251	err = num;
f09f71b2	252
c5de6467	253	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
f09f71b2	254
1da177e4 LT	255	return err;
	256	}
	257
c5de6467	258	static u32 au1550_func(struct i2c_adapter *adap)
1da177e4	259	{
6ed07134	260	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
1da177e4 LT	261	}
1da177e4 LT	262
8f9082c5	263	static const struct i2c_algorithm au1550_algo = {
1da177e4 LT	264	.master_xfer = au1550_xfer,
	265	.functionality = au1550_func,
	266	};
	267
f09f71b2 ML	268	static void i2c_au1550_setup(struct i2c_au1550_data *priv)
f09f71b2 ML	269	{
c5de6467	270	unsigned long cfg;
f09f71b2	271
c5de6467 ML	272	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
	273	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
	274	WR(priv, PSC_SMBCFG, 0);
	275	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
	276	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
	277	cpu_relax();
	278
	279	cfg = PSC_SMBCFG_RT_FIFO8 \| PSC_SMBCFG_TT_FIFO8 \| PSC_SMBCFG_DD_DISABLE;
	280	WR(priv, PSC_SMBCFG, cfg);
f09f71b2 ML	281
	282	/* Divide by 8 to get a 6.25 MHz clock. The later protocol
	283	* timings are based on this clock.
	284	*/
c5de6467 ML	285	cfg \|= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
	286	WR(priv, PSC_SMBCFG, cfg);
	287	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
f09f71b2 ML	288
	289	/* Set the protocol timer values. See Table 71 in the
	290	* Au1550 Data Book for standard timing values.
	291	*/
c5de6467	292	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) \| PSC_SMBTMR_SET_PS(15) \| \
f09f71b2 ML	293	PSC_SMBTMR_SET_PU(15) \| PSC_SMBTMR_SET_SH(15) \| \
f09f71b2 ML	294	PSC_SMBTMR_SET_SU(15) \| PSC_SMBTMR_SET_CL(15) \| \
c5de6467	295	PSC_SMBTMR_SET_CH(15));
f09f71b2	296
c5de6467 ML	297	cfg \|= PSC_SMBCFG_DE_ENABLE;
	298	WR(priv, PSC_SMBCFG, cfg);
	299	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
	300	cpu_relax();
f09f71b2	301
c5de6467	302	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
f09f71b2 ML	303	}
	304
	305	static void i2c_au1550_disable(struct i2c_au1550_data *priv)
	306	{
c5de6467 ML	307	WR(priv, PSC_SMBCFG, 0);
c5de6467 ML	308	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
f09f71b2 ML	309	}
f09f71b2 ML	310
1da177e4 LT	311	/*
	312	* registering functions to load algorithms at runtime
	313	* Prior to calling us, the 50MHz clock frequency and routing
	314	* must have been set up for the PSC indicated by the adapter.
	315	*/
8b798c4d ML	316	static int __devinit
8b798c4d ML	317	i2c_au1550_probe(struct platform_device *pdev)
1da177e4	318	{
8b798c4d	319	struct i2c_au1550_data *priv;
8b798c4d	320	struct resource *r;
8b798c4d ML	321	int ret;
	322
	323	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	324	if (!r) {
	325	ret = -ENODEV;
	326	goto out;
	327	}
1da177e4	328
8b798c4d ML	329	priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL);
	330	if (!priv) {
	331	ret = -ENOMEM;
	332	goto out;
	333	}
	334
c6ffddea	335	priv->ioarea = request_mem_region(r->start, resource_size(r),
8b798c4d ML	336	pdev->name);
	337	if (!priv->ioarea) {
	338	ret = -EBUSY;
	339	goto out_mem;
	340	}
	341
c5de6467 ML	342	priv->psc_base = ioremap(r->start, resource_size(r));
	343	if (!priv->psc_base) {
	344	ret = -EIO;
	345	goto out_map;
	346	}
8b798c4d	347	priv->xfer_timeout = 200;
8b798c4d	348
8b798c4d ML	349	priv->adap.nr = pdev->id;
	350	priv->adap.algo = &au1550_algo;
	351	priv->adap.algo_data = priv;
	352	priv->adap.dev.parent = &pdev->dev;
	353	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
1da177e4	354
c5de6467	355	/* Now, set up the PSC for SMBus PIO mode. */
f09f71b2	356	i2c_au1550_setup(priv);
1da177e4	357
8b798c4d ML	358	ret = i2c_add_numbered_adapter(&priv->adap);
	359	if (ret == 0) {
	360	platform_set_drvdata(pdev, priv);
	361	return 0;
	362	}
	363
f09f71b2	364	i2c_au1550_disable(priv);
c5de6467 ML	365	iounmap(priv->psc_base);
c5de6467 ML	366	out_map:
8b798c4d ML	367	release_resource(priv->ioarea);
	368	kfree(priv->ioarea);
	369	out_mem:
	370	kfree(priv);
	371	out:
	372	return ret;
	373	}
1da177e4	374
c5de6467	375	static int __devexit i2c_au1550_remove(struct platform_device *pdev)
1da177e4	376	{
8b798c4d	377	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
8b798c4d ML	378
	379	platform_set_drvdata(pdev, NULL);
	380	i2c_del_adapter(&priv->adap);
f09f71b2	381	i2c_au1550_disable(priv);
c5de6467	382	iounmap(priv->psc_base);
8b798c4d ML	383	release_resource(priv->ioarea);
	384	kfree(priv->ioarea);
	385	kfree(priv);
	386	return 0;
1da177e4 LT	387	}
1da177e4 LT	388
f09f71b2	389	#ifdef CONFIG_PM
46f344e2	390	static int i2c_au1550_suspend(struct device *dev)
1da177e4	391	{
46f344e2	392	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
8b798c4d	393
f09f71b2 ML	394	i2c_au1550_disable(priv);
f09f71b2 ML	395
1da177e4 LT	396	return 0;
	397	}
	398
46f344e2	399	static int i2c_au1550_resume(struct device *dev)
1da177e4	400	{
46f344e2	401	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
8b798c4d	402
f09f71b2 ML	403	i2c_au1550_setup(priv);
f09f71b2 ML	404
1da177e4 LT	405	return 0;
1da177e4 LT	406	}
46f344e2 ML	407
	408	static const struct dev_pm_ops i2c_au1550_pmops = {
	409	.suspend = i2c_au1550_suspend,
	410	.resume = i2c_au1550_resume,
	411	};
	412
	413	#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
	414
f09f71b2	415	#else
46f344e2	416	#define AU1XPSC_SMBUS_PMOPS NULL
f09f71b2	417	#endif
1da177e4	418
8b798c4d ML	419	static struct platform_driver au1xpsc_smbus_driver = {
	420	.driver = {
	421	.name = "au1xpsc_smbus",
	422	.owner = THIS_MODULE,
46f344e2	423	.pm = AU1XPSC_SMBUS_PMOPS,
8b798c4d ML	424	},
	425	.probe = i2c_au1550_probe,
	426	.remove = __devexit_p(i2c_au1550_remove),
1da177e4 LT	427	};
1da177e4 LT	428
a3664b51	429	module_platform_driver(au1xpsc_smbus_driver);
1da177e4 LT	430
	431	MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
	432	MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
	433	MODULE_LICENSE("GPL");
add8eda7	434	MODULE_ALIAS("platform:au1xpsc_smbus");