[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-bcm2835.c

/*
 * BCM2835 master mode driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define BCM2835_I2C_C		0x0
#define BCM2835_I2C_S		0x4
#define BCM2835_I2C_DLEN	0x8
#define BCM2835_I2C_A		0xc
#define BCM2835_I2C_FIFO	0x10
#define BCM2835_I2C_DIV		0x14
#define BCM2835_I2C_DEL		0x18
#define BCM2835_I2C_CLKT	0x1c

#define BCM2835_I2C_C_READ	BIT(0)
#define BCM2835_I2C_C_CLEAR	BIT(4) /* bits 4 and 5 both clear */
#define BCM2835_I2C_C_ST	BIT(7)
#define BCM2835_I2C_C_INTD	BIT(8)
#define BCM2835_I2C_C_INTT	BIT(9)
#define BCM2835_I2C_C_INTR	BIT(10)
#define BCM2835_I2C_C_I2CEN	BIT(15)

#define BCM2835_I2C_S_TA	BIT(0)
#define BCM2835_I2C_S_DONE	BIT(1)
#define BCM2835_I2C_S_TXW	BIT(2)
#define BCM2835_I2C_S_RXR	BIT(3)
#define BCM2835_I2C_S_TXD	BIT(4)
#define BCM2835_I2C_S_RXD	BIT(5)
#define BCM2835_I2C_S_TXE	BIT(6)
#define BCM2835_I2C_S_RXF	BIT(7)
#define BCM2835_I2C_S_ERR	BIT(8)
#define BCM2835_I2C_S_CLKT	BIT(9)
#define BCM2835_I2C_S_LEN	BIT(10) /* Fake bit for SW error reporting */

#define BCM2835_I2C_CDIV_MIN	0x0002
#define BCM2835_I2C_CDIV_MAX	0xFFFE

struct bcm2835_i2c_dev {
	struct device *dev;
	void __iomem *regs;
	struct clk *clk;
	int irq;
	u32 bus_clk_rate;
	struct i2c_adapter adapter;
	struct completion completion;
	struct i2c_msg *curr_msg;
	int num_msgs;
	u32 msg_err;
	u8 *msg_buf;
	size_t msg_buf_remaining;
};

static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
				      u32 reg, u32 val)
{
	writel(val, i2c_dev->regs + reg);
}

static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
{
	return readl(i2c_dev->regs + reg);
}

static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 divider;

	divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
			       i2c_dev->bus_clk_rate);
	/*
	 * Per the datasheet, the register is always interpreted as an even
	 * number, by rounding down. In other words, the LSB is ignored. So,
	 * if the LSB is set, increment the divider to avoid any issue.
	 */
	if (divider & 1)
		divider++;
	if ((divider < BCM2835_I2C_CDIV_MIN) ||
	    (divider > BCM2835_I2C_CDIV_MAX)) {
		dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
		return -EINVAL;
	}

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);

	return 0;
}

static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 val;

	while (i2c_dev->msg_buf_remaining) {
		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
		if (!(val & BCM2835_I2C_S_TXD))
			break;
		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
				   *i2c_dev->msg_buf);
		i2c_dev->msg_buf++;
		i2c_dev->msg_buf_remaining--;
	}
}

static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 val;

	while (i2c_dev->msg_buf_remaining) {
		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
		if (!(val & BCM2835_I2C_S_RXD))
			break;
		*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
						      BCM2835_I2C_FIFO);
		i2c_dev->msg_buf++;
		i2c_dev->msg_buf_remaining--;
	}
}

/*
 * Repeated Start Condition (Sr)
 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
 * talks about reading from a slave with 10 bit address. This is achieved by
 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
 * issue a read.
 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
 * firmware actually does it using polling and says that it's a workaround for
 * a problem in the state machine.
 * It turns out that it is possible to use the TXW interrupt to know when the
 * transfer is active, provided the FIFO has not been prefilled.
 */

static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
	struct i2c_msg *msg = i2c_dev->curr_msg;
	bool last_msg = (i2c_dev->num_msgs == 1);

	if (!i2c_dev->num_msgs)
		return;

	i2c_dev->num_msgs--;
	i2c_dev->msg_buf = msg->buf;
	i2c_dev->msg_buf_remaining = msg->len;

	if (msg->flags & I2C_M_RD)
		c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
	else
		c |= BCM2835_I2C_C_INTT;

	if (last_msg)
		c |= BCM2835_I2C_C_INTD;

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
}

/*
 * Note about I2C_C_CLEAR on error:
 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
 * the state machine to send a NACK and a STOP. Since we're setting CLEAR
 * without I2CEN, that NACK will be hanging around queued up for next time
 * we start the engine.
 */

static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
{
	struct bcm2835_i2c_dev *i2c_dev = data;
	u32 val, err;

	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);

	err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
	if (err) {
		i2c_dev->msg_err = err;
		goto complete;
	}

	if (val & BCM2835_I2C_S_DONE) {
		if (!i2c_dev->curr_msg) {
			dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
		} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
			bcm2835_drain_rxfifo(i2c_dev);
			val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
		}

		if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
			i2c_dev->msg_err = BCM2835_I2C_S_LEN;
		else
			i2c_dev->msg_err = 0;
		goto complete;
	}

	if (val & BCM2835_I2C_S_TXW) {
		if (!i2c_dev->msg_buf_remaining) {
			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
			goto complete;
		}

		bcm2835_fill_txfifo(i2c_dev);

		if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
			i2c_dev->curr_msg++;
			bcm2835_i2c_start_transfer(i2c_dev);
		}

		return IRQ_HANDLED;
	}

	if (val & BCM2835_I2C_S_RXR) {
		if (!i2c_dev->msg_buf_remaining) {
			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
			goto complete;
		}

		bcm2835_drain_rxfifo(i2c_dev);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;

complete:
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
			   BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
	complete(&i2c_dev->completion);

	return IRQ_HANDLED;
}

static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
			    int num)
{
	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
	unsigned long time_left;
	int i, ret;

	for (i = 0; i < (num - 1); i++)
		if (msgs[i].flags & I2C_M_RD) {
			dev_warn_once(i2c_dev->dev,
				      "only one read message supported, has to be last\n");
			return -EOPNOTSUPP;
		}

	ret = bcm2835_i2c_set_divider(i2c_dev);
	if (ret)
		return ret;

	i2c_dev->curr_msg = msgs;
	i2c_dev->num_msgs = num;
	reinit_completion(&i2c_dev->completion);

	bcm2835_i2c_start_transfer(i2c_dev);

	time_left = wait_for_completion_timeout(&i2c_dev->completion,
						adap->timeout);
	if (!time_left) {
		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
				   BCM2835_I2C_C_CLEAR);
		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
		return -ETIMEDOUT;
	}

	if (!i2c_dev->msg_err)
		return num;

	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);

	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
		return -EREMOTEIO;

	return -EIO;
}

static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm bcm2835_i2c_algo = {
	.master_xfer	= bcm2835_i2c_xfer,
	.functionality	= bcm2835_i2c_func,
};

/*
 * This HW was reported to have problems with clock stretching:
 * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
 */
static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
	.flags = I2C_AQ_NO_CLK_STRETCH,
};

static int bcm2835_i2c_probe(struct platform_device *pdev)
{
	struct bcm2835_i2c_dev *i2c_dev;
	struct resource *mem, *irq;
	int ret;
	struct i2c_adapter *adap;

	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
	if (!i2c_dev)
		return -ENOMEM;
	platform_set_drvdata(pdev, i2c_dev);
	i2c_dev->dev = &pdev->dev;
	init_completion(&i2c_dev->completion);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(i2c_dev->regs))
		return PTR_ERR(i2c_dev->regs);

	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2c_dev->clk)) {
		if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Could not get clock\n");
		return PTR_ERR(i2c_dev->clk);
	}

	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
				   &i2c_dev->bus_clk_rate);
	if (ret < 0) {
		dev_warn(&pdev->dev,
			 "Could not read clock-frequency property\n");
		i2c_dev->bus_clk_rate = 100000;
	}

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq) {
		dev_err(&pdev->dev, "No IRQ resource\n");
		return -ENODEV;
	}
	i2c_dev->irq = irq->start;

	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
			  dev_name(&pdev->dev), i2c_dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not request IRQ\n");
		return -ENODEV;
	}

	adap = &i2c_dev->adapter;
	i2c_set_adapdata(adap, i2c_dev);
	adap->owner = THIS_MODULE;
	adap->class = I2C_CLASS_DEPRECATED;
	strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
	adap->algo = &bcm2835_i2c_algo;
	adap->dev.parent = &pdev->dev;
	adap->dev.of_node = pdev->dev.of_node;
	adap->quirks = &bcm2835_i2c_quirks;

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);

	ret = i2c_add_adapter(adap);
	if (ret)
		free_irq(i2c_dev->irq, i2c_dev);

	return ret;
}

static int bcm2835_i2c_remove(struct platform_device *pdev)
{
	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);

	free_irq(i2c_dev->irq, i2c_dev);
	i2c_del_adapter(&i2c_dev->adapter);

	return 0;
}

static const struct of_device_id bcm2835_i2c_of_match[] = {
	{ .compatible = "brcm,bcm2835-i2c" },
	{},
};
MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);

static struct platform_driver bcm2835_i2c_driver = {
	.probe		= bcm2835_i2c_probe,
	.remove		= bcm2835_i2c_remove,
	.driver		= {
		.name	= "i2c-bcm2835",
		.of_match_table = bcm2835_i2c_of_match,
	},
};
module_platform_driver(bcm2835_i2c_driver);

MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:i2c-bcm2835");
Commit	Line	Data
f3b54b9a SW	1	/*
	2	* BCM2835 master mode driver
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/completion.h>
	16	#include <linux/err.h>
	17	#include <linux/i2c.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/io.h>
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/slab.h>
	23
	24	#define BCM2835_I2C_C 0x0
	25	#define BCM2835_I2C_S 0x4
	26	#define BCM2835_I2C_DLEN 0x8
	27	#define BCM2835_I2C_A 0xc
	28	#define BCM2835_I2C_FIFO 0x10
	29	#define BCM2835_I2C_DIV 0x14
	30	#define BCM2835_I2C_DEL 0x18
	31	#define BCM2835_I2C_CLKT 0x1c
	32
	33	#define BCM2835_I2C_C_READ BIT(0)
	34	#define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */
	35	#define BCM2835_I2C_C_ST BIT(7)
	36	#define BCM2835_I2C_C_INTD BIT(8)
	37	#define BCM2835_I2C_C_INTT BIT(9)
	38	#define BCM2835_I2C_C_INTR BIT(10)
	39	#define BCM2835_I2C_C_I2CEN BIT(15)
	40
	41	#define BCM2835_I2C_S_TA BIT(0)
	42	#define BCM2835_I2C_S_DONE BIT(1)
	43	#define BCM2835_I2C_S_TXW BIT(2)
	44	#define BCM2835_I2C_S_RXR BIT(3)
	45	#define BCM2835_I2C_S_TXD BIT(4)
	46	#define BCM2835_I2C_S_RXD BIT(5)
	47	#define BCM2835_I2C_S_TXE BIT(6)
	48	#define BCM2835_I2C_S_RXF BIT(7)
	49	#define BCM2835_I2C_S_ERR BIT(8)
	50	#define BCM2835_I2C_S_CLKT BIT(9)
	51	#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
	52
a294aba1 SW	53	#define BCM2835_I2C_CDIV_MIN 0x0002
	54	#define BCM2835_I2C_CDIV_MAX 0xFFFE
	55
f3b54b9a SW	56	struct bcm2835_i2c_dev {
	57	struct device *dev;
	58	void __iomem *regs;
	59	struct clk *clk;
	60	int irq;
9446f62e	61	u32 bus_clk_rate;
f3b54b9a SW	62	struct i2c_adapter adapter;
f3b54b9a SW	63	struct completion completion;
e2474541	64	struct i2c_msg *curr_msg;
ee05fea2	65	int num_msgs;
f3b54b9a SW	66	u32 msg_err;
	67	u8 *msg_buf;
	68	size_t msg_buf_remaining;
	69	};
	70
	71	static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
	72	u32 reg, u32 val)
	73	{
	74	writel(val, i2c_dev->regs + reg);
	75	}
	76
	77	static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
	78	{
	79	return readl(i2c_dev->regs + reg);
	80	}
	81
9446f62e NT	82	static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
	83	{
	84	u32 divider;
	85
	86	divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
	87	i2c_dev->bus_clk_rate);
	88	/*
	89	* Per the datasheet, the register is always interpreted as an even
	90	* number, by rounding down. In other words, the LSB is ignored. So,
	91	* if the LSB is set, increment the divider to avoid any issue.
	92	*/
	93	if (divider & 1)
	94	divider++;
	95	if ((divider < BCM2835_I2C_CDIV_MIN) \|\|
	96	(divider > BCM2835_I2C_CDIV_MAX)) {
	97	dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
	98	return -EINVAL;
	99	}
	100
	101	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
	102
	103	return 0;
	104	}
	105
f3b54b9a SW	106	static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
	107	{
	108	u32 val;
	109
	110	while (i2c_dev->msg_buf_remaining) {
	111	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
	112	if (!(val & BCM2835_I2C_S_TXD))
	113	break;
	114	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
	115	*i2c_dev->msg_buf);
	116	i2c_dev->msg_buf++;
	117	i2c_dev->msg_buf_remaining--;
	118	}
	119	}
	120
	121	static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
	122	{
	123	u32 val;
	124
	125	while (i2c_dev->msg_buf_remaining) {
	126	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
	127	if (!(val & BCM2835_I2C_S_RXD))
	128	break;
	129	*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
	130	BCM2835_I2C_FIFO);
	131	i2c_dev->msg_buf++;
	132	i2c_dev->msg_buf_remaining--;
	133	}
	134	}
	135
ee05fea2 NT	136	/*
	137	* Repeated Start Condition (Sr)
	138	* The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
	139	* talks about reading from a slave with 10 bit address. This is achieved by
	140	* issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
	141	* issue a read.
	142	* A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
	143	* firmware actually does it using polling and says that it's a workaround for
	144	* a problem in the state machine.
	145	* It turns out that it is possible to use the TXW interrupt to know when the
	146	* transfer is active, provided the FIFO has not been prefilled.
	147	*/
	148
	149	static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
	150	{
	151	u32 c = BCM2835_I2C_C_ST \| BCM2835_I2C_C_I2CEN;
	152	struct i2c_msg *msg = i2c_dev->curr_msg;
	153	bool last_msg = (i2c_dev->num_msgs == 1);
	154
	155	if (!i2c_dev->num_msgs)
	156	return;
	157
	158	i2c_dev->num_msgs--;
	159	i2c_dev->msg_buf = msg->buf;
	160	i2c_dev->msg_buf_remaining = msg->len;
	161
	162	if (msg->flags & I2C_M_RD)
	163	c \|= BCM2835_I2C_C_READ \| BCM2835_I2C_C_INTR;
	164	else
	165	c \|= BCM2835_I2C_C_INTT;
	166
	167	if (last_msg)
	168	c \|= BCM2835_I2C_C_INTD;
	169
	170	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
	171	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
	172	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
	173	}
	174
d4030d75 NT	175	/*
	176	* Note about I2C_C_CLEAR on error:
	177	* The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
	178	* non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
	179	* the state machine to send a NACK and a STOP. Since we're setting CLEAR
	180	* without I2CEN, that NACK will be hanging around queued up for next time
	181	* we start the engine.
	182	*/
	183
f3b54b9a SW	184	static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
	185	{
	186	struct bcm2835_i2c_dev *i2c_dev = data;
	187	u32 val, err;
	188
	189	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
f3b54b9a SW	190
	191	err = val & (BCM2835_I2C_S_CLKT \| BCM2835_I2C_S_ERR);
	192	if (err) {
	193	i2c_dev->msg_err = err;
d4030d75	194	goto complete;
f3b54b9a SW	195	}
f3b54b9a SW	196
f3b54b9a	197	if (val & BCM2835_I2C_S_DONE) {
ababb089 SW	198	if (!i2c_dev->curr_msg) {
	199	dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
	200	} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
e2474541 NT	201	bcm2835_drain_rxfifo(i2c_dev);
	202	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
	203	}
	204
	205	if ((val & BCM2835_I2C_S_RXD) \|\| i2c_dev->msg_buf_remaining)
f3b54b9a SW	206	i2c_dev->msg_err = BCM2835_I2C_S_LEN;
	207	else
	208	i2c_dev->msg_err = 0;
d4030d75	209	goto complete;
f3b54b9a SW	210	}
f3b54b9a SW	211
e2474541	212	if (val & BCM2835_I2C_S_TXW) {
d4030d75 NT	213	if (!i2c_dev->msg_buf_remaining) {
	214	i2c_dev->msg_err = val \| BCM2835_I2C_S_LEN;
	215	goto complete;
	216	}
	217
f3b54b9a	218	bcm2835_fill_txfifo(i2c_dev);
ee05fea2 NT	219
	220	if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
	221	i2c_dev->curr_msg++;
	222	bcm2835_i2c_start_transfer(i2c_dev);
	223	}
	224
f3b54b9a SW	225	return IRQ_HANDLED;
	226	}
	227
e2474541	228	if (val & BCM2835_I2C_S_RXR) {
d4030d75 NT	229	if (!i2c_dev->msg_buf_remaining) {
	230	i2c_dev->msg_err = val \| BCM2835_I2C_S_LEN;
	231	goto complete;
	232	}
	233
e2474541 NT	234	bcm2835_drain_rxfifo(i2c_dev);
	235	return IRQ_HANDLED;
	236	}
	237
f3b54b9a	238	return IRQ_NONE;
d4030d75 NT	239
	240	complete:
	241	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
	242	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT \|
	243	BCM2835_I2C_S_ERR \| BCM2835_I2C_S_DONE);
	244	complete(&i2c_dev->completion);
	245
	246	return IRQ_HANDLED;
f3b54b9a SW	247	}
f3b54b9a SW	248
ee05fea2 NT	249	static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
ee05fea2 NT	250	int num)
f3b54b9a	251	{
ee05fea2	252	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
c4dc1216	253	unsigned long time_left;
9446f62e	254	int i, ret;
f3b54b9a	255
ee05fea2 NT	256	for (i = 0; i < (num - 1); i++)
	257	if (msgs[i].flags & I2C_M_RD) {
	258	dev_warn_once(i2c_dev->dev,
	259	"only one read message supported, has to be last\n");
	260	return -EOPNOTSUPP;
	261	}
f3b54b9a	262
9446f62e NT	263	ret = bcm2835_i2c_set_divider(i2c_dev);
	264	if (ret)
	265	return ret;
	266
ee05fea2 NT	267	i2c_dev->curr_msg = msgs;
	268	i2c_dev->num_msgs = num;
	269	reinit_completion(&i2c_dev->completion);
f3b54b9a	270
ee05fea2	271	bcm2835_i2c_start_transfer(i2c_dev);
f3b54b9a SW	272
f3b54b9a SW	273	time_left = wait_for_completion_timeout(&i2c_dev->completion,
e13e19e1	274	adap->timeout);
f3b54b9a	275	if (!time_left) {
d4030d75 NT	276	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
d4030d75 NT	277	BCM2835_I2C_C_CLEAR);
f3b54b9a SW	278	dev_err(i2c_dev->dev, "i2c transfer timed out\n");
	279	return -ETIMEDOUT;
	280	}
	281
ee05fea2 NT	282	if (!i2c_dev->msg_err)
ee05fea2 NT	283	return num;
f3b54b9a	284
23c9540b	285	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
f3b54b9a SW	286
	287	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
	288	return -EREMOTEIO;
f3b54b9a	289
ee05fea2	290	return -EIO;
f3b54b9a SW	291	}
	292
	293	static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
	294	{
	295	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	296	}
	297
	298	static const struct i2c_algorithm bcm2835_i2c_algo = {
	299	.master_xfer = bcm2835_i2c_xfer,
	300	.functionality = bcm2835_i2c_func,
	301	};
	302
4dbfb5f4 NC	303	/*
	304	* This HW was reported to have problems with clock stretching:
	305	* http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
	306	* https://www.raspberrypi.org/forums/viewtopic.php?p=146272
	307	*/
	308	static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
	309	.flags = I2C_AQ_NO_CLK_STRETCH,
	310	};
	311
f3b54b9a SW	312	static int bcm2835_i2c_probe(struct platform_device *pdev)
	313	{
	314	struct bcm2835_i2c_dev *i2c_dev;
ae50b1df	315	struct resource mem, irq;
f3b54b9a SW	316	int ret;
	317	struct i2c_adapter *adap;
	318
	319	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
46797a2a	320	if (!i2c_dev)
f3b54b9a	321	return -ENOMEM;
f3b54b9a SW	322	platform_set_drvdata(pdev, i2c_dev);
	323	i2c_dev->dev = &pdev->dev;
	324	init_completion(&i2c_dev->completion);
	325
	326	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ae50b1df JH	327	i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
	328	if (IS_ERR(i2c_dev->regs))
	329	return PTR_ERR(i2c_dev->regs);
f3b54b9a SW	330
	331	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
	332	if (IS_ERR(i2c_dev->clk)) {
85946abc EA	333	if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
85946abc EA	334	dev_err(&pdev->dev, "Could not get clock\n");
f3b54b9a SW	335	return PTR_ERR(i2c_dev->clk);
	336	}
	337
	338	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
9446f62e	339	&i2c_dev->bus_clk_rate);
f3b54b9a SW	340	if (ret < 0) {
	341	dev_warn(&pdev->dev,
	342	"Could not read clock-frequency property\n");
9446f62e	343	i2c_dev->bus_clk_rate = 100000;
f3b54b9a SW	344	}
f3b54b9a SW	345
f3b54b9a SW	346	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	347	if (!irq) {
	348	dev_err(&pdev->dev, "No IRQ resource\n");
	349	return -ENODEV;
	350	}
	351	i2c_dev->irq = irq->start;
	352
	353	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
	354	dev_name(&pdev->dev), i2c_dev);
	355	if (ret) {
	356	dev_err(&pdev->dev, "Could not request IRQ\n");
	357	return -ENODEV;
	358	}
	359
	360	adap = &i2c_dev->adapter;
	361	i2c_set_adapdata(adap, i2c_dev);
	362	adap->owner = THIS_MODULE;
37e4f91a	363	adap->class = I2C_CLASS_DEPRECATED;
f3b54b9a SW	364	strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
	365	adap->algo = &bcm2835_i2c_algo;
	366	adap->dev.parent = &pdev->dev;
07a27a00	367	adap->dev.of_node = pdev->dev.of_node;
4dbfb5f4	368	adap->quirks = &bcm2835_i2c_quirks;
f3b54b9a SW	369
	370	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
	371
	372	ret = i2c_add_adapter(adap);
	373	if (ret)
	374	free_irq(i2c_dev->irq, i2c_dev);
	375
	376	return ret;
	377	}
	378
	379	static int bcm2835_i2c_remove(struct platform_device *pdev)
	380	{
	381	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
	382
	383	free_irq(i2c_dev->irq, i2c_dev);
	384	i2c_del_adapter(&i2c_dev->adapter);
	385
	386	return 0;
	387	}
	388
	389	static const struct of_device_id bcm2835_i2c_of_match[] = {
	390	{ .compatible = "brcm,bcm2835-i2c" },
	391	{},
	392	};
	393	MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
	394
	395	static struct platform_driver bcm2835_i2c_driver = {
	396	.probe = bcm2835_i2c_probe,
	397	.remove = bcm2835_i2c_remove,
	398	.driver = {
	399	.name = "i2c-bcm2835",
f3b54b9a SW	400	.of_match_table = bcm2835_i2c_of_match,
	401	},
	402	};
	403	module_platform_driver(bcm2835_i2c_driver);
	404
	405	MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
	406	MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
	407	MODULE_LICENSE("GPL v2");
	408	MODULE_ALIAS("platform:i2c-bcm2835");