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Commit | Line | Data |
---|---|---|
d24ecfcc | 1 | /* |
bd584996 | 2 | * Blackfin On-Chip Two Wire Interface Driver |
d24ecfcc | 3 | * |
bd584996 | 4 | * Copyright 2005-2007 Analog Devices Inc. |
d24ecfcc | 5 | * |
bd584996 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
d24ecfcc | 7 | * |
bd584996 | 8 | * Licensed under the GPL-2 or later. |
d24ecfcc BW |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/i2c.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
6df263cf | 16 | #include <linux/io.h> |
d24ecfcc BW |
17 | #include <linux/mm.h> |
18 | #include <linux/timer.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
540ac555 | 23 | #include <linux/delay.h> |
d24ecfcc | 24 | |
d24ecfcc | 25 | #include <asm/irq.h> |
45126da2 | 26 | #include <asm/portmux.h> |
c9d87edb | 27 | #include <asm/bfin_twi.h> |
d24ecfcc | 28 | |
d24ecfcc | 29 | /* SMBus mode*/ |
4dd39bb1 SZ |
30 | #define TWI_I2C_MODE_STANDARD 1 |
31 | #define TWI_I2C_MODE_STANDARDSUB 2 | |
32 | #define TWI_I2C_MODE_COMBINED 3 | |
33 | #define TWI_I2C_MODE_REPEAT 4 | |
d24ecfcc | 34 | |
5481d075 SZ |
35 | static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, |
36 | unsigned short twi_int_status) | |
d24ecfcc | 37 | { |
aa3d0209 | 38 | unsigned short mast_stat = read_MASTER_STAT(iface); |
d24ecfcc BW |
39 | |
40 | if (twi_int_status & XMTSERV) { | |
8419c8de SZ |
41 | if (iface->writeNum <= 0) { |
42 | /* start receive immediately after complete sending in | |
43 | * combine mode. | |
44 | */ | |
45 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) | |
46 | write_MASTER_CTL(iface, | |
47 | read_MASTER_CTL(iface) | MDIR); | |
48 | else if (iface->manual_stop) | |
49 | write_MASTER_CTL(iface, | |
50 | read_MASTER_CTL(iface) | STOP); | |
51 | else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && | |
52 | iface->cur_msg + 1 < iface->msg_num) { | |
53 | if (iface->pmsg[iface->cur_msg + 1].flags & | |
54 | I2C_M_RD) | |
55 | write_MASTER_CTL(iface, | |
56 | read_MASTER_CTL(iface) | | |
57 | MDIR); | |
58 | else | |
59 | write_MASTER_CTL(iface, | |
60 | read_MASTER_CTL(iface) & | |
61 | ~MDIR); | |
62 | } | |
63 | } | |
d24ecfcc | 64 | /* Transmit next data */ |
8419c8de SZ |
65 | while (iface->writeNum > 0 && |
66 | (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) { | |
aa3d0209 | 67 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
d24ecfcc BW |
68 | iface->writeNum--; |
69 | } | |
d24ecfcc BW |
70 | } |
71 | if (twi_int_status & RCVSERV) { | |
8419c8de SZ |
72 | while (iface->readNum > 0 && |
73 | (read_FIFO_STAT(iface) & RCVSTAT)) { | |
d24ecfcc | 74 | /* Receive next data */ |
aa3d0209 | 75 | *(iface->transPtr) = read_RCV_DATA8(iface); |
d24ecfcc BW |
76 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { |
77 | /* Change combine mode into sub mode after | |
78 | * read first data. | |
79 | */ | |
80 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
81 | /* Get read number from first byte in block | |
82 | * combine mode. | |
83 | */ | |
84 | if (iface->readNum == 1 && iface->manual_stop) | |
85 | iface->readNum = *iface->transPtr + 1; | |
86 | } | |
87 | iface->transPtr++; | |
88 | iface->readNum--; | |
a20a64d2 SZ |
89 | } |
90 | ||
91 | if (iface->readNum == 0) { | |
92 | if (iface->manual_stop) { | |
93 | /* Temporary workaround to avoid possible bus stall - | |
94 | * Flush FIFO before issuing the STOP condition | |
95 | */ | |
96 | read_RCV_DATA16(iface); | |
94327d00 | 97 | write_MASTER_CTL(iface, |
a20a64d2 SZ |
98 | read_MASTER_CTL(iface) | STOP); |
99 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && | |
100 | iface->cur_msg + 1 < iface->msg_num) { | |
101 | if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) | |
102 | write_MASTER_CTL(iface, | |
28a377c7 | 103 | read_MASTER_CTL(iface) | MDIR); |
a20a64d2 SZ |
104 | else |
105 | write_MASTER_CTL(iface, | |
28a377c7 | 106 | read_MASTER_CTL(iface) & ~MDIR); |
a20a64d2 | 107 | } |
d24ecfcc | 108 | } |
d24ecfcc BW |
109 | } |
110 | if (twi_int_status & MERR) { | |
aa3d0209 BW |
111 | write_INT_MASK(iface, 0); |
112 | write_MASTER_STAT(iface, 0x3e); | |
113 | write_MASTER_CTL(iface, 0); | |
4dd39bb1 | 114 | iface->result = -EIO; |
5cfafc18 MH |
115 | |
116 | if (mast_stat & LOSTARB) | |
117 | dev_dbg(&iface->adap.dev, "Lost Arbitration\n"); | |
118 | if (mast_stat & ANAK) | |
119 | dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n"); | |
120 | if (mast_stat & DNAK) | |
121 | dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n"); | |
122 | if (mast_stat & BUFRDERR) | |
123 | dev_dbg(&iface->adap.dev, "Buffer Read Error\n"); | |
124 | if (mast_stat & BUFWRERR) | |
125 | dev_dbg(&iface->adap.dev, "Buffer Write Error\n"); | |
126 | ||
540ac555 MH |
127 | /* Faulty slave devices, may drive SDA low after a transfer |
128 | * finishes. To release the bus this code generates up to 9 | |
129 | * extra clocks until SDA is released. | |
130 | */ | |
131 | ||
132 | if (read_MASTER_STAT(iface) & SDASEN) { | |
133 | int cnt = 9; | |
134 | do { | |
135 | write_MASTER_CTL(iface, SCLOVR); | |
136 | udelay(6); | |
137 | write_MASTER_CTL(iface, 0); | |
138 | udelay(6); | |
139 | } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--); | |
140 | ||
141 | write_MASTER_CTL(iface, SDAOVR | SCLOVR); | |
142 | udelay(6); | |
143 | write_MASTER_CTL(iface, SDAOVR); | |
144 | udelay(6); | |
145 | write_MASTER_CTL(iface, 0); | |
146 | } | |
147 | ||
f0ac131a SZ |
148 | /* If it is a quick transfer, only address without data, |
149 | * not an err, return 1. | |
d24ecfcc | 150 | */ |
f0ac131a SZ |
151 | if (iface->cur_mode == TWI_I2C_MODE_STANDARD && |
152 | iface->transPtr == NULL && | |
153 | (twi_int_status & MCOMP) && (mast_stat & DNAK)) | |
154 | iface->result = 1; | |
155 | ||
d24ecfcc BW |
156 | complete(&iface->complete); |
157 | return; | |
158 | } | |
159 | if (twi_int_status & MCOMP) { | |
2ee74eb9 SZ |
160 | if (twi_int_status & (XMTSERV | RCVSERV) && |
161 | (read_MASTER_CTL(iface) & MEN) == 0 && | |
4a65163e SZ |
162 | (iface->cur_mode == TWI_I2C_MODE_REPEAT || |
163 | iface->cur_mode == TWI_I2C_MODE_COMBINED)) { | |
164 | iface->result = -1; | |
165 | write_INT_MASK(iface, 0); | |
166 | write_MASTER_CTL(iface, 0); | |
167 | } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
d24ecfcc BW |
168 | if (iface->readNum == 0) { |
169 | /* set the read number to 1 and ask for manual | |
170 | * stop in block combine mode | |
171 | */ | |
172 | iface->readNum = 1; | |
173 | iface->manual_stop = 1; | |
aa3d0209 BW |
174 | write_MASTER_CTL(iface, |
175 | read_MASTER_CTL(iface) | (0xff << 6)); | |
d24ecfcc BW |
176 | } else { |
177 | /* set the readd number in other | |
178 | * combine mode. | |
179 | */ | |
aa3d0209 BW |
180 | write_MASTER_CTL(iface, |
181 | (read_MASTER_CTL(iface) & | |
d24ecfcc | 182 | (~(0xff << 6))) | |
aa3d0209 | 183 | (iface->readNum << 6)); |
d24ecfcc BW |
184 | } |
185 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
186 | write_MASTER_CTL(iface, |
187 | read_MASTER_CTL(iface) & ~RSTART); | |
4dd39bb1 | 188 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
28a377c7 | 189 | iface->cur_msg + 1 < iface->msg_num) { |
4dd39bb1 SZ |
190 | iface->cur_msg++; |
191 | iface->transPtr = iface->pmsg[iface->cur_msg].buf; | |
192 | iface->writeNum = iface->readNum = | |
193 | iface->pmsg[iface->cur_msg].len; | |
194 | /* Set Transmit device address */ | |
aa3d0209 | 195 | write_MASTER_ADDR(iface, |
4dd39bb1 SZ |
196 | iface->pmsg[iface->cur_msg].addr); |
197 | if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) | |
198 | iface->read_write = I2C_SMBUS_READ; | |
199 | else { | |
200 | iface->read_write = I2C_SMBUS_WRITE; | |
201 | /* Transmit first data */ | |
202 | if (iface->writeNum > 0) { | |
aa3d0209 | 203 | write_XMT_DATA8(iface, |
4dd39bb1 SZ |
204 | *(iface->transPtr++)); |
205 | iface->writeNum--; | |
4dd39bb1 SZ |
206 | } |
207 | } | |
208 | ||
a20a64d2 SZ |
209 | if (iface->pmsg[iface->cur_msg].len <= 255) { |
210 | write_MASTER_CTL(iface, | |
57a8f32e SZ |
211 | (read_MASTER_CTL(iface) & |
212 | (~(0xff << 6))) | | |
a20a64d2 SZ |
213 | (iface->pmsg[iface->cur_msg].len << 6)); |
214 | iface->manual_stop = 0; | |
215 | } else { | |
57a8f32e SZ |
216 | write_MASTER_CTL(iface, |
217 | (read_MASTER_CTL(iface) | | |
218 | (0xff << 6))); | |
4dd39bb1 SZ |
219 | iface->manual_stop = 1; |
220 | } | |
28a377c7 SZ |
221 | /* remove restart bit before last message */ |
222 | if (iface->cur_msg + 1 == iface->msg_num) | |
223 | write_MASTER_CTL(iface, | |
224 | read_MASTER_CTL(iface) & ~RSTART); | |
d24ecfcc BW |
225 | } else { |
226 | iface->result = 1; | |
aa3d0209 BW |
227 | write_INT_MASK(iface, 0); |
228 | write_MASTER_CTL(iface, 0); | |
d24ecfcc | 229 | } |
a20a64d2 | 230 | complete(&iface->complete); |
d24ecfcc BW |
231 | } |
232 | } | |
233 | ||
234 | /* Interrupt handler */ | |
235 | static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) | |
236 | { | |
237 | struct bfin_twi_iface *iface = dev_id; | |
238 | unsigned long flags; | |
5481d075 | 239 | unsigned short twi_int_status; |
d24ecfcc BW |
240 | |
241 | spin_lock_irqsave(&iface->lock, flags); | |
5481d075 SZ |
242 | while (1) { |
243 | twi_int_status = read_INT_STAT(iface); | |
244 | if (!twi_int_status) | |
245 | break; | |
246 | /* Clear interrupt status */ | |
247 | write_INT_STAT(iface, twi_int_status); | |
248 | bfin_twi_handle_interrupt(iface, twi_int_status); | |
5481d075 | 249 | } |
d24ecfcc BW |
250 | spin_unlock_irqrestore(&iface->lock, flags); |
251 | return IRQ_HANDLED; | |
252 | } | |
253 | ||
d24ecfcc | 254 | /* |
dd7319a5 | 255 | * One i2c master transfer |
d24ecfcc | 256 | */ |
dd7319a5 | 257 | static int bfin_twi_do_master_xfer(struct i2c_adapter *adap, |
d24ecfcc BW |
258 | struct i2c_msg *msgs, int num) |
259 | { | |
260 | struct bfin_twi_iface *iface = adap->algo_data; | |
261 | struct i2c_msg *pmsg; | |
d24ecfcc BW |
262 | int rc = 0; |
263 | ||
aa3d0209 | 264 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
265 | return -ENXIO; |
266 | ||
a25733d6 SZ |
267 | if (read_MASTER_STAT(iface) & BUSBUSY) |
268 | return -EAGAIN; | |
d24ecfcc | 269 | |
4dd39bb1 SZ |
270 | iface->pmsg = msgs; |
271 | iface->msg_num = num; | |
272 | iface->cur_msg = 0; | |
d24ecfcc | 273 | |
4dd39bb1 SZ |
274 | pmsg = &msgs[0]; |
275 | if (pmsg->flags & I2C_M_TEN) { | |
276 | dev_err(&adap->dev, "10 bits addr not supported!\n"); | |
277 | return -EINVAL; | |
278 | } | |
d24ecfcc | 279 | |
28a377c7 SZ |
280 | if (iface->msg_num > 1) |
281 | iface->cur_mode = TWI_I2C_MODE_REPEAT; | |
4dd39bb1 SZ |
282 | iface->manual_stop = 0; |
283 | iface->transPtr = pmsg->buf; | |
284 | iface->writeNum = iface->readNum = pmsg->len; | |
285 | iface->result = 0; | |
afc13b76 | 286 | init_completion(&(iface->complete)); |
4dd39bb1 | 287 | /* Set Transmit device address */ |
aa3d0209 | 288 | write_MASTER_ADDR(iface, pmsg->addr); |
4dd39bb1 SZ |
289 | |
290 | /* FIFO Initiation. Data in FIFO should be | |
291 | * discarded before start a new operation. | |
292 | */ | |
aa3d0209 | 293 | write_FIFO_CTL(iface, 0x3); |
aa3d0209 | 294 | write_FIFO_CTL(iface, 0); |
4dd39bb1 SZ |
295 | |
296 | if (pmsg->flags & I2C_M_RD) | |
297 | iface->read_write = I2C_SMBUS_READ; | |
298 | else { | |
299 | iface->read_write = I2C_SMBUS_WRITE; | |
300 | /* Transmit first data */ | |
301 | if (iface->writeNum > 0) { | |
aa3d0209 | 302 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
4dd39bb1 | 303 | iface->writeNum--; |
d24ecfcc | 304 | } |
4dd39bb1 | 305 | } |
d24ecfcc | 306 | |
4dd39bb1 | 307 | /* clear int stat */ |
aa3d0209 | 308 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc | 309 | |
4dd39bb1 | 310 | /* Interrupt mask . Enable XMT, RCV interrupt */ |
aa3d0209 | 311 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); |
d24ecfcc | 312 | |
4dd39bb1 | 313 | if (pmsg->len <= 255) |
aa3d0209 | 314 | write_MASTER_CTL(iface, pmsg->len << 6); |
4dd39bb1 | 315 | else { |
aa3d0209 | 316 | write_MASTER_CTL(iface, 0xff << 6); |
4dd39bb1 SZ |
317 | iface->manual_stop = 1; |
318 | } | |
d24ecfcc | 319 | |
4dd39bb1 | 320 | /* Master enable */ |
aa3d0209 | 321 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
28a377c7 | 322 | (iface->msg_num > 1 ? RSTART : 0) | |
4dd39bb1 SZ |
323 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
324 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
4dd39bb1 | 325 | |
dd7319a5 SZ |
326 | while (!iface->result) { |
327 | if (!wait_for_completion_timeout(&iface->complete, | |
328 | adap->timeout)) { | |
329 | iface->result = -1; | |
330 | dev_err(&adap->dev, "master transfer timeout\n"); | |
331 | } | |
332 | } | |
d24ecfcc | 333 | |
dd7319a5 SZ |
334 | if (iface->result == 1) |
335 | rc = iface->cur_msg + 1; | |
4dd39bb1 | 336 | else |
dd7319a5 SZ |
337 | rc = iface->result; |
338 | ||
339 | return rc; | |
d24ecfcc BW |
340 | } |
341 | ||
342 | /* | |
dd7319a5 | 343 | * Generic i2c master transfer entrypoint |
d24ecfcc | 344 | */ |
dd7319a5 SZ |
345 | static int bfin_twi_master_xfer(struct i2c_adapter *adap, |
346 | struct i2c_msg *msgs, int num) | |
347 | { | |
be2f80f0 | 348 | return bfin_twi_do_master_xfer(adap, msgs, num); |
dd7319a5 SZ |
349 | } |
350 | ||
351 | /* | |
352 | * One I2C SMBus transfer | |
353 | */ | |
354 | int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
d24ecfcc BW |
355 | unsigned short flags, char read_write, |
356 | u8 command, int size, union i2c_smbus_data *data) | |
357 | { | |
358 | struct bfin_twi_iface *iface = adap->algo_data; | |
359 | int rc = 0; | |
360 | ||
aa3d0209 | 361 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
362 | return -ENXIO; |
363 | ||
a25733d6 SZ |
364 | if (read_MASTER_STAT(iface) & BUSBUSY) |
365 | return -EAGAIN; | |
d24ecfcc BW |
366 | |
367 | iface->writeNum = 0; | |
368 | iface->readNum = 0; | |
369 | ||
370 | /* Prepare datas & select mode */ | |
371 | switch (size) { | |
372 | case I2C_SMBUS_QUICK: | |
373 | iface->transPtr = NULL; | |
374 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
375 | break; | |
376 | case I2C_SMBUS_BYTE: | |
377 | if (data == NULL) | |
378 | iface->transPtr = NULL; | |
379 | else { | |
380 | if (read_write == I2C_SMBUS_READ) | |
381 | iface->readNum = 1; | |
382 | else | |
383 | iface->writeNum = 1; | |
384 | iface->transPtr = &data->byte; | |
385 | } | |
386 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
387 | break; | |
388 | case I2C_SMBUS_BYTE_DATA: | |
389 | if (read_write == I2C_SMBUS_READ) { | |
390 | iface->readNum = 1; | |
391 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
392 | } else { | |
393 | iface->writeNum = 1; | |
394 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
395 | } | |
396 | iface->transPtr = &data->byte; | |
397 | break; | |
398 | case I2C_SMBUS_WORD_DATA: | |
399 | if (read_write == I2C_SMBUS_READ) { | |
400 | iface->readNum = 2; | |
401 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
402 | } else { | |
403 | iface->writeNum = 2; | |
404 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
405 | } | |
406 | iface->transPtr = (u8 *)&data->word; | |
407 | break; | |
408 | case I2C_SMBUS_PROC_CALL: | |
409 | iface->writeNum = 2; | |
410 | iface->readNum = 2; | |
411 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
412 | iface->transPtr = (u8 *)&data->word; | |
413 | break; | |
414 | case I2C_SMBUS_BLOCK_DATA: | |
415 | if (read_write == I2C_SMBUS_READ) { | |
416 | iface->readNum = 0; | |
417 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
418 | } else { | |
419 | iface->writeNum = data->block[0] + 1; | |
420 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
421 | } | |
422 | iface->transPtr = data->block; | |
423 | break; | |
e0cd2dd5 MH |
424 | case I2C_SMBUS_I2C_BLOCK_DATA: |
425 | if (read_write == I2C_SMBUS_READ) { | |
426 | iface->readNum = data->block[0]; | |
427 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
428 | } else { | |
429 | iface->writeNum = data->block[0]; | |
430 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
431 | } | |
432 | iface->transPtr = (u8 *)&data->block[1]; | |
433 | break; | |
d24ecfcc BW |
434 | default: |
435 | return -1; | |
436 | } | |
437 | ||
438 | iface->result = 0; | |
439 | iface->manual_stop = 0; | |
440 | iface->read_write = read_write; | |
441 | iface->command = command; | |
afc13b76 | 442 | init_completion(&(iface->complete)); |
d24ecfcc BW |
443 | |
444 | /* FIFO Initiation. Data in FIFO should be discarded before | |
445 | * start a new operation. | |
446 | */ | |
aa3d0209 | 447 | write_FIFO_CTL(iface, 0x3); |
aa3d0209 | 448 | write_FIFO_CTL(iface, 0); |
d24ecfcc BW |
449 | |
450 | /* clear int stat */ | |
aa3d0209 | 451 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc BW |
452 | |
453 | /* Set Transmit device address */ | |
aa3d0209 | 454 | write_MASTER_ADDR(iface, addr); |
d24ecfcc | 455 | |
d24ecfcc BW |
456 | switch (iface->cur_mode) { |
457 | case TWI_I2C_MODE_STANDARDSUB: | |
aa3d0209 BW |
458 | write_XMT_DATA8(iface, iface->command); |
459 | write_INT_MASK(iface, MCOMP | MERR | | |
d24ecfcc BW |
460 | ((iface->read_write == I2C_SMBUS_READ) ? |
461 | RCVSERV : XMTSERV)); | |
d24ecfcc BW |
462 | |
463 | if (iface->writeNum + 1 <= 255) | |
aa3d0209 | 464 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 465 | else { |
aa3d0209 | 466 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc BW |
467 | iface->manual_stop = 1; |
468 | } | |
469 | /* Master enable */ | |
aa3d0209 | 470 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
471 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
472 | break; | |
473 | case TWI_I2C_MODE_COMBINED: | |
aa3d0209 BW |
474 | write_XMT_DATA8(iface, iface->command); |
475 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); | |
d24ecfcc BW |
476 | |
477 | if (iface->writeNum > 0) | |
aa3d0209 | 478 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 479 | else |
aa3d0209 | 480 | write_MASTER_CTL(iface, 0x1 << 6); |
d24ecfcc | 481 | /* Master enable */ |
28a377c7 | 482 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART | |
d24ecfcc BW |
483 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
484 | break; | |
485 | default: | |
aa3d0209 | 486 | write_MASTER_CTL(iface, 0); |
d24ecfcc BW |
487 | if (size != I2C_SMBUS_QUICK) { |
488 | /* Don't access xmit data register when this is a | |
489 | * read operation. | |
490 | */ | |
491 | if (iface->read_write != I2C_SMBUS_READ) { | |
492 | if (iface->writeNum > 0) { | |
aa3d0209 BW |
493 | write_XMT_DATA8(iface, |
494 | *(iface->transPtr++)); | |
d24ecfcc | 495 | if (iface->writeNum <= 255) |
aa3d0209 BW |
496 | write_MASTER_CTL(iface, |
497 | iface->writeNum << 6); | |
d24ecfcc | 498 | else { |
aa3d0209 BW |
499 | write_MASTER_CTL(iface, |
500 | 0xff << 6); | |
d24ecfcc BW |
501 | iface->manual_stop = 1; |
502 | } | |
503 | iface->writeNum--; | |
504 | } else { | |
aa3d0209 BW |
505 | write_XMT_DATA8(iface, iface->command); |
506 | write_MASTER_CTL(iface, 1 << 6); | |
d24ecfcc BW |
507 | } |
508 | } else { | |
509 | if (iface->readNum > 0 && iface->readNum <= 255) | |
aa3d0209 BW |
510 | write_MASTER_CTL(iface, |
511 | iface->readNum << 6); | |
d24ecfcc | 512 | else if (iface->readNum > 255) { |
aa3d0209 | 513 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc | 514 | iface->manual_stop = 1; |
dd7319a5 | 515 | } else |
d24ecfcc | 516 | break; |
d24ecfcc BW |
517 | } |
518 | } | |
aa3d0209 | 519 | write_INT_MASK(iface, MCOMP | MERR | |
d24ecfcc BW |
520 | ((iface->read_write == I2C_SMBUS_READ) ? |
521 | RCVSERV : XMTSERV)); | |
d24ecfcc BW |
522 | |
523 | /* Master enable */ | |
aa3d0209 | 524 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
525 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
526 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
527 | break; | |
528 | } | |
d24ecfcc | 529 | |
dd7319a5 SZ |
530 | while (!iface->result) { |
531 | if (!wait_for_completion_timeout(&iface->complete, | |
532 | adap->timeout)) { | |
533 | iface->result = -1; | |
534 | dev_err(&adap->dev, "smbus transfer timeout\n"); | |
535 | } | |
536 | } | |
d24ecfcc BW |
537 | |
538 | rc = (iface->result >= 0) ? 0 : -1; | |
539 | ||
d24ecfcc BW |
540 | return rc; |
541 | } | |
542 | ||
dd7319a5 SZ |
543 | /* |
544 | * Generic I2C SMBus transfer entrypoint | |
545 | */ | |
546 | int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
547 | unsigned short flags, char read_write, | |
548 | u8 command, int size, union i2c_smbus_data *data) | |
549 | { | |
be2f80f0 | 550 | return bfin_twi_do_smbus_xfer(adap, addr, flags, |
dd7319a5 | 551 | read_write, command, size, data); |
dd7319a5 SZ |
552 | } |
553 | ||
d24ecfcc BW |
554 | /* |
555 | * Return what the adapter supports | |
556 | */ | |
557 | static u32 bfin_twi_functionality(struct i2c_adapter *adap) | |
558 | { | |
559 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
560 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
561 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
e0cd2dd5 | 562 | I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; |
d24ecfcc BW |
563 | } |
564 | ||
92d9d0df | 565 | static const struct i2c_algorithm bfin_twi_algorithm = { |
d24ecfcc BW |
566 | .master_xfer = bfin_twi_master_xfer, |
567 | .smbus_xfer = bfin_twi_smbus_xfer, | |
568 | .functionality = bfin_twi_functionality, | |
569 | }; | |
570 | ||
2fb9ac0c | 571 | #ifdef CONFIG_PM_SLEEP |
85777ad2 | 572 | static int i2c_bfin_twi_suspend(struct device *dev) |
d24ecfcc | 573 | { |
85777ad2 | 574 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
958585f5 MH |
575 | |
576 | iface->saved_clkdiv = read_CLKDIV(iface); | |
577 | iface->saved_control = read_CONTROL(iface); | |
578 | ||
579 | free_irq(iface->irq, iface); | |
d24ecfcc BW |
580 | |
581 | /* Disable TWI */ | |
958585f5 | 582 | write_CONTROL(iface, iface->saved_control & ~TWI_ENA); |
d24ecfcc BW |
583 | |
584 | return 0; | |
585 | } | |
586 | ||
85777ad2 | 587 | static int i2c_bfin_twi_resume(struct device *dev) |
d24ecfcc | 588 | { |
85777ad2 | 589 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
d24ecfcc | 590 | |
958585f5 | 591 | int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
85777ad2 | 592 | 0, to_platform_device(dev)->name, iface); |
958585f5 | 593 | if (rc) { |
85777ad2 | 594 | dev_err(dev, "Can't get IRQ %d !\n", iface->irq); |
958585f5 MH |
595 | return -ENODEV; |
596 | } | |
597 | ||
598 | /* Resume TWI interface clock as specified */ | |
599 | write_CLKDIV(iface, iface->saved_clkdiv); | |
600 | ||
601 | /* Resume TWI */ | |
602 | write_CONTROL(iface, iface->saved_control); | |
d24ecfcc BW |
603 | |
604 | return 0; | |
605 | } | |
606 | ||
85777ad2 RW |
607 | static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm, |
608 | i2c_bfin_twi_suspend, i2c_bfin_twi_resume); | |
2fb9ac0c JH |
609 | #define I2C_BFIN_TWI_PM_OPS (&i2c_bfin_twi_pm) |
610 | #else | |
611 | #define I2C_BFIN_TWI_PM_OPS NULL | |
612 | #endif | |
85777ad2 | 613 | |
aa3d0209 | 614 | static int i2c_bfin_twi_probe(struct platform_device *pdev) |
d24ecfcc | 615 | { |
aa3d0209 | 616 | struct bfin_twi_iface *iface; |
d24ecfcc | 617 | struct i2c_adapter *p_adap; |
aa3d0209 | 618 | struct resource *res; |
d24ecfcc | 619 | int rc; |
9528d1c7 | 620 | unsigned int clkhilow; |
d24ecfcc | 621 | |
0709dc97 SZ |
622 | iface = devm_kzalloc(&pdev->dev, sizeof(struct bfin_twi_iface), |
623 | GFP_KERNEL); | |
aa3d0209 BW |
624 | if (!iface) { |
625 | dev_err(&pdev->dev, "Cannot allocate memory\n"); | |
0709dc97 | 626 | return -ENOMEM; |
aa3d0209 BW |
627 | } |
628 | ||
d24ecfcc | 629 | spin_lock_init(&(iface->lock)); |
aa3d0209 BW |
630 | |
631 | /* Find and map our resources */ | |
632 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0709dc97 SZ |
633 | iface->regs_base = devm_ioremap_resource(&pdev->dev, res); |
634 | if (IS_ERR(iface->regs_base)) { | |
aa3d0209 | 635 | dev_err(&pdev->dev, "Cannot map IO\n"); |
0709dc97 | 636 | return PTR_ERR(iface->regs_base); |
aa3d0209 BW |
637 | } |
638 | ||
639 | iface->irq = platform_get_irq(pdev, 0); | |
640 | if (iface->irq < 0) { | |
641 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
0709dc97 | 642 | return -ENOENT; |
aa3d0209 | 643 | } |
d24ecfcc | 644 | |
d24ecfcc | 645 | p_adap = &iface->adap; |
aa3d0209 BW |
646 | p_adap->nr = pdev->id; |
647 | strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); | |
d24ecfcc BW |
648 | p_adap->algo = &bfin_twi_algorithm; |
649 | p_adap->algo_data = iface; | |
aa5b775e | 650 | p_adap->class = I2C_CLASS_DEPRECATED; |
aa3d0209 | 651 | p_adap->dev.parent = &pdev->dev; |
dd7319a5 SZ |
652 | p_adap->timeout = 5 * HZ; |
653 | p_adap->retries = 3; | |
d24ecfcc | 654 | |
6d4028c6 | 655 | rc = peripheral_request_list( |
3c41aa71 | 656 | dev_get_platdata(&pdev->dev), |
6d4028c6 | 657 | "i2c-bfin-twi"); |
74d362e0 BW |
658 | if (rc) { |
659 | dev_err(&pdev->dev, "Can't setup pin mux!\n"); | |
0709dc97 | 660 | return -EBUSY; |
74d362e0 BW |
661 | } |
662 | ||
0709dc97 | 663 | rc = devm_request_irq(&pdev->dev, iface->irq, bfin_twi_interrupt_entry, |
4311051c | 664 | 0, pdev->name, iface); |
d24ecfcc | 665 | if (rc) { |
aa3d0209 BW |
666 | dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); |
667 | rc = -ENODEV; | |
0709dc97 | 668 | goto out_error; |
d24ecfcc BW |
669 | } |
670 | ||
671 | /* Set TWI internal clock as 10MHz */ | |
ac07fb4d | 672 | write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F); |
d24ecfcc | 673 | |
9528d1c7 MH |
674 | /* |
675 | * We will not end up with a CLKDIV=0 because no one will specify | |
ac07fb4d | 676 | * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250) |
9528d1c7 | 677 | */ |
ac07fb4d | 678 | clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2; |
9528d1c7 | 679 | |
d24ecfcc | 680 | /* Set Twi interface clock as specified */ |
9528d1c7 | 681 | write_CLKDIV(iface, (clkhilow << 8) | clkhilow); |
d24ecfcc BW |
682 | |
683 | /* Enable TWI */ | |
aa3d0209 | 684 | write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); |
d24ecfcc | 685 | |
991dee59 | 686 | rc = i2c_add_numbered_adapter(p_adap); |
ea734404 | 687 | if (rc < 0) |
0709dc97 | 688 | goto out_error; |
aa3d0209 BW |
689 | |
690 | platform_set_drvdata(pdev, iface); | |
d24ecfcc | 691 | |
e952849a | 692 | dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Controller, " |
fa6ad222 | 693 | "regs_base@%p\n", iface->regs_base); |
aa3d0209 BW |
694 | |
695 | return 0; | |
696 | ||
0709dc97 | 697 | out_error: |
3c41aa71 | 698 | peripheral_free_list(dev_get_platdata(&pdev->dev)); |
d24ecfcc BW |
699 | return rc; |
700 | } | |
701 | ||
702 | static int i2c_bfin_twi_remove(struct platform_device *pdev) | |
703 | { | |
704 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); | |
705 | ||
d24ecfcc | 706 | i2c_del_adapter(&(iface->adap)); |
3c41aa71 | 707 | peripheral_free_list(dev_get_platdata(&pdev->dev)); |
d24ecfcc BW |
708 | |
709 | return 0; | |
710 | } | |
711 | ||
712 | static struct platform_driver i2c_bfin_twi_driver = { | |
713 | .probe = i2c_bfin_twi_probe, | |
714 | .remove = i2c_bfin_twi_remove, | |
d24ecfcc BW |
715 | .driver = { |
716 | .name = "i2c-bfin-twi", | |
2fb9ac0c | 717 | .pm = I2C_BFIN_TWI_PM_OPS, |
d24ecfcc BW |
718 | }, |
719 | }; | |
720 | ||
721 | static int __init i2c_bfin_twi_init(void) | |
722 | { | |
d24ecfcc BW |
723 | return platform_driver_register(&i2c_bfin_twi_driver); |
724 | } | |
725 | ||
726 | static void __exit i2c_bfin_twi_exit(void) | |
727 | { | |
728 | platform_driver_unregister(&i2c_bfin_twi_driver); | |
729 | } | |
730 | ||
74f56c4a | 731 | subsys_initcall(i2c_bfin_twi_init); |
d24ecfcc | 732 | module_exit(i2c_bfin_twi_exit); |
fa6ad222 BW |
733 | |
734 | MODULE_AUTHOR("Bryan Wu, Sonic Zhang"); | |
e952849a | 735 | MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Controller Driver"); |
fa6ad222 | 736 | MODULE_LICENSE("GPL"); |
add8eda7 | 737 | MODULE_ALIAS("platform:i2c-bfin-twi"); |