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Commit | Line | Data |
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d24ecfcc | 1 | /* |
bd584996 | 2 | * Blackfin On-Chip Two Wire Interface Driver |
d24ecfcc | 3 | * |
bd584996 | 4 | * Copyright 2005-2007 Analog Devices Inc. |
d24ecfcc | 5 | * |
bd584996 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
d24ecfcc | 7 | * |
bd584996 | 8 | * Licensed under the GPL-2 or later. |
d24ecfcc BW |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/i2c.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/timer.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/completion.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/platform_device.h> | |
21 | ||
22 | #include <asm/blackfin.h> | |
74d362e0 | 23 | #include <asm/portmux.h> |
d24ecfcc BW |
24 | #include <asm/irq.h> |
25 | ||
26 | #define POLL_TIMEOUT (2 * HZ) | |
27 | ||
28 | /* SMBus mode*/ | |
4dd39bb1 SZ |
29 | #define TWI_I2C_MODE_STANDARD 1 |
30 | #define TWI_I2C_MODE_STANDARDSUB 2 | |
31 | #define TWI_I2C_MODE_COMBINED 3 | |
32 | #define TWI_I2C_MODE_REPEAT 4 | |
d24ecfcc BW |
33 | |
34 | struct bfin_twi_iface { | |
d24ecfcc BW |
35 | int irq; |
36 | spinlock_t lock; | |
37 | char read_write; | |
38 | u8 command; | |
39 | u8 *transPtr; | |
40 | int readNum; | |
41 | int writeNum; | |
42 | int cur_mode; | |
43 | int manual_stop; | |
44 | int result; | |
45 | int timeout_count; | |
46 | struct timer_list timeout_timer; | |
47 | struct i2c_adapter adap; | |
48 | struct completion complete; | |
4dd39bb1 SZ |
49 | struct i2c_msg *pmsg; |
50 | int msg_num; | |
51 | int cur_msg; | |
958585f5 MH |
52 | u16 saved_clkdiv; |
53 | u16 saved_control; | |
aa3d0209 | 54 | void __iomem *regs_base; |
d24ecfcc BW |
55 | }; |
56 | ||
aa3d0209 BW |
57 | |
58 | #define DEFINE_TWI_REG(reg, off) \ | |
59 | static inline u16 read_##reg(struct bfin_twi_iface *iface) \ | |
60 | { return bfin_read16(iface->regs_base + (off)); } \ | |
61 | static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \ | |
62 | { bfin_write16(iface->regs_base + (off), v); } | |
63 | ||
64 | DEFINE_TWI_REG(CLKDIV, 0x00) | |
65 | DEFINE_TWI_REG(CONTROL, 0x04) | |
66 | DEFINE_TWI_REG(SLAVE_CTL, 0x08) | |
67 | DEFINE_TWI_REG(SLAVE_STAT, 0x0C) | |
68 | DEFINE_TWI_REG(SLAVE_ADDR, 0x10) | |
69 | DEFINE_TWI_REG(MASTER_CTL, 0x14) | |
70 | DEFINE_TWI_REG(MASTER_STAT, 0x18) | |
71 | DEFINE_TWI_REG(MASTER_ADDR, 0x1C) | |
72 | DEFINE_TWI_REG(INT_STAT, 0x20) | |
73 | DEFINE_TWI_REG(INT_MASK, 0x24) | |
74 | DEFINE_TWI_REG(FIFO_CTL, 0x28) | |
75 | DEFINE_TWI_REG(FIFO_STAT, 0x2C) | |
76 | DEFINE_TWI_REG(XMT_DATA8, 0x80) | |
77 | DEFINE_TWI_REG(XMT_DATA16, 0x84) | |
78 | DEFINE_TWI_REG(RCV_DATA8, 0x88) | |
79 | DEFINE_TWI_REG(RCV_DATA16, 0x8C) | |
d24ecfcc | 80 | |
74d362e0 BW |
81 | static const u16 pin_req[2][3] = { |
82 | {P_TWI0_SCL, P_TWI0_SDA, 0}, | |
83 | {P_TWI1_SCL, P_TWI1_SDA, 0}, | |
84 | }; | |
85 | ||
d24ecfcc BW |
86 | static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) |
87 | { | |
aa3d0209 BW |
88 | unsigned short twi_int_status = read_INT_STAT(iface); |
89 | unsigned short mast_stat = read_MASTER_STAT(iface); | |
d24ecfcc BW |
90 | |
91 | if (twi_int_status & XMTSERV) { | |
92 | /* Transmit next data */ | |
93 | if (iface->writeNum > 0) { | |
aa3d0209 | 94 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
d24ecfcc BW |
95 | iface->writeNum--; |
96 | } | |
97 | /* start receive immediately after complete sending in | |
98 | * combine mode. | |
99 | */ | |
4dd39bb1 | 100 | else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) |
aa3d0209 BW |
101 | write_MASTER_CTL(iface, |
102 | read_MASTER_CTL(iface) | MDIR | RSTART); | |
4dd39bb1 | 103 | else if (iface->manual_stop) |
aa3d0209 BW |
104 | write_MASTER_CTL(iface, |
105 | read_MASTER_CTL(iface) | STOP); | |
4dd39bb1 SZ |
106 | else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
107 | iface->cur_msg+1 < iface->msg_num) | |
aa3d0209 BW |
108 | write_MASTER_CTL(iface, |
109 | read_MASTER_CTL(iface) | RSTART); | |
d24ecfcc BW |
110 | SSYNC(); |
111 | /* Clear status */ | |
aa3d0209 | 112 | write_INT_STAT(iface, XMTSERV); |
d24ecfcc BW |
113 | SSYNC(); |
114 | } | |
115 | if (twi_int_status & RCVSERV) { | |
116 | if (iface->readNum > 0) { | |
117 | /* Receive next data */ | |
aa3d0209 | 118 | *(iface->transPtr) = read_RCV_DATA8(iface); |
d24ecfcc BW |
119 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { |
120 | /* Change combine mode into sub mode after | |
121 | * read first data. | |
122 | */ | |
123 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
124 | /* Get read number from first byte in block | |
125 | * combine mode. | |
126 | */ | |
127 | if (iface->readNum == 1 && iface->manual_stop) | |
128 | iface->readNum = *iface->transPtr + 1; | |
129 | } | |
130 | iface->transPtr++; | |
131 | iface->readNum--; | |
132 | } else if (iface->manual_stop) { | |
aa3d0209 BW |
133 | write_MASTER_CTL(iface, |
134 | read_MASTER_CTL(iface) | STOP); | |
d24ecfcc | 135 | SSYNC(); |
4dd39bb1 SZ |
136 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
137 | iface->cur_msg+1 < iface->msg_num) { | |
aa3d0209 BW |
138 | write_MASTER_CTL(iface, |
139 | read_MASTER_CTL(iface) | RSTART); | |
4dd39bb1 | 140 | SSYNC(); |
d24ecfcc BW |
141 | } |
142 | /* Clear interrupt source */ | |
aa3d0209 | 143 | write_INT_STAT(iface, RCVSERV); |
d24ecfcc BW |
144 | SSYNC(); |
145 | } | |
146 | if (twi_int_status & MERR) { | |
aa3d0209 BW |
147 | write_INT_STAT(iface, MERR); |
148 | write_INT_MASK(iface, 0); | |
149 | write_MASTER_STAT(iface, 0x3e); | |
150 | write_MASTER_CTL(iface, 0); | |
d24ecfcc | 151 | SSYNC(); |
4dd39bb1 | 152 | iface->result = -EIO; |
d24ecfcc BW |
153 | /* if both err and complete int stats are set, return proper |
154 | * results. | |
155 | */ | |
156 | if (twi_int_status & MCOMP) { | |
aa3d0209 BW |
157 | write_INT_STAT(iface, MCOMP); |
158 | write_INT_MASK(iface, 0); | |
159 | write_MASTER_CTL(iface, 0); | |
d24ecfcc BW |
160 | SSYNC(); |
161 | /* If it is a quick transfer, only address bug no data, | |
162 | * not an err, return 1. | |
163 | */ | |
164 | if (iface->writeNum == 0 && (mast_stat & BUFRDERR)) | |
165 | iface->result = 1; | |
166 | /* If address not acknowledged return -1, | |
167 | * else return 0. | |
168 | */ | |
169 | else if (!(mast_stat & ANAK)) | |
170 | iface->result = 0; | |
171 | } | |
172 | complete(&iface->complete); | |
173 | return; | |
174 | } | |
175 | if (twi_int_status & MCOMP) { | |
aa3d0209 | 176 | write_INT_STAT(iface, MCOMP); |
d24ecfcc BW |
177 | SSYNC(); |
178 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
179 | if (iface->readNum == 0) { | |
180 | /* set the read number to 1 and ask for manual | |
181 | * stop in block combine mode | |
182 | */ | |
183 | iface->readNum = 1; | |
184 | iface->manual_stop = 1; | |
aa3d0209 BW |
185 | write_MASTER_CTL(iface, |
186 | read_MASTER_CTL(iface) | (0xff << 6)); | |
d24ecfcc BW |
187 | } else { |
188 | /* set the readd number in other | |
189 | * combine mode. | |
190 | */ | |
aa3d0209 BW |
191 | write_MASTER_CTL(iface, |
192 | (read_MASTER_CTL(iface) & | |
d24ecfcc | 193 | (~(0xff << 6))) | |
aa3d0209 | 194 | (iface->readNum << 6)); |
d24ecfcc BW |
195 | } |
196 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
197 | write_MASTER_CTL(iface, |
198 | read_MASTER_CTL(iface) & ~RSTART); | |
d24ecfcc | 199 | SSYNC(); |
4dd39bb1 SZ |
200 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
201 | iface->cur_msg+1 < iface->msg_num) { | |
202 | iface->cur_msg++; | |
203 | iface->transPtr = iface->pmsg[iface->cur_msg].buf; | |
204 | iface->writeNum = iface->readNum = | |
205 | iface->pmsg[iface->cur_msg].len; | |
206 | /* Set Transmit device address */ | |
aa3d0209 | 207 | write_MASTER_ADDR(iface, |
4dd39bb1 SZ |
208 | iface->pmsg[iface->cur_msg].addr); |
209 | if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) | |
210 | iface->read_write = I2C_SMBUS_READ; | |
211 | else { | |
212 | iface->read_write = I2C_SMBUS_WRITE; | |
213 | /* Transmit first data */ | |
214 | if (iface->writeNum > 0) { | |
aa3d0209 | 215 | write_XMT_DATA8(iface, |
4dd39bb1 SZ |
216 | *(iface->transPtr++)); |
217 | iface->writeNum--; | |
218 | SSYNC(); | |
219 | } | |
220 | } | |
221 | ||
222 | if (iface->pmsg[iface->cur_msg].len <= 255) | |
57a8f32e SZ |
223 | write_MASTER_CTL(iface, |
224 | (read_MASTER_CTL(iface) & | |
225 | (~(0xff << 6))) | | |
226 | (iface->pmsg[iface->cur_msg].len << 6)); | |
4dd39bb1 | 227 | else { |
57a8f32e SZ |
228 | write_MASTER_CTL(iface, |
229 | (read_MASTER_CTL(iface) | | |
230 | (0xff << 6))); | |
4dd39bb1 SZ |
231 | iface->manual_stop = 1; |
232 | } | |
233 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
234 | write_MASTER_CTL(iface, |
235 | read_MASTER_CTL(iface) & ~RSTART); | |
4dd39bb1 | 236 | SSYNC(); |
d24ecfcc BW |
237 | } else { |
238 | iface->result = 1; | |
aa3d0209 BW |
239 | write_INT_MASK(iface, 0); |
240 | write_MASTER_CTL(iface, 0); | |
d24ecfcc BW |
241 | SSYNC(); |
242 | complete(&iface->complete); | |
243 | } | |
244 | } | |
245 | } | |
246 | ||
247 | /* Interrupt handler */ | |
248 | static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) | |
249 | { | |
250 | struct bfin_twi_iface *iface = dev_id; | |
251 | unsigned long flags; | |
252 | ||
253 | spin_lock_irqsave(&iface->lock, flags); | |
254 | del_timer(&iface->timeout_timer); | |
255 | bfin_twi_handle_interrupt(iface); | |
256 | spin_unlock_irqrestore(&iface->lock, flags); | |
257 | return IRQ_HANDLED; | |
258 | } | |
259 | ||
260 | static void bfin_twi_timeout(unsigned long data) | |
261 | { | |
262 | struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data; | |
263 | unsigned long flags; | |
264 | ||
265 | spin_lock_irqsave(&iface->lock, flags); | |
266 | bfin_twi_handle_interrupt(iface); | |
267 | if (iface->result == 0) { | |
268 | iface->timeout_count--; | |
269 | if (iface->timeout_count > 0) { | |
270 | iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; | |
271 | add_timer(&iface->timeout_timer); | |
272 | } else { | |
273 | iface->result = -1; | |
274 | complete(&iface->complete); | |
275 | } | |
276 | } | |
277 | spin_unlock_irqrestore(&iface->lock, flags); | |
278 | } | |
279 | ||
280 | /* | |
281 | * Generic i2c master transfer entrypoint | |
282 | */ | |
283 | static int bfin_twi_master_xfer(struct i2c_adapter *adap, | |
284 | struct i2c_msg *msgs, int num) | |
285 | { | |
286 | struct bfin_twi_iface *iface = adap->algo_data; | |
287 | struct i2c_msg *pmsg; | |
d24ecfcc BW |
288 | int rc = 0; |
289 | ||
aa3d0209 | 290 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
291 | return -ENXIO; |
292 | ||
aa3d0209 | 293 | while (read_MASTER_STAT(iface) & BUSBUSY) |
d24ecfcc | 294 | yield(); |
d24ecfcc | 295 | |
4dd39bb1 SZ |
296 | iface->pmsg = msgs; |
297 | iface->msg_num = num; | |
298 | iface->cur_msg = 0; | |
d24ecfcc | 299 | |
4dd39bb1 SZ |
300 | pmsg = &msgs[0]; |
301 | if (pmsg->flags & I2C_M_TEN) { | |
302 | dev_err(&adap->dev, "10 bits addr not supported!\n"); | |
303 | return -EINVAL; | |
304 | } | |
d24ecfcc | 305 | |
4dd39bb1 SZ |
306 | iface->cur_mode = TWI_I2C_MODE_REPEAT; |
307 | iface->manual_stop = 0; | |
308 | iface->transPtr = pmsg->buf; | |
309 | iface->writeNum = iface->readNum = pmsg->len; | |
310 | iface->result = 0; | |
311 | iface->timeout_count = 10; | |
afc13b76 | 312 | init_completion(&(iface->complete)); |
4dd39bb1 | 313 | /* Set Transmit device address */ |
aa3d0209 | 314 | write_MASTER_ADDR(iface, pmsg->addr); |
4dd39bb1 SZ |
315 | |
316 | /* FIFO Initiation. Data in FIFO should be | |
317 | * discarded before start a new operation. | |
318 | */ | |
aa3d0209 | 319 | write_FIFO_CTL(iface, 0x3); |
4dd39bb1 | 320 | SSYNC(); |
aa3d0209 | 321 | write_FIFO_CTL(iface, 0); |
4dd39bb1 SZ |
322 | SSYNC(); |
323 | ||
324 | if (pmsg->flags & I2C_M_RD) | |
325 | iface->read_write = I2C_SMBUS_READ; | |
326 | else { | |
327 | iface->read_write = I2C_SMBUS_WRITE; | |
328 | /* Transmit first data */ | |
329 | if (iface->writeNum > 0) { | |
aa3d0209 | 330 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
4dd39bb1 SZ |
331 | iface->writeNum--; |
332 | SSYNC(); | |
d24ecfcc | 333 | } |
4dd39bb1 | 334 | } |
d24ecfcc | 335 | |
4dd39bb1 | 336 | /* clear int stat */ |
aa3d0209 | 337 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc | 338 | |
4dd39bb1 | 339 | /* Interrupt mask . Enable XMT, RCV interrupt */ |
aa3d0209 | 340 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); |
4dd39bb1 | 341 | SSYNC(); |
d24ecfcc | 342 | |
4dd39bb1 | 343 | if (pmsg->len <= 255) |
aa3d0209 | 344 | write_MASTER_CTL(iface, pmsg->len << 6); |
4dd39bb1 | 345 | else { |
aa3d0209 | 346 | write_MASTER_CTL(iface, 0xff << 6); |
4dd39bb1 SZ |
347 | iface->manual_stop = 1; |
348 | } | |
d24ecfcc | 349 | |
4dd39bb1 SZ |
350 | iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; |
351 | add_timer(&iface->timeout_timer); | |
d24ecfcc | 352 | |
4dd39bb1 | 353 | /* Master enable */ |
aa3d0209 | 354 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
4dd39bb1 SZ |
355 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
356 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
357 | SSYNC(); | |
358 | ||
359 | wait_for_completion(&iface->complete); | |
360 | ||
361 | rc = iface->result; | |
d24ecfcc | 362 | |
4dd39bb1 SZ |
363 | if (rc == 1) |
364 | return num; | |
365 | else | |
366 | return rc; | |
d24ecfcc BW |
367 | } |
368 | ||
369 | /* | |
370 | * SMBus type transfer entrypoint | |
371 | */ | |
372 | ||
373 | int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
374 | unsigned short flags, char read_write, | |
375 | u8 command, int size, union i2c_smbus_data *data) | |
376 | { | |
377 | struct bfin_twi_iface *iface = adap->algo_data; | |
378 | int rc = 0; | |
379 | ||
aa3d0209 | 380 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
381 | return -ENXIO; |
382 | ||
aa3d0209 | 383 | while (read_MASTER_STAT(iface) & BUSBUSY) |
d24ecfcc | 384 | yield(); |
d24ecfcc BW |
385 | |
386 | iface->writeNum = 0; | |
387 | iface->readNum = 0; | |
388 | ||
389 | /* Prepare datas & select mode */ | |
390 | switch (size) { | |
391 | case I2C_SMBUS_QUICK: | |
392 | iface->transPtr = NULL; | |
393 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
394 | break; | |
395 | case I2C_SMBUS_BYTE: | |
396 | if (data == NULL) | |
397 | iface->transPtr = NULL; | |
398 | else { | |
399 | if (read_write == I2C_SMBUS_READ) | |
400 | iface->readNum = 1; | |
401 | else | |
402 | iface->writeNum = 1; | |
403 | iface->transPtr = &data->byte; | |
404 | } | |
405 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
406 | break; | |
407 | case I2C_SMBUS_BYTE_DATA: | |
408 | if (read_write == I2C_SMBUS_READ) { | |
409 | iface->readNum = 1; | |
410 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
411 | } else { | |
412 | iface->writeNum = 1; | |
413 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
414 | } | |
415 | iface->transPtr = &data->byte; | |
416 | break; | |
417 | case I2C_SMBUS_WORD_DATA: | |
418 | if (read_write == I2C_SMBUS_READ) { | |
419 | iface->readNum = 2; | |
420 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
421 | } else { | |
422 | iface->writeNum = 2; | |
423 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
424 | } | |
425 | iface->transPtr = (u8 *)&data->word; | |
426 | break; | |
427 | case I2C_SMBUS_PROC_CALL: | |
428 | iface->writeNum = 2; | |
429 | iface->readNum = 2; | |
430 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
431 | iface->transPtr = (u8 *)&data->word; | |
432 | break; | |
433 | case I2C_SMBUS_BLOCK_DATA: | |
434 | if (read_write == I2C_SMBUS_READ) { | |
435 | iface->readNum = 0; | |
436 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
437 | } else { | |
438 | iface->writeNum = data->block[0] + 1; | |
439 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
440 | } | |
441 | iface->transPtr = data->block; | |
442 | break; | |
443 | default: | |
444 | return -1; | |
445 | } | |
446 | ||
447 | iface->result = 0; | |
448 | iface->manual_stop = 0; | |
449 | iface->read_write = read_write; | |
450 | iface->command = command; | |
451 | iface->timeout_count = 10; | |
afc13b76 | 452 | init_completion(&(iface->complete)); |
d24ecfcc BW |
453 | |
454 | /* FIFO Initiation. Data in FIFO should be discarded before | |
455 | * start a new operation. | |
456 | */ | |
aa3d0209 | 457 | write_FIFO_CTL(iface, 0x3); |
d24ecfcc | 458 | SSYNC(); |
aa3d0209 | 459 | write_FIFO_CTL(iface, 0); |
d24ecfcc BW |
460 | |
461 | /* clear int stat */ | |
aa3d0209 | 462 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc BW |
463 | |
464 | /* Set Transmit device address */ | |
aa3d0209 | 465 | write_MASTER_ADDR(iface, addr); |
d24ecfcc BW |
466 | SSYNC(); |
467 | ||
468 | iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; | |
469 | add_timer(&iface->timeout_timer); | |
470 | ||
471 | switch (iface->cur_mode) { | |
472 | case TWI_I2C_MODE_STANDARDSUB: | |
aa3d0209 BW |
473 | write_XMT_DATA8(iface, iface->command); |
474 | write_INT_MASK(iface, MCOMP | MERR | | |
d24ecfcc BW |
475 | ((iface->read_write == I2C_SMBUS_READ) ? |
476 | RCVSERV : XMTSERV)); | |
477 | SSYNC(); | |
478 | ||
479 | if (iface->writeNum + 1 <= 255) | |
aa3d0209 | 480 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 481 | else { |
aa3d0209 | 482 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc BW |
483 | iface->manual_stop = 1; |
484 | } | |
485 | /* Master enable */ | |
aa3d0209 | 486 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
487 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
488 | break; | |
489 | case TWI_I2C_MODE_COMBINED: | |
aa3d0209 BW |
490 | write_XMT_DATA8(iface, iface->command); |
491 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); | |
d24ecfcc BW |
492 | SSYNC(); |
493 | ||
494 | if (iface->writeNum > 0) | |
aa3d0209 | 495 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 496 | else |
aa3d0209 | 497 | write_MASTER_CTL(iface, 0x1 << 6); |
d24ecfcc | 498 | /* Master enable */ |
aa3d0209 | 499 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
500 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
501 | break; | |
502 | default: | |
aa3d0209 | 503 | write_MASTER_CTL(iface, 0); |
d24ecfcc BW |
504 | if (size != I2C_SMBUS_QUICK) { |
505 | /* Don't access xmit data register when this is a | |
506 | * read operation. | |
507 | */ | |
508 | if (iface->read_write != I2C_SMBUS_READ) { | |
509 | if (iface->writeNum > 0) { | |
aa3d0209 BW |
510 | write_XMT_DATA8(iface, |
511 | *(iface->transPtr++)); | |
d24ecfcc | 512 | if (iface->writeNum <= 255) |
aa3d0209 BW |
513 | write_MASTER_CTL(iface, |
514 | iface->writeNum << 6); | |
d24ecfcc | 515 | else { |
aa3d0209 BW |
516 | write_MASTER_CTL(iface, |
517 | 0xff << 6); | |
d24ecfcc BW |
518 | iface->manual_stop = 1; |
519 | } | |
520 | iface->writeNum--; | |
521 | } else { | |
aa3d0209 BW |
522 | write_XMT_DATA8(iface, iface->command); |
523 | write_MASTER_CTL(iface, 1 << 6); | |
d24ecfcc BW |
524 | } |
525 | } else { | |
526 | if (iface->readNum > 0 && iface->readNum <= 255) | |
aa3d0209 BW |
527 | write_MASTER_CTL(iface, |
528 | iface->readNum << 6); | |
d24ecfcc | 529 | else if (iface->readNum > 255) { |
aa3d0209 | 530 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc BW |
531 | iface->manual_stop = 1; |
532 | } else { | |
533 | del_timer(&iface->timeout_timer); | |
534 | break; | |
535 | } | |
536 | } | |
537 | } | |
aa3d0209 | 538 | write_INT_MASK(iface, MCOMP | MERR | |
d24ecfcc BW |
539 | ((iface->read_write == I2C_SMBUS_READ) ? |
540 | RCVSERV : XMTSERV)); | |
541 | SSYNC(); | |
542 | ||
543 | /* Master enable */ | |
aa3d0209 | 544 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
545 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
546 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
547 | break; | |
548 | } | |
549 | SSYNC(); | |
550 | ||
551 | wait_for_completion(&iface->complete); | |
552 | ||
553 | rc = (iface->result >= 0) ? 0 : -1; | |
554 | ||
d24ecfcc BW |
555 | return rc; |
556 | } | |
557 | ||
558 | /* | |
559 | * Return what the adapter supports | |
560 | */ | |
561 | static u32 bfin_twi_functionality(struct i2c_adapter *adap) | |
562 | { | |
563 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
564 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
565 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
566 | I2C_FUNC_I2C; | |
567 | } | |
568 | ||
d24ecfcc BW |
569 | static struct i2c_algorithm bfin_twi_algorithm = { |
570 | .master_xfer = bfin_twi_master_xfer, | |
571 | .smbus_xfer = bfin_twi_smbus_xfer, | |
572 | .functionality = bfin_twi_functionality, | |
573 | }; | |
574 | ||
958585f5 | 575 | static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state) |
d24ecfcc | 576 | { |
958585f5 MH |
577 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); |
578 | ||
579 | iface->saved_clkdiv = read_CLKDIV(iface); | |
580 | iface->saved_control = read_CONTROL(iface); | |
581 | ||
582 | free_irq(iface->irq, iface); | |
d24ecfcc BW |
583 | |
584 | /* Disable TWI */ | |
958585f5 | 585 | write_CONTROL(iface, iface->saved_control & ~TWI_ENA); |
d24ecfcc BW |
586 | |
587 | return 0; | |
588 | } | |
589 | ||
958585f5 | 590 | static int i2c_bfin_twi_resume(struct platform_device *pdev) |
d24ecfcc | 591 | { |
958585f5 | 592 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); |
d24ecfcc | 593 | |
958585f5 MH |
594 | int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
595 | IRQF_DISABLED, pdev->name, iface); | |
596 | if (rc) { | |
597 | dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); | |
598 | return -ENODEV; | |
599 | } | |
600 | ||
601 | /* Resume TWI interface clock as specified */ | |
602 | write_CLKDIV(iface, iface->saved_clkdiv); | |
603 | ||
604 | /* Resume TWI */ | |
605 | write_CONTROL(iface, iface->saved_control); | |
d24ecfcc BW |
606 | |
607 | return 0; | |
608 | } | |
609 | ||
aa3d0209 | 610 | static int i2c_bfin_twi_probe(struct platform_device *pdev) |
d24ecfcc | 611 | { |
aa3d0209 | 612 | struct bfin_twi_iface *iface; |
d24ecfcc | 613 | struct i2c_adapter *p_adap; |
aa3d0209 | 614 | struct resource *res; |
d24ecfcc | 615 | int rc; |
9528d1c7 | 616 | unsigned int clkhilow; |
d24ecfcc | 617 | |
aa3d0209 BW |
618 | iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL); |
619 | if (!iface) { | |
620 | dev_err(&pdev->dev, "Cannot allocate memory\n"); | |
621 | rc = -ENOMEM; | |
622 | goto out_error_nomem; | |
623 | } | |
624 | ||
d24ecfcc | 625 | spin_lock_init(&(iface->lock)); |
aa3d0209 BW |
626 | |
627 | /* Find and map our resources */ | |
628 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
629 | if (res == NULL) { | |
630 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
631 | rc = -ENOENT; | |
632 | goto out_error_get_res; | |
633 | } | |
634 | ||
635 | iface->regs_base = ioremap(res->start, res->end - res->start + 1); | |
636 | if (iface->regs_base == NULL) { | |
637 | dev_err(&pdev->dev, "Cannot map IO\n"); | |
638 | rc = -ENXIO; | |
639 | goto out_error_ioremap; | |
640 | } | |
641 | ||
642 | iface->irq = platform_get_irq(pdev, 0); | |
643 | if (iface->irq < 0) { | |
644 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
645 | rc = -ENOENT; | |
646 | goto out_error_no_irq; | |
647 | } | |
d24ecfcc BW |
648 | |
649 | init_timer(&(iface->timeout_timer)); | |
650 | iface->timeout_timer.function = bfin_twi_timeout; | |
651 | iface->timeout_timer.data = (unsigned long)iface; | |
652 | ||
653 | p_adap = &iface->adap; | |
aa3d0209 BW |
654 | p_adap->nr = pdev->id; |
655 | strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); | |
d24ecfcc BW |
656 | p_adap->algo = &bfin_twi_algorithm; |
657 | p_adap->algo_data = iface; | |
e1995f65 | 658 | p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
aa3d0209 | 659 | p_adap->dev.parent = &pdev->dev; |
d24ecfcc | 660 | |
74d362e0 BW |
661 | rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi"); |
662 | if (rc) { | |
663 | dev_err(&pdev->dev, "Can't setup pin mux!\n"); | |
664 | goto out_error_pin_mux; | |
665 | } | |
666 | ||
d24ecfcc | 667 | rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
aa3d0209 | 668 | IRQF_DISABLED, pdev->name, iface); |
d24ecfcc | 669 | if (rc) { |
aa3d0209 BW |
670 | dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); |
671 | rc = -ENODEV; | |
672 | goto out_error_req_irq; | |
d24ecfcc BW |
673 | } |
674 | ||
675 | /* Set TWI internal clock as 10MHz */ | |
aa3d0209 | 676 | write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); |
d24ecfcc | 677 | |
9528d1c7 MH |
678 | /* |
679 | * We will not end up with a CLKDIV=0 because no one will specify | |
680 | * 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100) | |
681 | */ | |
682 | clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ; | |
683 | ||
d24ecfcc | 684 | /* Set Twi interface clock as specified */ |
9528d1c7 | 685 | write_CLKDIV(iface, (clkhilow << 8) | clkhilow); |
d24ecfcc BW |
686 | |
687 | /* Enable TWI */ | |
aa3d0209 | 688 | write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); |
d24ecfcc BW |
689 | SSYNC(); |
690 | ||
991dee59 | 691 | rc = i2c_add_numbered_adapter(p_adap); |
aa3d0209 BW |
692 | if (rc < 0) { |
693 | dev_err(&pdev->dev, "Can't add i2c adapter!\n"); | |
694 | goto out_error_add_adapter; | |
695 | } | |
696 | ||
697 | platform_set_drvdata(pdev, iface); | |
d24ecfcc | 698 | |
fa6ad222 BW |
699 | dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, " |
700 | "regs_base@%p\n", iface->regs_base); | |
aa3d0209 BW |
701 | |
702 | return 0; | |
703 | ||
704 | out_error_add_adapter: | |
705 | free_irq(iface->irq, iface); | |
706 | out_error_req_irq: | |
707 | out_error_no_irq: | |
74d362e0 BW |
708 | peripheral_free_list(pin_req[pdev->id]); |
709 | out_error_pin_mux: | |
aa3d0209 BW |
710 | iounmap(iface->regs_base); |
711 | out_error_ioremap: | |
712 | out_error_get_res: | |
713 | kfree(iface); | |
714 | out_error_nomem: | |
d24ecfcc BW |
715 | return rc; |
716 | } | |
717 | ||
718 | static int i2c_bfin_twi_remove(struct platform_device *pdev) | |
719 | { | |
720 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); | |
721 | ||
722 | platform_set_drvdata(pdev, NULL); | |
723 | ||
724 | i2c_del_adapter(&(iface->adap)); | |
725 | free_irq(iface->irq, iface); | |
74d362e0 | 726 | peripheral_free_list(pin_req[pdev->id]); |
aa3d0209 BW |
727 | iounmap(iface->regs_base); |
728 | kfree(iface); | |
d24ecfcc BW |
729 | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static struct platform_driver i2c_bfin_twi_driver = { | |
734 | .probe = i2c_bfin_twi_probe, | |
735 | .remove = i2c_bfin_twi_remove, | |
736 | .suspend = i2c_bfin_twi_suspend, | |
737 | .resume = i2c_bfin_twi_resume, | |
738 | .driver = { | |
739 | .name = "i2c-bfin-twi", | |
740 | .owner = THIS_MODULE, | |
741 | }, | |
742 | }; | |
743 | ||
744 | static int __init i2c_bfin_twi_init(void) | |
745 | { | |
d24ecfcc BW |
746 | return platform_driver_register(&i2c_bfin_twi_driver); |
747 | } | |
748 | ||
749 | static void __exit i2c_bfin_twi_exit(void) | |
750 | { | |
751 | platform_driver_unregister(&i2c_bfin_twi_driver); | |
752 | } | |
753 | ||
d24ecfcc BW |
754 | module_init(i2c_bfin_twi_init); |
755 | module_exit(i2c_bfin_twi_exit); | |
fa6ad222 BW |
756 | |
757 | MODULE_AUTHOR("Bryan Wu, Sonic Zhang"); | |
758 | MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver"); | |
759 | MODULE_LICENSE("GPL"); | |
add8eda7 | 760 | MODULE_ALIAS("platform:i2c-bfin-twi"); |