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Commit | Line | Data |
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d24ecfcc | 1 | /* |
bd584996 | 2 | * Blackfin On-Chip Two Wire Interface Driver |
d24ecfcc | 3 | * |
bd584996 | 4 | * Copyright 2005-2007 Analog Devices Inc. |
d24ecfcc | 5 | * |
bd584996 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
d24ecfcc | 7 | * |
bd584996 | 8 | * Licensed under the GPL-2 or later. |
d24ecfcc BW |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/i2c.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
6df263cf | 16 | #include <linux/io.h> |
d24ecfcc BW |
17 | #include <linux/mm.h> |
18 | #include <linux/timer.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
540ac555 | 23 | #include <linux/delay.h> |
d24ecfcc BW |
24 | |
25 | #include <asm/blackfin.h> | |
74d362e0 | 26 | #include <asm/portmux.h> |
d24ecfcc BW |
27 | #include <asm/irq.h> |
28 | ||
d24ecfcc | 29 | /* SMBus mode*/ |
4dd39bb1 SZ |
30 | #define TWI_I2C_MODE_STANDARD 1 |
31 | #define TWI_I2C_MODE_STANDARDSUB 2 | |
32 | #define TWI_I2C_MODE_COMBINED 3 | |
33 | #define TWI_I2C_MODE_REPEAT 4 | |
d24ecfcc BW |
34 | |
35 | struct bfin_twi_iface { | |
d24ecfcc BW |
36 | int irq; |
37 | spinlock_t lock; | |
38 | char read_write; | |
39 | u8 command; | |
40 | u8 *transPtr; | |
41 | int readNum; | |
42 | int writeNum; | |
43 | int cur_mode; | |
44 | int manual_stop; | |
45 | int result; | |
d24ecfcc BW |
46 | struct i2c_adapter adap; |
47 | struct completion complete; | |
4dd39bb1 SZ |
48 | struct i2c_msg *pmsg; |
49 | int msg_num; | |
50 | int cur_msg; | |
958585f5 MH |
51 | u16 saved_clkdiv; |
52 | u16 saved_control; | |
aa3d0209 | 53 | void __iomem *regs_base; |
d24ecfcc BW |
54 | }; |
55 | ||
aa3d0209 BW |
56 | |
57 | #define DEFINE_TWI_REG(reg, off) \ | |
58 | static inline u16 read_##reg(struct bfin_twi_iface *iface) \ | |
59 | { return bfin_read16(iface->regs_base + (off)); } \ | |
60 | static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \ | |
61 | { bfin_write16(iface->regs_base + (off), v); } | |
62 | ||
63 | DEFINE_TWI_REG(CLKDIV, 0x00) | |
64 | DEFINE_TWI_REG(CONTROL, 0x04) | |
65 | DEFINE_TWI_REG(SLAVE_CTL, 0x08) | |
66 | DEFINE_TWI_REG(SLAVE_STAT, 0x0C) | |
67 | DEFINE_TWI_REG(SLAVE_ADDR, 0x10) | |
68 | DEFINE_TWI_REG(MASTER_CTL, 0x14) | |
69 | DEFINE_TWI_REG(MASTER_STAT, 0x18) | |
70 | DEFINE_TWI_REG(MASTER_ADDR, 0x1C) | |
71 | DEFINE_TWI_REG(INT_STAT, 0x20) | |
72 | DEFINE_TWI_REG(INT_MASK, 0x24) | |
73 | DEFINE_TWI_REG(FIFO_CTL, 0x28) | |
74 | DEFINE_TWI_REG(FIFO_STAT, 0x2C) | |
75 | DEFINE_TWI_REG(XMT_DATA8, 0x80) | |
76 | DEFINE_TWI_REG(XMT_DATA16, 0x84) | |
77 | DEFINE_TWI_REG(RCV_DATA8, 0x88) | |
78 | DEFINE_TWI_REG(RCV_DATA16, 0x8C) | |
d24ecfcc | 79 | |
74d362e0 BW |
80 | static const u16 pin_req[2][3] = { |
81 | {P_TWI0_SCL, P_TWI0_SDA, 0}, | |
82 | {P_TWI1_SCL, P_TWI1_SDA, 0}, | |
83 | }; | |
84 | ||
5481d075 SZ |
85 | static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, |
86 | unsigned short twi_int_status) | |
d24ecfcc | 87 | { |
aa3d0209 | 88 | unsigned short mast_stat = read_MASTER_STAT(iface); |
d24ecfcc BW |
89 | |
90 | if (twi_int_status & XMTSERV) { | |
91 | /* Transmit next data */ | |
92 | if (iface->writeNum > 0) { | |
5481d075 | 93 | SSYNC(); |
aa3d0209 | 94 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
d24ecfcc BW |
95 | iface->writeNum--; |
96 | } | |
97 | /* start receive immediately after complete sending in | |
98 | * combine mode. | |
99 | */ | |
4dd39bb1 | 100 | else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) |
aa3d0209 BW |
101 | write_MASTER_CTL(iface, |
102 | read_MASTER_CTL(iface) | MDIR | RSTART); | |
4dd39bb1 | 103 | else if (iface->manual_stop) |
aa3d0209 BW |
104 | write_MASTER_CTL(iface, |
105 | read_MASTER_CTL(iface) | STOP); | |
4dd39bb1 | 106 | else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
94327d00 FS |
107 | iface->cur_msg + 1 < iface->msg_num) { |
108 | if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) | |
109 | write_MASTER_CTL(iface, | |
110 | read_MASTER_CTL(iface) | RSTART | MDIR); | |
111 | else | |
112 | write_MASTER_CTL(iface, | |
113 | (read_MASTER_CTL(iface) | RSTART) & ~MDIR); | |
114 | } | |
d24ecfcc BW |
115 | } |
116 | if (twi_int_status & RCVSERV) { | |
117 | if (iface->readNum > 0) { | |
118 | /* Receive next data */ | |
aa3d0209 | 119 | *(iface->transPtr) = read_RCV_DATA8(iface); |
d24ecfcc BW |
120 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { |
121 | /* Change combine mode into sub mode after | |
122 | * read first data. | |
123 | */ | |
124 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
125 | /* Get read number from first byte in block | |
126 | * combine mode. | |
127 | */ | |
128 | if (iface->readNum == 1 && iface->manual_stop) | |
129 | iface->readNum = *iface->transPtr + 1; | |
130 | } | |
131 | iface->transPtr++; | |
132 | iface->readNum--; | |
133 | } else if (iface->manual_stop) { | |
925594e0 MH |
134 | /* Temporary workaround to avoid possible bus stall - |
135 | * Flush FIFO before issuing the STOP condition | |
136 | */ | |
137 | read_RCV_DATA16(iface); | |
aa3d0209 BW |
138 | write_MASTER_CTL(iface, |
139 | read_MASTER_CTL(iface) | STOP); | |
4dd39bb1 | 140 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
94327d00 FS |
141 | iface->cur_msg + 1 < iface->msg_num) { |
142 | if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) | |
143 | write_MASTER_CTL(iface, | |
144 | read_MASTER_CTL(iface) | RSTART | MDIR); | |
145 | else | |
146 | write_MASTER_CTL(iface, | |
147 | (read_MASTER_CTL(iface) | RSTART) & ~MDIR); | |
d24ecfcc | 148 | } |
d24ecfcc BW |
149 | } |
150 | if (twi_int_status & MERR) { | |
aa3d0209 BW |
151 | write_INT_MASK(iface, 0); |
152 | write_MASTER_STAT(iface, 0x3e); | |
153 | write_MASTER_CTL(iface, 0); | |
4dd39bb1 | 154 | iface->result = -EIO; |
5cfafc18 MH |
155 | |
156 | if (mast_stat & LOSTARB) | |
157 | dev_dbg(&iface->adap.dev, "Lost Arbitration\n"); | |
158 | if (mast_stat & ANAK) | |
159 | dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n"); | |
160 | if (mast_stat & DNAK) | |
161 | dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n"); | |
162 | if (mast_stat & BUFRDERR) | |
163 | dev_dbg(&iface->adap.dev, "Buffer Read Error\n"); | |
164 | if (mast_stat & BUFWRERR) | |
165 | dev_dbg(&iface->adap.dev, "Buffer Write Error\n"); | |
166 | ||
540ac555 MH |
167 | /* Faulty slave devices, may drive SDA low after a transfer |
168 | * finishes. To release the bus this code generates up to 9 | |
169 | * extra clocks until SDA is released. | |
170 | */ | |
171 | ||
172 | if (read_MASTER_STAT(iface) & SDASEN) { | |
173 | int cnt = 9; | |
174 | do { | |
175 | write_MASTER_CTL(iface, SCLOVR); | |
176 | udelay(6); | |
177 | write_MASTER_CTL(iface, 0); | |
178 | udelay(6); | |
179 | } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--); | |
180 | ||
181 | write_MASTER_CTL(iface, SDAOVR | SCLOVR); | |
182 | udelay(6); | |
183 | write_MASTER_CTL(iface, SDAOVR); | |
184 | udelay(6); | |
185 | write_MASTER_CTL(iface, 0); | |
186 | } | |
187 | ||
f0ac131a SZ |
188 | /* If it is a quick transfer, only address without data, |
189 | * not an err, return 1. | |
d24ecfcc | 190 | */ |
f0ac131a SZ |
191 | if (iface->cur_mode == TWI_I2C_MODE_STANDARD && |
192 | iface->transPtr == NULL && | |
193 | (twi_int_status & MCOMP) && (mast_stat & DNAK)) | |
194 | iface->result = 1; | |
195 | ||
d24ecfcc BW |
196 | complete(&iface->complete); |
197 | return; | |
198 | } | |
199 | if (twi_int_status & MCOMP) { | |
4a65163e SZ |
200 | if ((read_MASTER_CTL(iface) & MEN) == 0 && |
201 | (iface->cur_mode == TWI_I2C_MODE_REPEAT || | |
202 | iface->cur_mode == TWI_I2C_MODE_COMBINED)) { | |
203 | iface->result = -1; | |
204 | write_INT_MASK(iface, 0); | |
205 | write_MASTER_CTL(iface, 0); | |
206 | } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
d24ecfcc BW |
207 | if (iface->readNum == 0) { |
208 | /* set the read number to 1 and ask for manual | |
209 | * stop in block combine mode | |
210 | */ | |
211 | iface->readNum = 1; | |
212 | iface->manual_stop = 1; | |
aa3d0209 BW |
213 | write_MASTER_CTL(iface, |
214 | read_MASTER_CTL(iface) | (0xff << 6)); | |
d24ecfcc BW |
215 | } else { |
216 | /* set the readd number in other | |
217 | * combine mode. | |
218 | */ | |
aa3d0209 BW |
219 | write_MASTER_CTL(iface, |
220 | (read_MASTER_CTL(iface) & | |
d24ecfcc | 221 | (~(0xff << 6))) | |
aa3d0209 | 222 | (iface->readNum << 6)); |
d24ecfcc BW |
223 | } |
224 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
225 | write_MASTER_CTL(iface, |
226 | read_MASTER_CTL(iface) & ~RSTART); | |
4dd39bb1 SZ |
227 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
228 | iface->cur_msg+1 < iface->msg_num) { | |
229 | iface->cur_msg++; | |
230 | iface->transPtr = iface->pmsg[iface->cur_msg].buf; | |
231 | iface->writeNum = iface->readNum = | |
232 | iface->pmsg[iface->cur_msg].len; | |
233 | /* Set Transmit device address */ | |
aa3d0209 | 234 | write_MASTER_ADDR(iface, |
4dd39bb1 SZ |
235 | iface->pmsg[iface->cur_msg].addr); |
236 | if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) | |
237 | iface->read_write = I2C_SMBUS_READ; | |
238 | else { | |
239 | iface->read_write = I2C_SMBUS_WRITE; | |
240 | /* Transmit first data */ | |
241 | if (iface->writeNum > 0) { | |
aa3d0209 | 242 | write_XMT_DATA8(iface, |
4dd39bb1 SZ |
243 | *(iface->transPtr++)); |
244 | iface->writeNum--; | |
4dd39bb1 SZ |
245 | } |
246 | } | |
247 | ||
248 | if (iface->pmsg[iface->cur_msg].len <= 255) | |
57a8f32e SZ |
249 | write_MASTER_CTL(iface, |
250 | (read_MASTER_CTL(iface) & | |
251 | (~(0xff << 6))) | | |
252 | (iface->pmsg[iface->cur_msg].len << 6)); | |
4dd39bb1 | 253 | else { |
57a8f32e SZ |
254 | write_MASTER_CTL(iface, |
255 | (read_MASTER_CTL(iface) | | |
256 | (0xff << 6))); | |
4dd39bb1 SZ |
257 | iface->manual_stop = 1; |
258 | } | |
259 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
260 | write_MASTER_CTL(iface, |
261 | read_MASTER_CTL(iface) & ~RSTART); | |
d24ecfcc BW |
262 | } else { |
263 | iface->result = 1; | |
aa3d0209 BW |
264 | write_INT_MASK(iface, 0); |
265 | write_MASTER_CTL(iface, 0); | |
d24ecfcc BW |
266 | } |
267 | } | |
dd7319a5 | 268 | complete(&iface->complete); |
d24ecfcc BW |
269 | } |
270 | ||
271 | /* Interrupt handler */ | |
272 | static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) | |
273 | { | |
274 | struct bfin_twi_iface *iface = dev_id; | |
275 | unsigned long flags; | |
5481d075 | 276 | unsigned short twi_int_status; |
d24ecfcc BW |
277 | |
278 | spin_lock_irqsave(&iface->lock, flags); | |
5481d075 SZ |
279 | while (1) { |
280 | twi_int_status = read_INT_STAT(iface); | |
281 | if (!twi_int_status) | |
282 | break; | |
283 | /* Clear interrupt status */ | |
284 | write_INT_STAT(iface, twi_int_status); | |
285 | bfin_twi_handle_interrupt(iface, twi_int_status); | |
286 | SSYNC(); | |
287 | } | |
d24ecfcc BW |
288 | spin_unlock_irqrestore(&iface->lock, flags); |
289 | return IRQ_HANDLED; | |
290 | } | |
291 | ||
d24ecfcc | 292 | /* |
dd7319a5 | 293 | * One i2c master transfer |
d24ecfcc | 294 | */ |
dd7319a5 | 295 | static int bfin_twi_do_master_xfer(struct i2c_adapter *adap, |
d24ecfcc BW |
296 | struct i2c_msg *msgs, int num) |
297 | { | |
298 | struct bfin_twi_iface *iface = adap->algo_data; | |
299 | struct i2c_msg *pmsg; | |
d24ecfcc BW |
300 | int rc = 0; |
301 | ||
aa3d0209 | 302 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
303 | return -ENXIO; |
304 | ||
aa3d0209 | 305 | while (read_MASTER_STAT(iface) & BUSBUSY) |
d24ecfcc | 306 | yield(); |
d24ecfcc | 307 | |
4dd39bb1 SZ |
308 | iface->pmsg = msgs; |
309 | iface->msg_num = num; | |
310 | iface->cur_msg = 0; | |
d24ecfcc | 311 | |
4dd39bb1 SZ |
312 | pmsg = &msgs[0]; |
313 | if (pmsg->flags & I2C_M_TEN) { | |
314 | dev_err(&adap->dev, "10 bits addr not supported!\n"); | |
315 | return -EINVAL; | |
316 | } | |
d24ecfcc | 317 | |
4dd39bb1 SZ |
318 | iface->cur_mode = TWI_I2C_MODE_REPEAT; |
319 | iface->manual_stop = 0; | |
320 | iface->transPtr = pmsg->buf; | |
321 | iface->writeNum = iface->readNum = pmsg->len; | |
322 | iface->result = 0; | |
afc13b76 | 323 | init_completion(&(iface->complete)); |
4dd39bb1 | 324 | /* Set Transmit device address */ |
aa3d0209 | 325 | write_MASTER_ADDR(iface, pmsg->addr); |
4dd39bb1 SZ |
326 | |
327 | /* FIFO Initiation. Data in FIFO should be | |
328 | * discarded before start a new operation. | |
329 | */ | |
aa3d0209 | 330 | write_FIFO_CTL(iface, 0x3); |
4dd39bb1 | 331 | SSYNC(); |
aa3d0209 | 332 | write_FIFO_CTL(iface, 0); |
4dd39bb1 SZ |
333 | SSYNC(); |
334 | ||
335 | if (pmsg->flags & I2C_M_RD) | |
336 | iface->read_write = I2C_SMBUS_READ; | |
337 | else { | |
338 | iface->read_write = I2C_SMBUS_WRITE; | |
339 | /* Transmit first data */ | |
340 | if (iface->writeNum > 0) { | |
aa3d0209 | 341 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
4dd39bb1 SZ |
342 | iface->writeNum--; |
343 | SSYNC(); | |
d24ecfcc | 344 | } |
4dd39bb1 | 345 | } |
d24ecfcc | 346 | |
4dd39bb1 | 347 | /* clear int stat */ |
aa3d0209 | 348 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc | 349 | |
4dd39bb1 | 350 | /* Interrupt mask . Enable XMT, RCV interrupt */ |
aa3d0209 | 351 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); |
4dd39bb1 | 352 | SSYNC(); |
d24ecfcc | 353 | |
4dd39bb1 | 354 | if (pmsg->len <= 255) |
aa3d0209 | 355 | write_MASTER_CTL(iface, pmsg->len << 6); |
4dd39bb1 | 356 | else { |
aa3d0209 | 357 | write_MASTER_CTL(iface, 0xff << 6); |
4dd39bb1 SZ |
358 | iface->manual_stop = 1; |
359 | } | |
d24ecfcc | 360 | |
4dd39bb1 | 361 | /* Master enable */ |
aa3d0209 | 362 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
4dd39bb1 SZ |
363 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
364 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
365 | SSYNC(); | |
366 | ||
dd7319a5 SZ |
367 | while (!iface->result) { |
368 | if (!wait_for_completion_timeout(&iface->complete, | |
369 | adap->timeout)) { | |
370 | iface->result = -1; | |
371 | dev_err(&adap->dev, "master transfer timeout\n"); | |
372 | } | |
373 | } | |
d24ecfcc | 374 | |
dd7319a5 SZ |
375 | if (iface->result == 1) |
376 | rc = iface->cur_msg + 1; | |
4dd39bb1 | 377 | else |
dd7319a5 SZ |
378 | rc = iface->result; |
379 | ||
380 | return rc; | |
d24ecfcc BW |
381 | } |
382 | ||
383 | /* | |
dd7319a5 | 384 | * Generic i2c master transfer entrypoint |
d24ecfcc | 385 | */ |
dd7319a5 SZ |
386 | static int bfin_twi_master_xfer(struct i2c_adapter *adap, |
387 | struct i2c_msg *msgs, int num) | |
388 | { | |
be2f80f0 | 389 | return bfin_twi_do_master_xfer(adap, msgs, num); |
dd7319a5 SZ |
390 | } |
391 | ||
392 | /* | |
393 | * One I2C SMBus transfer | |
394 | */ | |
395 | int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
d24ecfcc BW |
396 | unsigned short flags, char read_write, |
397 | u8 command, int size, union i2c_smbus_data *data) | |
398 | { | |
399 | struct bfin_twi_iface *iface = adap->algo_data; | |
400 | int rc = 0; | |
401 | ||
aa3d0209 | 402 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
403 | return -ENXIO; |
404 | ||
aa3d0209 | 405 | while (read_MASTER_STAT(iface) & BUSBUSY) |
d24ecfcc | 406 | yield(); |
d24ecfcc BW |
407 | |
408 | iface->writeNum = 0; | |
409 | iface->readNum = 0; | |
410 | ||
411 | /* Prepare datas & select mode */ | |
412 | switch (size) { | |
413 | case I2C_SMBUS_QUICK: | |
414 | iface->transPtr = NULL; | |
415 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
416 | break; | |
417 | case I2C_SMBUS_BYTE: | |
418 | if (data == NULL) | |
419 | iface->transPtr = NULL; | |
420 | else { | |
421 | if (read_write == I2C_SMBUS_READ) | |
422 | iface->readNum = 1; | |
423 | else | |
424 | iface->writeNum = 1; | |
425 | iface->transPtr = &data->byte; | |
426 | } | |
427 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
428 | break; | |
429 | case I2C_SMBUS_BYTE_DATA: | |
430 | if (read_write == I2C_SMBUS_READ) { | |
431 | iface->readNum = 1; | |
432 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
433 | } else { | |
434 | iface->writeNum = 1; | |
435 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
436 | } | |
437 | iface->transPtr = &data->byte; | |
438 | break; | |
439 | case I2C_SMBUS_WORD_DATA: | |
440 | if (read_write == I2C_SMBUS_READ) { | |
441 | iface->readNum = 2; | |
442 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
443 | } else { | |
444 | iface->writeNum = 2; | |
445 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
446 | } | |
447 | iface->transPtr = (u8 *)&data->word; | |
448 | break; | |
449 | case I2C_SMBUS_PROC_CALL: | |
450 | iface->writeNum = 2; | |
451 | iface->readNum = 2; | |
452 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
453 | iface->transPtr = (u8 *)&data->word; | |
454 | break; | |
455 | case I2C_SMBUS_BLOCK_DATA: | |
456 | if (read_write == I2C_SMBUS_READ) { | |
457 | iface->readNum = 0; | |
458 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
459 | } else { | |
460 | iface->writeNum = data->block[0] + 1; | |
461 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
462 | } | |
463 | iface->transPtr = data->block; | |
464 | break; | |
e0cd2dd5 MH |
465 | case I2C_SMBUS_I2C_BLOCK_DATA: |
466 | if (read_write == I2C_SMBUS_READ) { | |
467 | iface->readNum = data->block[0]; | |
468 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
469 | } else { | |
470 | iface->writeNum = data->block[0]; | |
471 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
472 | } | |
473 | iface->transPtr = (u8 *)&data->block[1]; | |
474 | break; | |
d24ecfcc BW |
475 | default: |
476 | return -1; | |
477 | } | |
478 | ||
479 | iface->result = 0; | |
480 | iface->manual_stop = 0; | |
481 | iface->read_write = read_write; | |
482 | iface->command = command; | |
afc13b76 | 483 | init_completion(&(iface->complete)); |
d24ecfcc BW |
484 | |
485 | /* FIFO Initiation. Data in FIFO should be discarded before | |
486 | * start a new operation. | |
487 | */ | |
aa3d0209 | 488 | write_FIFO_CTL(iface, 0x3); |
d24ecfcc | 489 | SSYNC(); |
aa3d0209 | 490 | write_FIFO_CTL(iface, 0); |
d24ecfcc BW |
491 | |
492 | /* clear int stat */ | |
aa3d0209 | 493 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc BW |
494 | |
495 | /* Set Transmit device address */ | |
aa3d0209 | 496 | write_MASTER_ADDR(iface, addr); |
d24ecfcc BW |
497 | SSYNC(); |
498 | ||
d24ecfcc BW |
499 | switch (iface->cur_mode) { |
500 | case TWI_I2C_MODE_STANDARDSUB: | |
aa3d0209 BW |
501 | write_XMT_DATA8(iface, iface->command); |
502 | write_INT_MASK(iface, MCOMP | MERR | | |
d24ecfcc BW |
503 | ((iface->read_write == I2C_SMBUS_READ) ? |
504 | RCVSERV : XMTSERV)); | |
505 | SSYNC(); | |
506 | ||
507 | if (iface->writeNum + 1 <= 255) | |
aa3d0209 | 508 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 509 | else { |
aa3d0209 | 510 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc BW |
511 | iface->manual_stop = 1; |
512 | } | |
513 | /* Master enable */ | |
aa3d0209 | 514 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
515 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
516 | break; | |
517 | case TWI_I2C_MODE_COMBINED: | |
aa3d0209 BW |
518 | write_XMT_DATA8(iface, iface->command); |
519 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); | |
d24ecfcc BW |
520 | SSYNC(); |
521 | ||
522 | if (iface->writeNum > 0) | |
aa3d0209 | 523 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 524 | else |
aa3d0209 | 525 | write_MASTER_CTL(iface, 0x1 << 6); |
d24ecfcc | 526 | /* Master enable */ |
aa3d0209 | 527 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
528 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
529 | break; | |
530 | default: | |
aa3d0209 | 531 | write_MASTER_CTL(iface, 0); |
d24ecfcc BW |
532 | if (size != I2C_SMBUS_QUICK) { |
533 | /* Don't access xmit data register when this is a | |
534 | * read operation. | |
535 | */ | |
536 | if (iface->read_write != I2C_SMBUS_READ) { | |
537 | if (iface->writeNum > 0) { | |
aa3d0209 BW |
538 | write_XMT_DATA8(iface, |
539 | *(iface->transPtr++)); | |
d24ecfcc | 540 | if (iface->writeNum <= 255) |
aa3d0209 BW |
541 | write_MASTER_CTL(iface, |
542 | iface->writeNum << 6); | |
d24ecfcc | 543 | else { |
aa3d0209 BW |
544 | write_MASTER_CTL(iface, |
545 | 0xff << 6); | |
d24ecfcc BW |
546 | iface->manual_stop = 1; |
547 | } | |
548 | iface->writeNum--; | |
549 | } else { | |
aa3d0209 BW |
550 | write_XMT_DATA8(iface, iface->command); |
551 | write_MASTER_CTL(iface, 1 << 6); | |
d24ecfcc BW |
552 | } |
553 | } else { | |
554 | if (iface->readNum > 0 && iface->readNum <= 255) | |
aa3d0209 BW |
555 | write_MASTER_CTL(iface, |
556 | iface->readNum << 6); | |
d24ecfcc | 557 | else if (iface->readNum > 255) { |
aa3d0209 | 558 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc | 559 | iface->manual_stop = 1; |
dd7319a5 | 560 | } else |
d24ecfcc | 561 | break; |
d24ecfcc BW |
562 | } |
563 | } | |
aa3d0209 | 564 | write_INT_MASK(iface, MCOMP | MERR | |
d24ecfcc BW |
565 | ((iface->read_write == I2C_SMBUS_READ) ? |
566 | RCVSERV : XMTSERV)); | |
567 | SSYNC(); | |
568 | ||
569 | /* Master enable */ | |
aa3d0209 | 570 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
571 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
572 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
573 | break; | |
574 | } | |
575 | SSYNC(); | |
576 | ||
dd7319a5 SZ |
577 | while (!iface->result) { |
578 | if (!wait_for_completion_timeout(&iface->complete, | |
579 | adap->timeout)) { | |
580 | iface->result = -1; | |
581 | dev_err(&adap->dev, "smbus transfer timeout\n"); | |
582 | } | |
583 | } | |
d24ecfcc BW |
584 | |
585 | rc = (iface->result >= 0) ? 0 : -1; | |
586 | ||
d24ecfcc BW |
587 | return rc; |
588 | } | |
589 | ||
dd7319a5 SZ |
590 | /* |
591 | * Generic I2C SMBus transfer entrypoint | |
592 | */ | |
593 | int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
594 | unsigned short flags, char read_write, | |
595 | u8 command, int size, union i2c_smbus_data *data) | |
596 | { | |
be2f80f0 | 597 | return bfin_twi_do_smbus_xfer(adap, addr, flags, |
dd7319a5 | 598 | read_write, command, size, data); |
dd7319a5 SZ |
599 | } |
600 | ||
d24ecfcc BW |
601 | /* |
602 | * Return what the adapter supports | |
603 | */ | |
604 | static u32 bfin_twi_functionality(struct i2c_adapter *adap) | |
605 | { | |
606 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
607 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
608 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
e0cd2dd5 | 609 | I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; |
d24ecfcc BW |
610 | } |
611 | ||
d24ecfcc BW |
612 | static struct i2c_algorithm bfin_twi_algorithm = { |
613 | .master_xfer = bfin_twi_master_xfer, | |
614 | .smbus_xfer = bfin_twi_smbus_xfer, | |
615 | .functionality = bfin_twi_functionality, | |
616 | }; | |
617 | ||
85777ad2 | 618 | static int i2c_bfin_twi_suspend(struct device *dev) |
d24ecfcc | 619 | { |
85777ad2 | 620 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
958585f5 MH |
621 | |
622 | iface->saved_clkdiv = read_CLKDIV(iface); | |
623 | iface->saved_control = read_CONTROL(iface); | |
624 | ||
625 | free_irq(iface->irq, iface); | |
d24ecfcc BW |
626 | |
627 | /* Disable TWI */ | |
958585f5 | 628 | write_CONTROL(iface, iface->saved_control & ~TWI_ENA); |
d24ecfcc BW |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
85777ad2 | 633 | static int i2c_bfin_twi_resume(struct device *dev) |
d24ecfcc | 634 | { |
85777ad2 | 635 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
d24ecfcc | 636 | |
958585f5 | 637 | int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
85777ad2 | 638 | 0, to_platform_device(dev)->name, iface); |
958585f5 | 639 | if (rc) { |
85777ad2 | 640 | dev_err(dev, "Can't get IRQ %d !\n", iface->irq); |
958585f5 MH |
641 | return -ENODEV; |
642 | } | |
643 | ||
644 | /* Resume TWI interface clock as specified */ | |
645 | write_CLKDIV(iface, iface->saved_clkdiv); | |
646 | ||
647 | /* Resume TWI */ | |
648 | write_CONTROL(iface, iface->saved_control); | |
d24ecfcc BW |
649 | |
650 | return 0; | |
651 | } | |
652 | ||
85777ad2 RW |
653 | static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm, |
654 | i2c_bfin_twi_suspend, i2c_bfin_twi_resume); | |
655 | ||
aa3d0209 | 656 | static int i2c_bfin_twi_probe(struct platform_device *pdev) |
d24ecfcc | 657 | { |
aa3d0209 | 658 | struct bfin_twi_iface *iface; |
d24ecfcc | 659 | struct i2c_adapter *p_adap; |
aa3d0209 | 660 | struct resource *res; |
d24ecfcc | 661 | int rc; |
9528d1c7 | 662 | unsigned int clkhilow; |
d24ecfcc | 663 | |
aa3d0209 BW |
664 | iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL); |
665 | if (!iface) { | |
666 | dev_err(&pdev->dev, "Cannot allocate memory\n"); | |
667 | rc = -ENOMEM; | |
668 | goto out_error_nomem; | |
669 | } | |
670 | ||
d24ecfcc | 671 | spin_lock_init(&(iface->lock)); |
aa3d0209 BW |
672 | |
673 | /* Find and map our resources */ | |
674 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
675 | if (res == NULL) { | |
676 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
677 | rc = -ENOENT; | |
678 | goto out_error_get_res; | |
679 | } | |
680 | ||
c6ffddea | 681 | iface->regs_base = ioremap(res->start, resource_size(res)); |
aa3d0209 BW |
682 | if (iface->regs_base == NULL) { |
683 | dev_err(&pdev->dev, "Cannot map IO\n"); | |
684 | rc = -ENXIO; | |
685 | goto out_error_ioremap; | |
686 | } | |
687 | ||
688 | iface->irq = platform_get_irq(pdev, 0); | |
689 | if (iface->irq < 0) { | |
690 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
691 | rc = -ENOENT; | |
692 | goto out_error_no_irq; | |
693 | } | |
d24ecfcc | 694 | |
d24ecfcc | 695 | p_adap = &iface->adap; |
aa3d0209 BW |
696 | p_adap->nr = pdev->id; |
697 | strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); | |
d24ecfcc BW |
698 | p_adap->algo = &bfin_twi_algorithm; |
699 | p_adap->algo_data = iface; | |
e1995f65 | 700 | p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
aa3d0209 | 701 | p_adap->dev.parent = &pdev->dev; |
dd7319a5 SZ |
702 | p_adap->timeout = 5 * HZ; |
703 | p_adap->retries = 3; | |
d24ecfcc | 704 | |
74d362e0 BW |
705 | rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi"); |
706 | if (rc) { | |
707 | dev_err(&pdev->dev, "Can't setup pin mux!\n"); | |
708 | goto out_error_pin_mux; | |
709 | } | |
710 | ||
d24ecfcc | 711 | rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
4311051c | 712 | 0, pdev->name, iface); |
d24ecfcc | 713 | if (rc) { |
aa3d0209 BW |
714 | dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); |
715 | rc = -ENODEV; | |
716 | goto out_error_req_irq; | |
d24ecfcc BW |
717 | } |
718 | ||
719 | /* Set TWI internal clock as 10MHz */ | |
ac07fb4d | 720 | write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F); |
d24ecfcc | 721 | |
9528d1c7 MH |
722 | /* |
723 | * We will not end up with a CLKDIV=0 because no one will specify | |
ac07fb4d | 724 | * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250) |
9528d1c7 | 725 | */ |
ac07fb4d | 726 | clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2; |
9528d1c7 | 727 | |
d24ecfcc | 728 | /* Set Twi interface clock as specified */ |
9528d1c7 | 729 | write_CLKDIV(iface, (clkhilow << 8) | clkhilow); |
d24ecfcc BW |
730 | |
731 | /* Enable TWI */ | |
aa3d0209 | 732 | write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); |
d24ecfcc BW |
733 | SSYNC(); |
734 | ||
991dee59 | 735 | rc = i2c_add_numbered_adapter(p_adap); |
aa3d0209 BW |
736 | if (rc < 0) { |
737 | dev_err(&pdev->dev, "Can't add i2c adapter!\n"); | |
738 | goto out_error_add_adapter; | |
739 | } | |
740 | ||
741 | platform_set_drvdata(pdev, iface); | |
d24ecfcc | 742 | |
fa6ad222 BW |
743 | dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, " |
744 | "regs_base@%p\n", iface->regs_base); | |
aa3d0209 BW |
745 | |
746 | return 0; | |
747 | ||
748 | out_error_add_adapter: | |
749 | free_irq(iface->irq, iface); | |
750 | out_error_req_irq: | |
751 | out_error_no_irq: | |
74d362e0 BW |
752 | peripheral_free_list(pin_req[pdev->id]); |
753 | out_error_pin_mux: | |
aa3d0209 BW |
754 | iounmap(iface->regs_base); |
755 | out_error_ioremap: | |
756 | out_error_get_res: | |
757 | kfree(iface); | |
758 | out_error_nomem: | |
d24ecfcc BW |
759 | return rc; |
760 | } | |
761 | ||
762 | static int i2c_bfin_twi_remove(struct platform_device *pdev) | |
763 | { | |
764 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); | |
765 | ||
766 | platform_set_drvdata(pdev, NULL); | |
767 | ||
768 | i2c_del_adapter(&(iface->adap)); | |
769 | free_irq(iface->irq, iface); | |
74d362e0 | 770 | peripheral_free_list(pin_req[pdev->id]); |
aa3d0209 BW |
771 | iounmap(iface->regs_base); |
772 | kfree(iface); | |
d24ecfcc BW |
773 | |
774 | return 0; | |
775 | } | |
776 | ||
777 | static struct platform_driver i2c_bfin_twi_driver = { | |
778 | .probe = i2c_bfin_twi_probe, | |
779 | .remove = i2c_bfin_twi_remove, | |
d24ecfcc BW |
780 | .driver = { |
781 | .name = "i2c-bfin-twi", | |
782 | .owner = THIS_MODULE, | |
85777ad2 | 783 | .pm = &i2c_bfin_twi_pm, |
d24ecfcc BW |
784 | }, |
785 | }; | |
786 | ||
787 | static int __init i2c_bfin_twi_init(void) | |
788 | { | |
d24ecfcc BW |
789 | return platform_driver_register(&i2c_bfin_twi_driver); |
790 | } | |
791 | ||
792 | static void __exit i2c_bfin_twi_exit(void) | |
793 | { | |
794 | platform_driver_unregister(&i2c_bfin_twi_driver); | |
795 | } | |
796 | ||
74f56c4a | 797 | subsys_initcall(i2c_bfin_twi_init); |
d24ecfcc | 798 | module_exit(i2c_bfin_twi_exit); |
fa6ad222 BW |
799 | |
800 | MODULE_AUTHOR("Bryan Wu, Sonic Zhang"); | |
801 | MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver"); | |
802 | MODULE_LICENSE("GPL"); | |
add8eda7 | 803 | MODULE_ALIAS("platform:i2c-bfin-twi"); |