]>
Commit | Line | Data |
---|---|---|
d24ecfcc | 1 | /* |
bd584996 | 2 | * Blackfin On-Chip Two Wire Interface Driver |
d24ecfcc | 3 | * |
bd584996 | 4 | * Copyright 2005-2007 Analog Devices Inc. |
d24ecfcc | 5 | * |
bd584996 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
d24ecfcc | 7 | * |
bd584996 | 8 | * Licensed under the GPL-2 or later. |
d24ecfcc BW |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/i2c.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
6df263cf | 16 | #include <linux/io.h> |
d24ecfcc BW |
17 | #include <linux/mm.h> |
18 | #include <linux/timer.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
540ac555 | 23 | #include <linux/delay.h> |
d24ecfcc BW |
24 | |
25 | #include <asm/blackfin.h> | |
74d362e0 | 26 | #include <asm/portmux.h> |
d24ecfcc BW |
27 | #include <asm/irq.h> |
28 | ||
d24ecfcc | 29 | /* SMBus mode*/ |
4dd39bb1 SZ |
30 | #define TWI_I2C_MODE_STANDARD 1 |
31 | #define TWI_I2C_MODE_STANDARDSUB 2 | |
32 | #define TWI_I2C_MODE_COMBINED 3 | |
33 | #define TWI_I2C_MODE_REPEAT 4 | |
d24ecfcc BW |
34 | |
35 | struct bfin_twi_iface { | |
d24ecfcc BW |
36 | int irq; |
37 | spinlock_t lock; | |
38 | char read_write; | |
39 | u8 command; | |
40 | u8 *transPtr; | |
41 | int readNum; | |
42 | int writeNum; | |
43 | int cur_mode; | |
44 | int manual_stop; | |
45 | int result; | |
d24ecfcc BW |
46 | struct i2c_adapter adap; |
47 | struct completion complete; | |
4dd39bb1 SZ |
48 | struct i2c_msg *pmsg; |
49 | int msg_num; | |
50 | int cur_msg; | |
958585f5 MH |
51 | u16 saved_clkdiv; |
52 | u16 saved_control; | |
aa3d0209 | 53 | void __iomem *regs_base; |
d24ecfcc BW |
54 | }; |
55 | ||
aa3d0209 BW |
56 | |
57 | #define DEFINE_TWI_REG(reg, off) \ | |
58 | static inline u16 read_##reg(struct bfin_twi_iface *iface) \ | |
59 | { return bfin_read16(iface->regs_base + (off)); } \ | |
60 | static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \ | |
61 | { bfin_write16(iface->regs_base + (off), v); } | |
62 | ||
63 | DEFINE_TWI_REG(CLKDIV, 0x00) | |
64 | DEFINE_TWI_REG(CONTROL, 0x04) | |
65 | DEFINE_TWI_REG(SLAVE_CTL, 0x08) | |
66 | DEFINE_TWI_REG(SLAVE_STAT, 0x0C) | |
67 | DEFINE_TWI_REG(SLAVE_ADDR, 0x10) | |
68 | DEFINE_TWI_REG(MASTER_CTL, 0x14) | |
69 | DEFINE_TWI_REG(MASTER_STAT, 0x18) | |
70 | DEFINE_TWI_REG(MASTER_ADDR, 0x1C) | |
71 | DEFINE_TWI_REG(INT_STAT, 0x20) | |
72 | DEFINE_TWI_REG(INT_MASK, 0x24) | |
73 | DEFINE_TWI_REG(FIFO_CTL, 0x28) | |
74 | DEFINE_TWI_REG(FIFO_STAT, 0x2C) | |
75 | DEFINE_TWI_REG(XMT_DATA8, 0x80) | |
76 | DEFINE_TWI_REG(XMT_DATA16, 0x84) | |
77 | DEFINE_TWI_REG(RCV_DATA8, 0x88) | |
78 | DEFINE_TWI_REG(RCV_DATA16, 0x8C) | |
d24ecfcc | 79 | |
74d362e0 BW |
80 | static const u16 pin_req[2][3] = { |
81 | {P_TWI0_SCL, P_TWI0_SDA, 0}, | |
82 | {P_TWI1_SCL, P_TWI1_SDA, 0}, | |
83 | }; | |
84 | ||
5481d075 SZ |
85 | static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, |
86 | unsigned short twi_int_status) | |
d24ecfcc | 87 | { |
aa3d0209 | 88 | unsigned short mast_stat = read_MASTER_STAT(iface); |
d24ecfcc BW |
89 | |
90 | if (twi_int_status & XMTSERV) { | |
91 | /* Transmit next data */ | |
92 | if (iface->writeNum > 0) { | |
5481d075 | 93 | SSYNC(); |
aa3d0209 | 94 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
d24ecfcc BW |
95 | iface->writeNum--; |
96 | } | |
97 | /* start receive immediately after complete sending in | |
98 | * combine mode. | |
99 | */ | |
4dd39bb1 | 100 | else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) |
aa3d0209 BW |
101 | write_MASTER_CTL(iface, |
102 | read_MASTER_CTL(iface) | MDIR | RSTART); | |
4dd39bb1 | 103 | else if (iface->manual_stop) |
aa3d0209 BW |
104 | write_MASTER_CTL(iface, |
105 | read_MASTER_CTL(iface) | STOP); | |
4dd39bb1 | 106 | else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
94327d00 FS |
107 | iface->cur_msg + 1 < iface->msg_num) { |
108 | if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) | |
109 | write_MASTER_CTL(iface, | |
110 | read_MASTER_CTL(iface) | RSTART | MDIR); | |
111 | else | |
112 | write_MASTER_CTL(iface, | |
113 | (read_MASTER_CTL(iface) | RSTART) & ~MDIR); | |
114 | } | |
d24ecfcc BW |
115 | } |
116 | if (twi_int_status & RCVSERV) { | |
117 | if (iface->readNum > 0) { | |
118 | /* Receive next data */ | |
aa3d0209 | 119 | *(iface->transPtr) = read_RCV_DATA8(iface); |
d24ecfcc BW |
120 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { |
121 | /* Change combine mode into sub mode after | |
122 | * read first data. | |
123 | */ | |
124 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
125 | /* Get read number from first byte in block | |
126 | * combine mode. | |
127 | */ | |
128 | if (iface->readNum == 1 && iface->manual_stop) | |
129 | iface->readNum = *iface->transPtr + 1; | |
130 | } | |
131 | iface->transPtr++; | |
132 | iface->readNum--; | |
a20a64d2 SZ |
133 | } |
134 | ||
135 | if (iface->readNum == 0) { | |
136 | if (iface->manual_stop) { | |
137 | /* Temporary workaround to avoid possible bus stall - | |
138 | * Flush FIFO before issuing the STOP condition | |
139 | */ | |
140 | read_RCV_DATA16(iface); | |
94327d00 | 141 | write_MASTER_CTL(iface, |
a20a64d2 SZ |
142 | read_MASTER_CTL(iface) | STOP); |
143 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && | |
144 | iface->cur_msg + 1 < iface->msg_num) { | |
145 | if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) | |
146 | write_MASTER_CTL(iface, | |
147 | read_MASTER_CTL(iface) | RSTART | MDIR); | |
148 | else | |
149 | write_MASTER_CTL(iface, | |
150 | (read_MASTER_CTL(iface) | RSTART) & ~MDIR); | |
151 | } | |
d24ecfcc | 152 | } |
d24ecfcc BW |
153 | } |
154 | if (twi_int_status & MERR) { | |
aa3d0209 BW |
155 | write_INT_MASK(iface, 0); |
156 | write_MASTER_STAT(iface, 0x3e); | |
157 | write_MASTER_CTL(iface, 0); | |
4dd39bb1 | 158 | iface->result = -EIO; |
5cfafc18 MH |
159 | |
160 | if (mast_stat & LOSTARB) | |
161 | dev_dbg(&iface->adap.dev, "Lost Arbitration\n"); | |
162 | if (mast_stat & ANAK) | |
163 | dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n"); | |
164 | if (mast_stat & DNAK) | |
165 | dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n"); | |
166 | if (mast_stat & BUFRDERR) | |
167 | dev_dbg(&iface->adap.dev, "Buffer Read Error\n"); | |
168 | if (mast_stat & BUFWRERR) | |
169 | dev_dbg(&iface->adap.dev, "Buffer Write Error\n"); | |
170 | ||
540ac555 MH |
171 | /* Faulty slave devices, may drive SDA low after a transfer |
172 | * finishes. To release the bus this code generates up to 9 | |
173 | * extra clocks until SDA is released. | |
174 | */ | |
175 | ||
176 | if (read_MASTER_STAT(iface) & SDASEN) { | |
177 | int cnt = 9; | |
178 | do { | |
179 | write_MASTER_CTL(iface, SCLOVR); | |
180 | udelay(6); | |
181 | write_MASTER_CTL(iface, 0); | |
182 | udelay(6); | |
183 | } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--); | |
184 | ||
185 | write_MASTER_CTL(iface, SDAOVR | SCLOVR); | |
186 | udelay(6); | |
187 | write_MASTER_CTL(iface, SDAOVR); | |
188 | udelay(6); | |
189 | write_MASTER_CTL(iface, 0); | |
190 | } | |
191 | ||
f0ac131a SZ |
192 | /* If it is a quick transfer, only address without data, |
193 | * not an err, return 1. | |
d24ecfcc | 194 | */ |
f0ac131a SZ |
195 | if (iface->cur_mode == TWI_I2C_MODE_STANDARD && |
196 | iface->transPtr == NULL && | |
197 | (twi_int_status & MCOMP) && (mast_stat & DNAK)) | |
198 | iface->result = 1; | |
199 | ||
d24ecfcc BW |
200 | complete(&iface->complete); |
201 | return; | |
202 | } | |
203 | if (twi_int_status & MCOMP) { | |
4a65163e SZ |
204 | if ((read_MASTER_CTL(iface) & MEN) == 0 && |
205 | (iface->cur_mode == TWI_I2C_MODE_REPEAT || | |
206 | iface->cur_mode == TWI_I2C_MODE_COMBINED)) { | |
207 | iface->result = -1; | |
208 | write_INT_MASK(iface, 0); | |
209 | write_MASTER_CTL(iface, 0); | |
210 | } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
d24ecfcc BW |
211 | if (iface->readNum == 0) { |
212 | /* set the read number to 1 and ask for manual | |
213 | * stop in block combine mode | |
214 | */ | |
215 | iface->readNum = 1; | |
216 | iface->manual_stop = 1; | |
aa3d0209 BW |
217 | write_MASTER_CTL(iface, |
218 | read_MASTER_CTL(iface) | (0xff << 6)); | |
d24ecfcc BW |
219 | } else { |
220 | /* set the readd number in other | |
221 | * combine mode. | |
222 | */ | |
aa3d0209 BW |
223 | write_MASTER_CTL(iface, |
224 | (read_MASTER_CTL(iface) & | |
d24ecfcc | 225 | (~(0xff << 6))) | |
aa3d0209 | 226 | (iface->readNum << 6)); |
d24ecfcc BW |
227 | } |
228 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
229 | write_MASTER_CTL(iface, |
230 | read_MASTER_CTL(iface) & ~RSTART); | |
4dd39bb1 SZ |
231 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
232 | iface->cur_msg+1 < iface->msg_num) { | |
233 | iface->cur_msg++; | |
234 | iface->transPtr = iface->pmsg[iface->cur_msg].buf; | |
235 | iface->writeNum = iface->readNum = | |
236 | iface->pmsg[iface->cur_msg].len; | |
237 | /* Set Transmit device address */ | |
aa3d0209 | 238 | write_MASTER_ADDR(iface, |
4dd39bb1 SZ |
239 | iface->pmsg[iface->cur_msg].addr); |
240 | if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) | |
241 | iface->read_write = I2C_SMBUS_READ; | |
242 | else { | |
243 | iface->read_write = I2C_SMBUS_WRITE; | |
244 | /* Transmit first data */ | |
245 | if (iface->writeNum > 0) { | |
aa3d0209 | 246 | write_XMT_DATA8(iface, |
4dd39bb1 SZ |
247 | *(iface->transPtr++)); |
248 | iface->writeNum--; | |
4dd39bb1 SZ |
249 | } |
250 | } | |
251 | ||
a20a64d2 SZ |
252 | if (iface->pmsg[iface->cur_msg].len <= 255) { |
253 | write_MASTER_CTL(iface, | |
57a8f32e SZ |
254 | (read_MASTER_CTL(iface) & |
255 | (~(0xff << 6))) | | |
a20a64d2 SZ |
256 | (iface->pmsg[iface->cur_msg].len << 6)); |
257 | iface->manual_stop = 0; | |
258 | } else { | |
57a8f32e SZ |
259 | write_MASTER_CTL(iface, |
260 | (read_MASTER_CTL(iface) | | |
261 | (0xff << 6))); | |
4dd39bb1 SZ |
262 | iface->manual_stop = 1; |
263 | } | |
264 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
265 | write_MASTER_CTL(iface, |
266 | read_MASTER_CTL(iface) & ~RSTART); | |
d24ecfcc BW |
267 | } else { |
268 | iface->result = 1; | |
aa3d0209 BW |
269 | write_INT_MASK(iface, 0); |
270 | write_MASTER_CTL(iface, 0); | |
d24ecfcc | 271 | } |
a20a64d2 | 272 | complete(&iface->complete); |
d24ecfcc BW |
273 | } |
274 | } | |
275 | ||
276 | /* Interrupt handler */ | |
277 | static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) | |
278 | { | |
279 | struct bfin_twi_iface *iface = dev_id; | |
280 | unsigned long flags; | |
5481d075 | 281 | unsigned short twi_int_status; |
d24ecfcc BW |
282 | |
283 | spin_lock_irqsave(&iface->lock, flags); | |
5481d075 SZ |
284 | while (1) { |
285 | twi_int_status = read_INT_STAT(iface); | |
286 | if (!twi_int_status) | |
287 | break; | |
288 | /* Clear interrupt status */ | |
289 | write_INT_STAT(iface, twi_int_status); | |
290 | bfin_twi_handle_interrupt(iface, twi_int_status); | |
291 | SSYNC(); | |
292 | } | |
d24ecfcc BW |
293 | spin_unlock_irqrestore(&iface->lock, flags); |
294 | return IRQ_HANDLED; | |
295 | } | |
296 | ||
d24ecfcc | 297 | /* |
dd7319a5 | 298 | * One i2c master transfer |
d24ecfcc | 299 | */ |
dd7319a5 | 300 | static int bfin_twi_do_master_xfer(struct i2c_adapter *adap, |
d24ecfcc BW |
301 | struct i2c_msg *msgs, int num) |
302 | { | |
303 | struct bfin_twi_iface *iface = adap->algo_data; | |
304 | struct i2c_msg *pmsg; | |
d24ecfcc BW |
305 | int rc = 0; |
306 | ||
aa3d0209 | 307 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
308 | return -ENXIO; |
309 | ||
a25733d6 SZ |
310 | if (read_MASTER_STAT(iface) & BUSBUSY) |
311 | return -EAGAIN; | |
d24ecfcc | 312 | |
4dd39bb1 SZ |
313 | iface->pmsg = msgs; |
314 | iface->msg_num = num; | |
315 | iface->cur_msg = 0; | |
d24ecfcc | 316 | |
4dd39bb1 SZ |
317 | pmsg = &msgs[0]; |
318 | if (pmsg->flags & I2C_M_TEN) { | |
319 | dev_err(&adap->dev, "10 bits addr not supported!\n"); | |
320 | return -EINVAL; | |
321 | } | |
d24ecfcc | 322 | |
4dd39bb1 SZ |
323 | iface->cur_mode = TWI_I2C_MODE_REPEAT; |
324 | iface->manual_stop = 0; | |
325 | iface->transPtr = pmsg->buf; | |
326 | iface->writeNum = iface->readNum = pmsg->len; | |
327 | iface->result = 0; | |
afc13b76 | 328 | init_completion(&(iface->complete)); |
4dd39bb1 | 329 | /* Set Transmit device address */ |
aa3d0209 | 330 | write_MASTER_ADDR(iface, pmsg->addr); |
4dd39bb1 SZ |
331 | |
332 | /* FIFO Initiation. Data in FIFO should be | |
333 | * discarded before start a new operation. | |
334 | */ | |
aa3d0209 | 335 | write_FIFO_CTL(iface, 0x3); |
4dd39bb1 | 336 | SSYNC(); |
aa3d0209 | 337 | write_FIFO_CTL(iface, 0); |
4dd39bb1 SZ |
338 | SSYNC(); |
339 | ||
340 | if (pmsg->flags & I2C_M_RD) | |
341 | iface->read_write = I2C_SMBUS_READ; | |
342 | else { | |
343 | iface->read_write = I2C_SMBUS_WRITE; | |
344 | /* Transmit first data */ | |
345 | if (iface->writeNum > 0) { | |
aa3d0209 | 346 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
4dd39bb1 SZ |
347 | iface->writeNum--; |
348 | SSYNC(); | |
d24ecfcc | 349 | } |
4dd39bb1 | 350 | } |
d24ecfcc | 351 | |
4dd39bb1 | 352 | /* clear int stat */ |
aa3d0209 | 353 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc | 354 | |
4dd39bb1 | 355 | /* Interrupt mask . Enable XMT, RCV interrupt */ |
aa3d0209 | 356 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); |
4dd39bb1 | 357 | SSYNC(); |
d24ecfcc | 358 | |
4dd39bb1 | 359 | if (pmsg->len <= 255) |
aa3d0209 | 360 | write_MASTER_CTL(iface, pmsg->len << 6); |
4dd39bb1 | 361 | else { |
aa3d0209 | 362 | write_MASTER_CTL(iface, 0xff << 6); |
4dd39bb1 SZ |
363 | iface->manual_stop = 1; |
364 | } | |
d24ecfcc | 365 | |
4dd39bb1 | 366 | /* Master enable */ |
aa3d0209 | 367 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
4dd39bb1 SZ |
368 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
369 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
370 | SSYNC(); | |
371 | ||
dd7319a5 SZ |
372 | while (!iface->result) { |
373 | if (!wait_for_completion_timeout(&iface->complete, | |
374 | adap->timeout)) { | |
375 | iface->result = -1; | |
376 | dev_err(&adap->dev, "master transfer timeout\n"); | |
377 | } | |
378 | } | |
d24ecfcc | 379 | |
dd7319a5 SZ |
380 | if (iface->result == 1) |
381 | rc = iface->cur_msg + 1; | |
4dd39bb1 | 382 | else |
dd7319a5 SZ |
383 | rc = iface->result; |
384 | ||
385 | return rc; | |
d24ecfcc BW |
386 | } |
387 | ||
388 | /* | |
dd7319a5 | 389 | * Generic i2c master transfer entrypoint |
d24ecfcc | 390 | */ |
dd7319a5 SZ |
391 | static int bfin_twi_master_xfer(struct i2c_adapter *adap, |
392 | struct i2c_msg *msgs, int num) | |
393 | { | |
be2f80f0 | 394 | return bfin_twi_do_master_xfer(adap, msgs, num); |
dd7319a5 SZ |
395 | } |
396 | ||
397 | /* | |
398 | * One I2C SMBus transfer | |
399 | */ | |
400 | int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
d24ecfcc BW |
401 | unsigned short flags, char read_write, |
402 | u8 command, int size, union i2c_smbus_data *data) | |
403 | { | |
404 | struct bfin_twi_iface *iface = adap->algo_data; | |
405 | int rc = 0; | |
406 | ||
aa3d0209 | 407 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
408 | return -ENXIO; |
409 | ||
a25733d6 SZ |
410 | if (read_MASTER_STAT(iface) & BUSBUSY) |
411 | return -EAGAIN; | |
d24ecfcc BW |
412 | |
413 | iface->writeNum = 0; | |
414 | iface->readNum = 0; | |
415 | ||
416 | /* Prepare datas & select mode */ | |
417 | switch (size) { | |
418 | case I2C_SMBUS_QUICK: | |
419 | iface->transPtr = NULL; | |
420 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
421 | break; | |
422 | case I2C_SMBUS_BYTE: | |
423 | if (data == NULL) | |
424 | iface->transPtr = NULL; | |
425 | else { | |
426 | if (read_write == I2C_SMBUS_READ) | |
427 | iface->readNum = 1; | |
428 | else | |
429 | iface->writeNum = 1; | |
430 | iface->transPtr = &data->byte; | |
431 | } | |
432 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
433 | break; | |
434 | case I2C_SMBUS_BYTE_DATA: | |
435 | if (read_write == I2C_SMBUS_READ) { | |
436 | iface->readNum = 1; | |
437 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
438 | } else { | |
439 | iface->writeNum = 1; | |
440 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
441 | } | |
442 | iface->transPtr = &data->byte; | |
443 | break; | |
444 | case I2C_SMBUS_WORD_DATA: | |
445 | if (read_write == I2C_SMBUS_READ) { | |
446 | iface->readNum = 2; | |
447 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
448 | } else { | |
449 | iface->writeNum = 2; | |
450 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
451 | } | |
452 | iface->transPtr = (u8 *)&data->word; | |
453 | break; | |
454 | case I2C_SMBUS_PROC_CALL: | |
455 | iface->writeNum = 2; | |
456 | iface->readNum = 2; | |
457 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
458 | iface->transPtr = (u8 *)&data->word; | |
459 | break; | |
460 | case I2C_SMBUS_BLOCK_DATA: | |
461 | if (read_write == I2C_SMBUS_READ) { | |
462 | iface->readNum = 0; | |
463 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
464 | } else { | |
465 | iface->writeNum = data->block[0] + 1; | |
466 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
467 | } | |
468 | iface->transPtr = data->block; | |
469 | break; | |
e0cd2dd5 MH |
470 | case I2C_SMBUS_I2C_BLOCK_DATA: |
471 | if (read_write == I2C_SMBUS_READ) { | |
472 | iface->readNum = data->block[0]; | |
473 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
474 | } else { | |
475 | iface->writeNum = data->block[0]; | |
476 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
477 | } | |
478 | iface->transPtr = (u8 *)&data->block[1]; | |
479 | break; | |
d24ecfcc BW |
480 | default: |
481 | return -1; | |
482 | } | |
483 | ||
484 | iface->result = 0; | |
485 | iface->manual_stop = 0; | |
486 | iface->read_write = read_write; | |
487 | iface->command = command; | |
afc13b76 | 488 | init_completion(&(iface->complete)); |
d24ecfcc BW |
489 | |
490 | /* FIFO Initiation. Data in FIFO should be discarded before | |
491 | * start a new operation. | |
492 | */ | |
aa3d0209 | 493 | write_FIFO_CTL(iface, 0x3); |
d24ecfcc | 494 | SSYNC(); |
aa3d0209 | 495 | write_FIFO_CTL(iface, 0); |
d24ecfcc BW |
496 | |
497 | /* clear int stat */ | |
aa3d0209 | 498 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc BW |
499 | |
500 | /* Set Transmit device address */ | |
aa3d0209 | 501 | write_MASTER_ADDR(iface, addr); |
d24ecfcc BW |
502 | SSYNC(); |
503 | ||
d24ecfcc BW |
504 | switch (iface->cur_mode) { |
505 | case TWI_I2C_MODE_STANDARDSUB: | |
aa3d0209 BW |
506 | write_XMT_DATA8(iface, iface->command); |
507 | write_INT_MASK(iface, MCOMP | MERR | | |
d24ecfcc BW |
508 | ((iface->read_write == I2C_SMBUS_READ) ? |
509 | RCVSERV : XMTSERV)); | |
510 | SSYNC(); | |
511 | ||
512 | if (iface->writeNum + 1 <= 255) | |
aa3d0209 | 513 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 514 | else { |
aa3d0209 | 515 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc BW |
516 | iface->manual_stop = 1; |
517 | } | |
518 | /* Master enable */ | |
aa3d0209 | 519 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
520 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
521 | break; | |
522 | case TWI_I2C_MODE_COMBINED: | |
aa3d0209 BW |
523 | write_XMT_DATA8(iface, iface->command); |
524 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); | |
d24ecfcc BW |
525 | SSYNC(); |
526 | ||
527 | if (iface->writeNum > 0) | |
aa3d0209 | 528 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 529 | else |
aa3d0209 | 530 | write_MASTER_CTL(iface, 0x1 << 6); |
d24ecfcc | 531 | /* Master enable */ |
aa3d0209 | 532 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
533 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
534 | break; | |
535 | default: | |
aa3d0209 | 536 | write_MASTER_CTL(iface, 0); |
d24ecfcc BW |
537 | if (size != I2C_SMBUS_QUICK) { |
538 | /* Don't access xmit data register when this is a | |
539 | * read operation. | |
540 | */ | |
541 | if (iface->read_write != I2C_SMBUS_READ) { | |
542 | if (iface->writeNum > 0) { | |
aa3d0209 BW |
543 | write_XMT_DATA8(iface, |
544 | *(iface->transPtr++)); | |
d24ecfcc | 545 | if (iface->writeNum <= 255) |
aa3d0209 BW |
546 | write_MASTER_CTL(iface, |
547 | iface->writeNum << 6); | |
d24ecfcc | 548 | else { |
aa3d0209 BW |
549 | write_MASTER_CTL(iface, |
550 | 0xff << 6); | |
d24ecfcc BW |
551 | iface->manual_stop = 1; |
552 | } | |
553 | iface->writeNum--; | |
554 | } else { | |
aa3d0209 BW |
555 | write_XMT_DATA8(iface, iface->command); |
556 | write_MASTER_CTL(iface, 1 << 6); | |
d24ecfcc BW |
557 | } |
558 | } else { | |
559 | if (iface->readNum > 0 && iface->readNum <= 255) | |
aa3d0209 BW |
560 | write_MASTER_CTL(iface, |
561 | iface->readNum << 6); | |
d24ecfcc | 562 | else if (iface->readNum > 255) { |
aa3d0209 | 563 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc | 564 | iface->manual_stop = 1; |
dd7319a5 | 565 | } else |
d24ecfcc | 566 | break; |
d24ecfcc BW |
567 | } |
568 | } | |
aa3d0209 | 569 | write_INT_MASK(iface, MCOMP | MERR | |
d24ecfcc BW |
570 | ((iface->read_write == I2C_SMBUS_READ) ? |
571 | RCVSERV : XMTSERV)); | |
572 | SSYNC(); | |
573 | ||
574 | /* Master enable */ | |
aa3d0209 | 575 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
576 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
577 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
578 | break; | |
579 | } | |
580 | SSYNC(); | |
581 | ||
dd7319a5 SZ |
582 | while (!iface->result) { |
583 | if (!wait_for_completion_timeout(&iface->complete, | |
584 | adap->timeout)) { | |
585 | iface->result = -1; | |
586 | dev_err(&adap->dev, "smbus transfer timeout\n"); | |
587 | } | |
588 | } | |
d24ecfcc BW |
589 | |
590 | rc = (iface->result >= 0) ? 0 : -1; | |
591 | ||
d24ecfcc BW |
592 | return rc; |
593 | } | |
594 | ||
dd7319a5 SZ |
595 | /* |
596 | * Generic I2C SMBus transfer entrypoint | |
597 | */ | |
598 | int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
599 | unsigned short flags, char read_write, | |
600 | u8 command, int size, union i2c_smbus_data *data) | |
601 | { | |
be2f80f0 | 602 | return bfin_twi_do_smbus_xfer(adap, addr, flags, |
dd7319a5 | 603 | read_write, command, size, data); |
dd7319a5 SZ |
604 | } |
605 | ||
d24ecfcc BW |
606 | /* |
607 | * Return what the adapter supports | |
608 | */ | |
609 | static u32 bfin_twi_functionality(struct i2c_adapter *adap) | |
610 | { | |
611 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
612 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
613 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
e0cd2dd5 | 614 | I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; |
d24ecfcc BW |
615 | } |
616 | ||
d24ecfcc BW |
617 | static struct i2c_algorithm bfin_twi_algorithm = { |
618 | .master_xfer = bfin_twi_master_xfer, | |
619 | .smbus_xfer = bfin_twi_smbus_xfer, | |
620 | .functionality = bfin_twi_functionality, | |
621 | }; | |
622 | ||
85777ad2 | 623 | static int i2c_bfin_twi_suspend(struct device *dev) |
d24ecfcc | 624 | { |
85777ad2 | 625 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
958585f5 MH |
626 | |
627 | iface->saved_clkdiv = read_CLKDIV(iface); | |
628 | iface->saved_control = read_CONTROL(iface); | |
629 | ||
630 | free_irq(iface->irq, iface); | |
d24ecfcc BW |
631 | |
632 | /* Disable TWI */ | |
958585f5 | 633 | write_CONTROL(iface, iface->saved_control & ~TWI_ENA); |
d24ecfcc BW |
634 | |
635 | return 0; | |
636 | } | |
637 | ||
85777ad2 | 638 | static int i2c_bfin_twi_resume(struct device *dev) |
d24ecfcc | 639 | { |
85777ad2 | 640 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
d24ecfcc | 641 | |
958585f5 | 642 | int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
85777ad2 | 643 | 0, to_platform_device(dev)->name, iface); |
958585f5 | 644 | if (rc) { |
85777ad2 | 645 | dev_err(dev, "Can't get IRQ %d !\n", iface->irq); |
958585f5 MH |
646 | return -ENODEV; |
647 | } | |
648 | ||
649 | /* Resume TWI interface clock as specified */ | |
650 | write_CLKDIV(iface, iface->saved_clkdiv); | |
651 | ||
652 | /* Resume TWI */ | |
653 | write_CONTROL(iface, iface->saved_control); | |
d24ecfcc BW |
654 | |
655 | return 0; | |
656 | } | |
657 | ||
85777ad2 RW |
658 | static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm, |
659 | i2c_bfin_twi_suspend, i2c_bfin_twi_resume); | |
660 | ||
aa3d0209 | 661 | static int i2c_bfin_twi_probe(struct platform_device *pdev) |
d24ecfcc | 662 | { |
aa3d0209 | 663 | struct bfin_twi_iface *iface; |
d24ecfcc | 664 | struct i2c_adapter *p_adap; |
aa3d0209 | 665 | struct resource *res; |
d24ecfcc | 666 | int rc; |
9528d1c7 | 667 | unsigned int clkhilow; |
d24ecfcc | 668 | |
aa3d0209 BW |
669 | iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL); |
670 | if (!iface) { | |
671 | dev_err(&pdev->dev, "Cannot allocate memory\n"); | |
672 | rc = -ENOMEM; | |
673 | goto out_error_nomem; | |
674 | } | |
675 | ||
d24ecfcc | 676 | spin_lock_init(&(iface->lock)); |
aa3d0209 BW |
677 | |
678 | /* Find and map our resources */ | |
679 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
680 | if (res == NULL) { | |
681 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
682 | rc = -ENOENT; | |
683 | goto out_error_get_res; | |
684 | } | |
685 | ||
c6ffddea | 686 | iface->regs_base = ioremap(res->start, resource_size(res)); |
aa3d0209 BW |
687 | if (iface->regs_base == NULL) { |
688 | dev_err(&pdev->dev, "Cannot map IO\n"); | |
689 | rc = -ENXIO; | |
690 | goto out_error_ioremap; | |
691 | } | |
692 | ||
693 | iface->irq = platform_get_irq(pdev, 0); | |
694 | if (iface->irq < 0) { | |
695 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
696 | rc = -ENOENT; | |
697 | goto out_error_no_irq; | |
698 | } | |
d24ecfcc | 699 | |
d24ecfcc | 700 | p_adap = &iface->adap; |
aa3d0209 BW |
701 | p_adap->nr = pdev->id; |
702 | strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); | |
d24ecfcc BW |
703 | p_adap->algo = &bfin_twi_algorithm; |
704 | p_adap->algo_data = iface; | |
e1995f65 | 705 | p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
aa3d0209 | 706 | p_adap->dev.parent = &pdev->dev; |
dd7319a5 SZ |
707 | p_adap->timeout = 5 * HZ; |
708 | p_adap->retries = 3; | |
d24ecfcc | 709 | |
74d362e0 BW |
710 | rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi"); |
711 | if (rc) { | |
712 | dev_err(&pdev->dev, "Can't setup pin mux!\n"); | |
713 | goto out_error_pin_mux; | |
714 | } | |
715 | ||
d24ecfcc | 716 | rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
4311051c | 717 | 0, pdev->name, iface); |
d24ecfcc | 718 | if (rc) { |
aa3d0209 BW |
719 | dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); |
720 | rc = -ENODEV; | |
721 | goto out_error_req_irq; | |
d24ecfcc BW |
722 | } |
723 | ||
724 | /* Set TWI internal clock as 10MHz */ | |
ac07fb4d | 725 | write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F); |
d24ecfcc | 726 | |
9528d1c7 MH |
727 | /* |
728 | * We will not end up with a CLKDIV=0 because no one will specify | |
ac07fb4d | 729 | * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250) |
9528d1c7 | 730 | */ |
ac07fb4d | 731 | clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2; |
9528d1c7 | 732 | |
d24ecfcc | 733 | /* Set Twi interface clock as specified */ |
9528d1c7 | 734 | write_CLKDIV(iface, (clkhilow << 8) | clkhilow); |
d24ecfcc BW |
735 | |
736 | /* Enable TWI */ | |
aa3d0209 | 737 | write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); |
d24ecfcc BW |
738 | SSYNC(); |
739 | ||
991dee59 | 740 | rc = i2c_add_numbered_adapter(p_adap); |
aa3d0209 BW |
741 | if (rc < 0) { |
742 | dev_err(&pdev->dev, "Can't add i2c adapter!\n"); | |
743 | goto out_error_add_adapter; | |
744 | } | |
745 | ||
746 | platform_set_drvdata(pdev, iface); | |
d24ecfcc | 747 | |
fa6ad222 BW |
748 | dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, " |
749 | "regs_base@%p\n", iface->regs_base); | |
aa3d0209 BW |
750 | |
751 | return 0; | |
752 | ||
753 | out_error_add_adapter: | |
754 | free_irq(iface->irq, iface); | |
755 | out_error_req_irq: | |
756 | out_error_no_irq: | |
74d362e0 BW |
757 | peripheral_free_list(pin_req[pdev->id]); |
758 | out_error_pin_mux: | |
aa3d0209 BW |
759 | iounmap(iface->regs_base); |
760 | out_error_ioremap: | |
761 | out_error_get_res: | |
762 | kfree(iface); | |
763 | out_error_nomem: | |
d24ecfcc BW |
764 | return rc; |
765 | } | |
766 | ||
767 | static int i2c_bfin_twi_remove(struct platform_device *pdev) | |
768 | { | |
769 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); | |
770 | ||
771 | platform_set_drvdata(pdev, NULL); | |
772 | ||
773 | i2c_del_adapter(&(iface->adap)); | |
774 | free_irq(iface->irq, iface); | |
74d362e0 | 775 | peripheral_free_list(pin_req[pdev->id]); |
aa3d0209 BW |
776 | iounmap(iface->regs_base); |
777 | kfree(iface); | |
d24ecfcc BW |
778 | |
779 | return 0; | |
780 | } | |
781 | ||
782 | static struct platform_driver i2c_bfin_twi_driver = { | |
783 | .probe = i2c_bfin_twi_probe, | |
784 | .remove = i2c_bfin_twi_remove, | |
d24ecfcc BW |
785 | .driver = { |
786 | .name = "i2c-bfin-twi", | |
787 | .owner = THIS_MODULE, | |
85777ad2 | 788 | .pm = &i2c_bfin_twi_pm, |
d24ecfcc BW |
789 | }, |
790 | }; | |
791 | ||
792 | static int __init i2c_bfin_twi_init(void) | |
793 | { | |
d24ecfcc BW |
794 | return platform_driver_register(&i2c_bfin_twi_driver); |
795 | } | |
796 | ||
797 | static void __exit i2c_bfin_twi_exit(void) | |
798 | { | |
799 | platform_driver_unregister(&i2c_bfin_twi_driver); | |
800 | } | |
801 | ||
74f56c4a | 802 | subsys_initcall(i2c_bfin_twi_init); |
d24ecfcc | 803 | module_exit(i2c_bfin_twi_exit); |
fa6ad222 BW |
804 | |
805 | MODULE_AUTHOR("Bryan Wu, Sonic Zhang"); | |
806 | MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver"); | |
807 | MODULE_LICENSE("GPL"); | |
add8eda7 | 808 | MODULE_ALIAS("platform:i2c-bfin-twi"); |