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i2c-bfin-twi: Just let i2c-bfin-twi driver depends on BLACKFIN
[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
15#include <linux/mm.h>
16#include <linux/timer.h>
17#include <linux/spinlock.h>
18#include <linux/completion.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21
22#include <asm/blackfin.h>
74d362e0 23#include <asm/portmux.h>
d24ecfcc
BW		 24#include <asm/irq.h>
25
26#define POLL_TIMEOUT (2 * HZ)
27
28/* SMBus mode*/
4dd39bb1
SZ		 29#define TWI_I2C_MODE_STANDARD 1
30#define TWI_I2C_MODE_STANDARDSUB 2
31#define TWI_I2C_MODE_COMBINED 3
32#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 33
34struct bfin_twi_iface {
d24ecfcc
BW		 35 int irq;
36 spinlock_t lock;
37 char read_write;
38 u8 command;
39 u8 *transPtr;
40 int readNum;
41 int writeNum;
42 int cur_mode;
43 int manual_stop;
44 int result;
45 int timeout_count;
46 struct timer_list timeout_timer;
47 struct i2c_adapter adap;
48 struct completion complete;
4dd39bb1
SZ		 49 struct i2c_msg *pmsg;
50 int msg_num;
51 int cur_msg;
aa3d0209 52 void __iomem *regs_base;
d24ecfcc
BW		 53};
54
aa3d0209
BW		 55
56#define DEFINE_TWI_REG(reg, off) \
57static inline u16 read_##reg(struct bfin_twi_iface *iface) \
58 { return bfin_read16(iface->regs_base + (off)); } \
59static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
60 { bfin_write16(iface->regs_base + (off), v); }
61
62DEFINE_TWI_REG(CLKDIV, 0x00)
63DEFINE_TWI_REG(CONTROL, 0x04)
64DEFINE_TWI_REG(SLAVE_CTL, 0x08)
65DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
66DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
67DEFINE_TWI_REG(MASTER_CTL, 0x14)
68DEFINE_TWI_REG(MASTER_STAT, 0x18)
69DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
70DEFINE_TWI_REG(INT_STAT, 0x20)
71DEFINE_TWI_REG(INT_MASK, 0x24)
72DEFINE_TWI_REG(FIFO_CTL, 0x28)
73DEFINE_TWI_REG(FIFO_STAT, 0x2C)
74DEFINE_TWI_REG(XMT_DATA8, 0x80)
75DEFINE_TWI_REG(XMT_DATA16, 0x84)
76DEFINE_TWI_REG(RCV_DATA8, 0x88)
77DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 78
74d362e0
BW		 79static const u16 pin_req[2][3] = {
80 {P_TWI0_SCL, P_TWI0_SDA, 0},
81 {P_TWI1_SCL, P_TWI1_SDA, 0},
82};
83
d24ecfcc
BW		 84static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
85{
aa3d0209
BW		 86 unsigned short twi_int_status = read_INT_STAT(iface);
87 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 88
89 if (twi_int_status & XMTSERV) {
90 /* Transmit next data */
91 if (iface->writeNum > 0) {
aa3d0209 92 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 93 iface->writeNum--;
94 }
95 /* start receive immediately after complete sending in
96 * combine mode.
97 */
4dd39bb1 98 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209
BW		 99 write_MASTER_CTL(iface,
100 read_MASTER_CTL(iface) | MDIR | RSTART);
4dd39bb1 101 else if (iface->manual_stop)
aa3d0209
BW		 102 write_MASTER_CTL(iface,
103 read_MASTER_CTL(iface) | STOP);
4dd39bb1
SZ		 104 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
105 iface->cur_msg+1 < iface->msg_num)
aa3d0209
BW		 106 write_MASTER_CTL(iface,
107 read_MASTER_CTL(iface) | RSTART);
d24ecfcc
BW		 108 SSYNC();
109 /* Clear status */
aa3d0209 110 write_INT_STAT(iface, XMTSERV);
d24ecfcc
BW		 111 SSYNC();
112 }
113 if (twi_int_status & RCVSERV) {
114 if (iface->readNum > 0) {
115 /* Receive next data */
aa3d0209 116 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 117 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
118 /* Change combine mode into sub mode after
119 * read first data.
120 */
121 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
122 /* Get read number from first byte in block
123 * combine mode.
124 */
125 if (iface->readNum == 1 && iface->manual_stop)
126 iface->readNum = *iface->transPtr + 1;
127 }
128 iface->transPtr++;
129 iface->readNum--;
130 } else if (iface->manual_stop) {
aa3d0209
BW		 131 write_MASTER_CTL(iface,
132 read_MASTER_CTL(iface) | STOP);
d24ecfcc 133 SSYNC();
4dd39bb1
SZ		 134 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
135 iface->cur_msg+1 < iface->msg_num) {
aa3d0209
BW		 136 write_MASTER_CTL(iface,
137 read_MASTER_CTL(iface) | RSTART);
4dd39bb1 138 SSYNC();
d24ecfcc
BW		 139 }
140 /* Clear interrupt source */
aa3d0209 141 write_INT_STAT(iface, RCVSERV);
d24ecfcc
BW		 142 SSYNC();
143 }
144 if (twi_int_status & MERR) {
aa3d0209
BW		 145 write_INT_STAT(iface, MERR);
146 write_INT_MASK(iface, 0);
147 write_MASTER_STAT(iface, 0x3e);
148 write_MASTER_CTL(iface, 0);
d24ecfcc 149 SSYNC();
4dd39bb1 150 iface->result = -EIO;
d24ecfcc
BW		 151 /* if both err and complete int stats are set, return proper
152 * results.
153 */
154 if (twi_int_status & MCOMP) {
aa3d0209
BW		 155 write_INT_STAT(iface, MCOMP);
156 write_INT_MASK(iface, 0);
157 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 158 SSYNC();
159 /* If it is a quick transfer, only address bug no data,
160 * not an err, return 1.
161 */
162 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
163 iface->result = 1;
164 /* If address not acknowledged return -1,
165 * else return 0.
166 */
167 else if (!(mast_stat & ANAK))
168 iface->result = 0;
169 }
170 complete(&iface->complete);
171 return;
172 }
173 if (twi_int_status & MCOMP) {
aa3d0209 174 write_INT_STAT(iface, MCOMP);
d24ecfcc
BW		 175 SSYNC();
176 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
177 if (iface->readNum == 0) {
178 /* set the read number to 1 and ask for manual
179 * stop in block combine mode
180 */
181 iface->readNum = 1;
182 iface->manual_stop = 1;
aa3d0209
BW		 183 write_MASTER_CTL(iface,
184 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 185 } else {
186 /* set the readd number in other
187 * combine mode.
188 */
aa3d0209
BW		 189 write_MASTER_CTL(iface,
190 (read_MASTER_CTL(iface) &
d24ecfcc 191 (~(0xff << 6))) |
aa3d0209 192 (iface->readNum << 6));
d24ecfcc
BW		 193 }
194 /* remove restart bit and enable master receive */
aa3d0209
BW		 195 write_MASTER_CTL(iface,
196 read_MASTER_CTL(iface) & ~RSTART);
197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) | MEN | MDIR);
d24ecfcc 199 SSYNC();
4dd39bb1
SZ		 200 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
201 iface->cur_msg+1 < iface->msg_num) {
202 iface->cur_msg++;
203 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
204 iface->writeNum = iface->readNum =
205 iface->pmsg[iface->cur_msg].len;
206 /* Set Transmit device address */
aa3d0209 207 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 208 iface->pmsg[iface->cur_msg].addr);
209 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
210 iface->read_write = I2C_SMBUS_READ;
211 else {
212 iface->read_write = I2C_SMBUS_WRITE;
213 /* Transmit first data */
214 if (iface->writeNum > 0) {
aa3d0209 215 write_XMT_DATA8(iface,
4dd39bb1
SZ		 216 *(iface->transPtr++));
217 iface->writeNum--;
218 SSYNC();
219 }
220 }
221
222 if (iface->pmsg[iface->cur_msg].len <= 255)
aa3d0209 223 write_MASTER_CTL(iface,
4dd39bb1
SZ		 224 iface->pmsg[iface->cur_msg].len << 6);
225 else {
aa3d0209 226 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 227 iface->manual_stop = 1;
228 }
229 /* remove restart bit and enable master receive */
aa3d0209
BW		 230 write_MASTER_CTL(iface,
231 read_MASTER_CTL(iface) & ~RSTART);
232 write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
4dd39bb1
SZ		 233 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
234 MDIR : 0));
235 SSYNC();
d24ecfcc
BW		 236 } else {
237 iface->result = 1;
aa3d0209
BW		 238 write_INT_MASK(iface, 0);
239 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 240 SSYNC();
241 complete(&iface->complete);
242 }
243 }
244}
245
246/* Interrupt handler */
247static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
248{
249 struct bfin_twi_iface *iface = dev_id;
250 unsigned long flags;
251
252 spin_lock_irqsave(&iface->lock, flags);
253 del_timer(&iface->timeout_timer);
254 bfin_twi_handle_interrupt(iface);
255 spin_unlock_irqrestore(&iface->lock, flags);
256 return IRQ_HANDLED;
257}
258
259static void bfin_twi_timeout(unsigned long data)
260{
261 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
262 unsigned long flags;
263
264 spin_lock_irqsave(&iface->lock, flags);
265 bfin_twi_handle_interrupt(iface);
266 if (iface->result == 0) {
267 iface->timeout_count--;
268 if (iface->timeout_count > 0) {
269 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
270 add_timer(&iface->timeout_timer);
271 } else {
272 iface->result = -1;
273 complete(&iface->complete);
274 }
275 }
276 spin_unlock_irqrestore(&iface->lock, flags);
277}
278
279/*
280 * Generic i2c master transfer entrypoint
281 */
282static int bfin_twi_master_xfer(struct i2c_adapter *adap,
283 struct i2c_msg *msgs, int num)
284{
285 struct bfin_twi_iface *iface = adap->algo_data;
286 struct i2c_msg *pmsg;
d24ecfcc
BW		 287 int rc = 0;
288
aa3d0209 289 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 290 return -ENXIO;
291
aa3d0209 292 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 293 yield();
d24ecfcc 294
4dd39bb1
SZ		 295 iface->pmsg = msgs;
296 iface->msg_num = num;
297 iface->cur_msg = 0;
d24ecfcc 298
4dd39bb1
SZ		 299 pmsg = &msgs[0];
300 if (pmsg->flags & I2C_M_TEN) {
301 dev_err(&adap->dev, "10 bits addr not supported!\n");
302 return -EINVAL;
303 }
d24ecfcc 304
4dd39bb1
SZ		 305 iface->cur_mode = TWI_I2C_MODE_REPEAT;
306 iface->manual_stop = 0;
307 iface->transPtr = pmsg->buf;
308 iface->writeNum = iface->readNum = pmsg->len;
309 iface->result = 0;
310 iface->timeout_count = 10;
311 /* Set Transmit device address */
aa3d0209 312 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 313
314 /* FIFO Initiation. Data in FIFO should be
315 * discarded before start a new operation.
316 */
aa3d0209 317 write_FIFO_CTL(iface, 0x3);
4dd39bb1 318 SSYNC();
aa3d0209 319 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 320 SSYNC();
321
322 if (pmsg->flags & I2C_M_RD)
323 iface->read_write = I2C_SMBUS_READ;
324 else {
325 iface->read_write = I2C_SMBUS_WRITE;
326 /* Transmit first data */
327 if (iface->writeNum > 0) {
aa3d0209 328 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 329 iface->writeNum--;
330 SSYNC();
d24ecfcc 331 }
4dd39bb1 332 }
d24ecfcc 333
4dd39bb1 334 /* clear int stat */
aa3d0209 335 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 336
4dd39bb1 337 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 338 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 339 SSYNC();
d24ecfcc 340
4dd39bb1 341 if (pmsg->len <= 255)
aa3d0209 342 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 343 else {
aa3d0209 344 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 345 iface->manual_stop = 1;
346 }
d24ecfcc 347
4dd39bb1
SZ		 348 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
349 add_timer(&iface->timeout_timer);
d24ecfcc 350
4dd39bb1 351 /* Master enable */
aa3d0209 352 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
4dd39bb1
SZ		 353 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
354 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
355 SSYNC();
356
357 wait_for_completion(&iface->complete);
358
359 rc = iface->result;
d24ecfcc 360
4dd39bb1
SZ		 361 if (rc == 1)
362 return num;
363 else
364 return rc;
d24ecfcc
BW		 365}
366
367/*
368 * SMBus type transfer entrypoint
369 */
370
371int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
372 unsigned short flags, char read_write,
373 u8 command, int size, union i2c_smbus_data *data)
374{
375 struct bfin_twi_iface *iface = adap->algo_data;
376 int rc = 0;
377
aa3d0209 378 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 379 return -ENXIO;
380
aa3d0209 381 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 382 yield();
d24ecfcc
BW		 383
384 iface->writeNum = 0;
385 iface->readNum = 0;
386
387 /* Prepare datas & select mode */
388 switch (size) {
389 case I2C_SMBUS_QUICK:
390 iface->transPtr = NULL;
391 iface->cur_mode = TWI_I2C_MODE_STANDARD;
392 break;
393 case I2C_SMBUS_BYTE:
394 if (data == NULL)
395 iface->transPtr = NULL;
396 else {
397 if (read_write == I2C_SMBUS_READ)
398 iface->readNum = 1;
399 else
400 iface->writeNum = 1;
401 iface->transPtr = &data->byte;
402 }
403 iface->cur_mode = TWI_I2C_MODE_STANDARD;
404 break;
405 case I2C_SMBUS_BYTE_DATA:
406 if (read_write == I2C_SMBUS_READ) {
407 iface->readNum = 1;
408 iface->cur_mode = TWI_I2C_MODE_COMBINED;
409 } else {
410 iface->writeNum = 1;
411 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
412 }
413 iface->transPtr = &data->byte;
414 break;
415 case I2C_SMBUS_WORD_DATA:
416 if (read_write == I2C_SMBUS_READ) {
417 iface->readNum = 2;
418 iface->cur_mode = TWI_I2C_MODE_COMBINED;
419 } else {
420 iface->writeNum = 2;
421 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
422 }
423 iface->transPtr = (u8 *)&data->word;
424 break;
425 case I2C_SMBUS_PROC_CALL:
426 iface->writeNum = 2;
427 iface->readNum = 2;
428 iface->cur_mode = TWI_I2C_MODE_COMBINED;
429 iface->transPtr = (u8 *)&data->word;
430 break;
431 case I2C_SMBUS_BLOCK_DATA:
432 if (read_write == I2C_SMBUS_READ) {
433 iface->readNum = 0;
434 iface->cur_mode = TWI_I2C_MODE_COMBINED;
435 } else {
436 iface->writeNum = data->block[0] + 1;
437 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
438 }
439 iface->transPtr = data->block;
440 break;
441 default:
442 return -1;
443 }
444
445 iface->result = 0;
446 iface->manual_stop = 0;
447 iface->read_write = read_write;
448 iface->command = command;
449 iface->timeout_count = 10;
450
451 /* FIFO Initiation. Data in FIFO should be discarded before
452 * start a new operation.
453 */
aa3d0209 454 write_FIFO_CTL(iface, 0x3);
d24ecfcc 455 SSYNC();
aa3d0209 456 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 457
458 /* clear int stat */
aa3d0209 459 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 460
461 /* Set Transmit device address */
aa3d0209 462 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 463 SSYNC();
464
465 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
466 add_timer(&iface->timeout_timer);
467
468 switch (iface->cur_mode) {
469 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 470 write_XMT_DATA8(iface, iface->command);
471 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 472 ((iface->read_write == I2C_SMBUS_READ) ?
473 RCVSERV : XMTSERV));
474 SSYNC();
475
476 if (iface->writeNum + 1 <= 255)
aa3d0209 477 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 478 else {
aa3d0209 479 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 480 iface->manual_stop = 1;
481 }
482 /* Master enable */
aa3d0209 483 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 484 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
485 break;
486 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 487 write_XMT_DATA8(iface, iface->command);
488 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 489 SSYNC();
490
491 if (iface->writeNum > 0)
aa3d0209 492 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 493 else
aa3d0209 494 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 495 /* Master enable */
aa3d0209 496 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 497 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
498 break;
499 default:
aa3d0209 500 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 501 if (size != I2C_SMBUS_QUICK) {
502 /* Don't access xmit data register when this is a
503 * read operation.
504 */
505 if (iface->read_write != I2C_SMBUS_READ) {
506 if (iface->writeNum > 0) {
aa3d0209
BW		 507 write_XMT_DATA8(iface,
508 *(iface->transPtr++));
d24ecfcc 509 if (iface->writeNum <= 255)
aa3d0209
BW		 510 write_MASTER_CTL(iface,
511 iface->writeNum << 6);
d24ecfcc 512 else {
aa3d0209
BW		 513 write_MASTER_CTL(iface,
514 0xff << 6);
d24ecfcc
BW		 515 iface->manual_stop = 1;
516 }
517 iface->writeNum--;
518 } else {
aa3d0209
BW		 519 write_XMT_DATA8(iface, iface->command);
520 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 521 }
522 } else {
523 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 524 write_MASTER_CTL(iface,
525 iface->readNum << 6);
d24ecfcc 526 else if (iface->readNum > 255) {
aa3d0209 527 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 528 iface->manual_stop = 1;
529 } else {
530 del_timer(&iface->timeout_timer);
531 break;
532 }
533 }
534 }
aa3d0209 535 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 536 ((iface->read_write == I2C_SMBUS_READ) ?
537 RCVSERV : XMTSERV));
538 SSYNC();
539
540 /* Master enable */
aa3d0209 541 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 542 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
543 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
544 break;
545 }
546 SSYNC();
547
548 wait_for_completion(&iface->complete);
549
550 rc = (iface->result >= 0) ? 0 : -1;
551
d24ecfcc
BW		 552 return rc;
553}
554
555/*
556 * Return what the adapter supports
557 */
558static u32 bfin_twi_functionality(struct i2c_adapter *adap)
559{
560 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
561 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
562 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
563 I2C_FUNC_I2C;
564}
565
566
567static struct i2c_algorithm bfin_twi_algorithm = {
568 .master_xfer = bfin_twi_master_xfer,
569 .smbus_xfer = bfin_twi_smbus_xfer,
570 .functionality = bfin_twi_functionality,
571};
572
573
574static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
575{
aa3d0209 576 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
d24ecfcc
BW		 577
578 /* Disable TWI */
aa3d0209 579 write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
d24ecfcc
BW		 580 SSYNC();
581
582 return 0;
583}
584
585static int i2c_bfin_twi_resume(struct platform_device *dev)
586{
aa3d0209 587 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
d24ecfcc
BW		 588
589 /* Enable TWI */
aa3d0209 590 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 591 SSYNC();
592
593 return 0;
594}
595
aa3d0209 596static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 597{
aa3d0209 598 struct bfin_twi_iface *iface;
d24ecfcc 599 struct i2c_adapter *p_adap;
aa3d0209 600 struct resource *res;
d24ecfcc
BW		 601 int rc;
602
aa3d0209
BW		 603 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
604 if (!iface) {
605 dev_err(&pdev->dev, "Cannot allocate memory\n");
606 rc = -ENOMEM;
607 goto out_error_nomem;
608 }
609
d24ecfcc
BW		 610 spin_lock_init(&(iface->lock));
611 init_completion(&(iface->complete));
aa3d0209
BW		 612
613 /* Find and map our resources */
614 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
615 if (res == NULL) {
616 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
617 rc = -ENOENT;
618 goto out_error_get_res;
619 }
620
621 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
622 if (iface->regs_base == NULL) {
623 dev_err(&pdev->dev, "Cannot map IO\n");
624 rc = -ENXIO;
625 goto out_error_ioremap;
626 }
627
628 iface->irq = platform_get_irq(pdev, 0);
629 if (iface->irq < 0) {
630 dev_err(&pdev->dev, "No IRQ specified\n");
631 rc = -ENOENT;
632 goto out_error_no_irq;
633 }
d24ecfcc
BW		 634
635 init_timer(&(iface->timeout_timer));
636 iface->timeout_timer.function = bfin_twi_timeout;
637 iface->timeout_timer.data = (unsigned long)iface;
638
639 p_adap = &iface->adap;
640 p_adap->id = I2C_HW_BLACKFIN;
aa3d0209
BW		 641 p_adap->nr = pdev->id;
642 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 643 p_adap->algo = &bfin_twi_algorithm;
644 p_adap->algo_data = iface;
645 p_adap->class = I2C_CLASS_ALL;
aa3d0209 646 p_adap->dev.parent = &pdev->dev;
d24ecfcc 647
74d362e0
BW		 648 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
649 if (rc) {
650 dev_err(&pdev->dev, "Can't setup pin mux!\n");
651 goto out_error_pin_mux;
652 }
653
d24ecfcc 654 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
aa3d0209 655 IRQF_DISABLED, pdev->name, iface);
d24ecfcc 656 if (rc) {
aa3d0209
BW		 657 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
658 rc = -ENODEV;
659 goto out_error_req_irq;
d24ecfcc
BW		 660 }
661
662 /* Set TWI internal clock as 10MHz */
aa3d0209 663 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
d24ecfcc
BW		 664
665 /* Set Twi interface clock as specified */
aa3d0209
BW		 666 write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
667 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
d24ecfcc
BW		 668 & 0xFF));
669
670 /* Enable TWI */
aa3d0209 671 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 672 SSYNC();
673
991dee59 674 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 675 if (rc < 0) {
676 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
677 goto out_error_add_adapter;
678 }
679
680 platform_set_drvdata(pdev, iface);
d24ecfcc 681
fa6ad222
BW		 682 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
683 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 684
685 return 0;
686
687out_error_add_adapter:
688 free_irq(iface->irq, iface);
689out_error_req_irq:
690out_error_no_irq:
74d362e0
BW		 691 peripheral_free_list(pin_req[pdev->id]);
692out_error_pin_mux:
aa3d0209
BW		 693 iounmap(iface->regs_base);
694out_error_ioremap:
695out_error_get_res:
696 kfree(iface);
697out_error_nomem:
d24ecfcc
BW		 698 return rc;
699}
700
701static int i2c_bfin_twi_remove(struct platform_device *pdev)
702{
703 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
704
705 platform_set_drvdata(pdev, NULL);
706
707 i2c_del_adapter(&(iface->adap));
708 free_irq(iface->irq, iface);
74d362e0 709 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 710 iounmap(iface->regs_base);
711 kfree(iface);
d24ecfcc
BW		 712
713 return 0;
714}
715
716static struct platform_driver i2c_bfin_twi_driver = {
717 .probe = i2c_bfin_twi_probe,
718 .remove = i2c_bfin_twi_remove,
719 .suspend = i2c_bfin_twi_suspend,
720 .resume = i2c_bfin_twi_resume,
721 .driver = {
722 .name = "i2c-bfin-twi",
723 .owner = THIS_MODULE,
724 },
725};
726
727static int __init i2c_bfin_twi_init(void)
728{
d24ecfcc
BW		 729 return platform_driver_register(&i2c_bfin_twi_driver);
730}
731
732static void __exit i2c_bfin_twi_exit(void)
733{
734 platform_driver_unregister(&i2c_bfin_twi_driver);
735}
736
d24ecfcc
BW		 737module_init(i2c_bfin_twi_init);
738module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 739
740MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
741MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
742MODULE_LICENSE("GPL");
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