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95a7f10e VB |
1 | /* |
2 | * TI DAVINCI I2C adapter driver. | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * Copyright (C) 2007 MontaVista Software Inc. | |
6 | * | |
7 | * Updated by Vinod & Sudhakar Feb 2005 | |
8 | * | |
9 | * ---------------------------------------------------------------------------- | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * ---------------------------------------------------------------------------- | |
25 | * | |
26 | */ | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/i2c.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/io.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
95a7f10e | 39 | |
a09e64fb | 40 | #include <mach/hardware.h> |
95a7f10e | 41 | |
a09e64fb | 42 | #include <mach/i2c.h> |
95a7f10e VB |
43 | |
44 | /* ----- global defines ----------------------------------------------- */ | |
45 | ||
46 | #define DAVINCI_I2C_TIMEOUT (1*HZ) | |
47 | #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ | |
48 | DAVINCI_I2C_IMR_SCD | \ | |
49 | DAVINCI_I2C_IMR_ARDY | \ | |
50 | DAVINCI_I2C_IMR_NACK | \ | |
51 | DAVINCI_I2C_IMR_AL) | |
52 | ||
53 | #define DAVINCI_I2C_OAR_REG 0x00 | |
54 | #define DAVINCI_I2C_IMR_REG 0x04 | |
55 | #define DAVINCI_I2C_STR_REG 0x08 | |
56 | #define DAVINCI_I2C_CLKL_REG 0x0c | |
57 | #define DAVINCI_I2C_CLKH_REG 0x10 | |
58 | #define DAVINCI_I2C_CNT_REG 0x14 | |
59 | #define DAVINCI_I2C_DRR_REG 0x18 | |
60 | #define DAVINCI_I2C_SAR_REG 0x1c | |
61 | #define DAVINCI_I2C_DXR_REG 0x20 | |
62 | #define DAVINCI_I2C_MDR_REG 0x24 | |
63 | #define DAVINCI_I2C_IVR_REG 0x28 | |
64 | #define DAVINCI_I2C_EMDR_REG 0x2c | |
65 | #define DAVINCI_I2C_PSC_REG 0x30 | |
66 | ||
67 | #define DAVINCI_I2C_IVR_AAS 0x07 | |
68 | #define DAVINCI_I2C_IVR_SCD 0x06 | |
69 | #define DAVINCI_I2C_IVR_XRDY 0x05 | |
70 | #define DAVINCI_I2C_IVR_RDR 0x04 | |
71 | #define DAVINCI_I2C_IVR_ARDY 0x03 | |
72 | #define DAVINCI_I2C_IVR_NACK 0x02 | |
73 | #define DAVINCI_I2C_IVR_AL 0x01 | |
74 | ||
75 | #define DAVINCI_I2C_STR_BB (1 << 12) | |
76 | #define DAVINCI_I2C_STR_RSFULL (1 << 11) | |
77 | #define DAVINCI_I2C_STR_SCD (1 << 5) | |
78 | #define DAVINCI_I2C_STR_ARDY (1 << 2) | |
79 | #define DAVINCI_I2C_STR_NACK (1 << 1) | |
80 | #define DAVINCI_I2C_STR_AL (1 << 0) | |
81 | ||
82 | #define DAVINCI_I2C_MDR_NACK (1 << 15) | |
83 | #define DAVINCI_I2C_MDR_STT (1 << 13) | |
84 | #define DAVINCI_I2C_MDR_STP (1 << 11) | |
85 | #define DAVINCI_I2C_MDR_MST (1 << 10) | |
86 | #define DAVINCI_I2C_MDR_TRX (1 << 9) | |
87 | #define DAVINCI_I2C_MDR_XA (1 << 8) | |
5a0d5f5f | 88 | #define DAVINCI_I2C_MDR_RM (1 << 7) |
95a7f10e VB |
89 | #define DAVINCI_I2C_MDR_IRS (1 << 5) |
90 | ||
91 | #define DAVINCI_I2C_IMR_AAS (1 << 6) | |
92 | #define DAVINCI_I2C_IMR_SCD (1 << 5) | |
93 | #define DAVINCI_I2C_IMR_XRDY (1 << 4) | |
94 | #define DAVINCI_I2C_IMR_RRDY (1 << 3) | |
95 | #define DAVINCI_I2C_IMR_ARDY (1 << 2) | |
96 | #define DAVINCI_I2C_IMR_NACK (1 << 1) | |
97 | #define DAVINCI_I2C_IMR_AL (1 << 0) | |
98 | ||
99 | #define MOD_REG_BIT(val, mask, set) do { \ | |
100 | if (set) { \ | |
101 | val |= mask; \ | |
102 | } else { \ | |
103 | val &= ~mask; \ | |
104 | } \ | |
105 | } while (0) | |
106 | ||
107 | struct davinci_i2c_dev { | |
108 | struct device *dev; | |
109 | void __iomem *base; | |
110 | struct completion cmd_complete; | |
111 | struct clk *clk; | |
112 | int cmd_err; | |
113 | u8 *buf; | |
114 | size_t buf_len; | |
115 | int irq; | |
c6c7c729 | 116 | int stop; |
5a0d5f5f | 117 | u8 terminate; |
95a7f10e VB |
118 | struct i2c_adapter adapter; |
119 | }; | |
120 | ||
121 | /* default platform data to use if not supplied in the platform_device */ | |
122 | static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { | |
123 | .bus_freq = 100, | |
124 | .bus_delay = 0, | |
125 | }; | |
126 | ||
127 | static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, | |
128 | int reg, u16 val) | |
129 | { | |
130 | __raw_writew(val, i2c_dev->base + reg); | |
131 | } | |
132 | ||
133 | static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) | |
134 | { | |
135 | return __raw_readw(i2c_dev->base + reg); | |
136 | } | |
137 | ||
138 | /* | |
139 | * This functions configures I2C and brings I2C out of reset. | |
140 | * This function is called during I2C init function. This function | |
141 | * also gets called if I2C encounters any errors. | |
142 | */ | |
143 | static int i2c_davinci_init(struct davinci_i2c_dev *dev) | |
144 | { | |
145 | struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; | |
146 | u16 psc; | |
147 | u32 clk; | |
cc99ff70 | 148 | u32 d; |
95a7f10e VB |
149 | u32 clkh; |
150 | u32 clkl; | |
151 | u32 input_clock = clk_get_rate(dev->clk); | |
152 | u16 w; | |
153 | ||
154 | if (!pdata) | |
155 | pdata = &davinci_i2c_platform_data_default; | |
156 | ||
157 | /* put I2C into reset */ | |
158 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | |
159 | MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0); | |
160 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | |
161 | ||
162 | /* NOTE: I2C Clock divider programming info | |
163 | * As per I2C specs the following formulas provide prescaler | |
164 | * and low/high divider values | |
165 | * input clk --> PSC Div -----------> ICCL/H Div --> output clock | |
166 | * module clk | |
167 | * | |
168 | * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] | |
169 | * | |
170 | * Thus, | |
171 | * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; | |
172 | * | |
173 | * where if PSC == 0, d = 7, | |
174 | * if PSC == 1, d = 6 | |
175 | * if PSC > 1 , d = 5 | |
176 | */ | |
177 | ||
cc99ff70 TK |
178 | /* get minimum of 7 MHz clock, but max of 12 MHz */ |
179 | psc = (input_clock / 7000000) - 1; | |
180 | if ((input_clock / (psc + 1)) > 12000000) | |
181 | psc++; /* better to run under spec than over */ | |
182 | d = (psc >= 2) ? 5 : 7 - psc; | |
95a7f10e | 183 | |
cc99ff70 TK |
184 | clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); |
185 | clkh = clk >> 1; | |
95a7f10e VB |
186 | clkl = clk - clkh; |
187 | ||
188 | davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); | |
189 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); | |
190 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); | |
191 | ||
7605fa3b DB |
192 | /* Respond at reserved "SMBus Host" slave address" (and zero); |
193 | * we seem to have no option to not respond... | |
194 | */ | |
195 | davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); | |
196 | ||
cc99ff70 | 197 | dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); |
95a7f10e VB |
198 | dev_dbg(dev->dev, "PSC = %d\n", |
199 | davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); | |
200 | dev_dbg(dev->dev, "CLKL = %d\n", | |
201 | davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); | |
202 | dev_dbg(dev->dev, "CLKH = %d\n", | |
203 | davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); | |
cc99ff70 TK |
204 | dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", |
205 | pdata->bus_freq, pdata->bus_delay); | |
95a7f10e VB |
206 | |
207 | /* Take the I2C module out of reset: */ | |
208 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | |
209 | MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1); | |
210 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | |
211 | ||
212 | /* Enable interrupts */ | |
213 | davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | /* | |
219 | * Waiting for bus not busy | |
220 | */ | |
221 | static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, | |
222 | char allow_sleep) | |
223 | { | |
224 | unsigned long timeout; | |
225 | ||
98a679ca | 226 | timeout = jiffies + dev->adapter.timeout; |
95a7f10e VB |
227 | while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) |
228 | & DAVINCI_I2C_STR_BB) { | |
229 | if (time_after(jiffies, timeout)) { | |
230 | dev_warn(dev->dev, | |
231 | "timeout waiting for bus ready\n"); | |
232 | return -ETIMEDOUT; | |
233 | } | |
234 | if (allow_sleep) | |
235 | schedule_timeout(1); | |
236 | } | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
241 | /* | |
242 | * Low level master read/write transaction. This function is called | |
243 | * from i2c_davinci_xfer. | |
244 | */ | |
245 | static int | |
246 | i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) | |
247 | { | |
248 | struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); | |
249 | struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; | |
250 | u32 flag; | |
95a7f10e VB |
251 | u16 w; |
252 | int r; | |
253 | ||
95a7f10e VB |
254 | if (!pdata) |
255 | pdata = &davinci_i2c_platform_data_default; | |
256 | /* Introduce a delay, required for some boards (e.g Davinci EVM) */ | |
257 | if (pdata->bus_delay) | |
258 | udelay(pdata->bus_delay); | |
259 | ||
260 | /* set the slave address */ | |
261 | davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); | |
262 | ||
263 | dev->buf = msg->buf; | |
264 | dev->buf_len = msg->len; | |
c6c7c729 | 265 | dev->stop = stop; |
95a7f10e VB |
266 | |
267 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); | |
268 | ||
2e743787 | 269 | INIT_COMPLETION(dev->cmd_complete); |
95a7f10e VB |
270 | dev->cmd_err = 0; |
271 | ||
95a7f10e VB |
272 | /* Take I2C out of reset, configure it as master and set the |
273 | * start bit */ | |
274 | flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT; | |
275 | ||
276 | /* if the slave address is ten bit address, enable XA bit */ | |
277 | if (msg->flags & I2C_M_TEN) | |
278 | flag |= DAVINCI_I2C_MDR_XA; | |
279 | if (!(msg->flags & I2C_M_RD)) | |
280 | flag |= DAVINCI_I2C_MDR_TRX; | |
281 | if (stop) | |
282 | flag |= DAVINCI_I2C_MDR_STP; | |
c6c7c729 DB |
283 | if (msg->len == 0) { |
284 | flag |= DAVINCI_I2C_MDR_RM; | |
285 | flag &= ~DAVINCI_I2C_MDR_STP; | |
286 | } | |
95a7f10e VB |
287 | |
288 | /* Enable receive or transmit interrupts */ | |
289 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); | |
290 | if (msg->flags & I2C_M_RD) | |
291 | MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1); | |
292 | else | |
293 | MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1); | |
294 | davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); | |
295 | ||
5a0d5f5f | 296 | dev->terminate = 0; |
c6c7c729 | 297 | |
95a7f10e VB |
298 | /* write the data into mode register */ |
299 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); | |
300 | ||
c6c7c729 DB |
301 | /* |
302 | * First byte should be set here, not after interrupt, | |
303 | * because transmit-data-ready interrupt can come before | |
304 | * NACK-interrupt during sending of previous message and | |
305 | * ICDXR may have wrong data | |
306 | */ | |
307 | if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { | |
308 | davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); | |
309 | dev->buf_len--; | |
310 | } | |
311 | ||
95a7f10e | 312 | r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, |
98a679ca | 313 | dev->adapter.timeout); |
95a7f10e VB |
314 | if (r == 0) { |
315 | dev_err(dev->dev, "controller timed out\n"); | |
316 | i2c_davinci_init(dev); | |
5a0d5f5f | 317 | dev->buf_len = 0; |
95a7f10e VB |
318 | return -ETIMEDOUT; |
319 | } | |
5a0d5f5f TK |
320 | if (dev->buf_len) { |
321 | /* This should be 0 if all bytes were transferred | |
322 | * or dev->cmd_err denotes an error. | |
323 | * A signal may have aborted the transfer. | |
324 | */ | |
325 | if (r >= 0) { | |
326 | dev_err(dev->dev, "abnormal termination buf_len=%i\n", | |
327 | dev->buf_len); | |
328 | r = -EREMOTEIO; | |
329 | } | |
330 | dev->terminate = 1; | |
331 | wmb(); | |
332 | dev->buf_len = 0; | |
333 | } | |
334 | if (r < 0) | |
335 | return r; | |
95a7f10e VB |
336 | |
337 | /* no error */ | |
338 | if (likely(!dev->cmd_err)) | |
339 | return msg->len; | |
340 | ||
341 | /* We have an error */ | |
342 | if (dev->cmd_err & DAVINCI_I2C_STR_AL) { | |
343 | i2c_davinci_init(dev); | |
344 | return -EIO; | |
345 | } | |
346 | ||
347 | if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { | |
348 | if (msg->flags & I2C_M_IGNORE_NAK) | |
349 | return msg->len; | |
350 | if (stop) { | |
351 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | |
352 | MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1); | |
353 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | |
354 | } | |
355 | return -EREMOTEIO; | |
356 | } | |
357 | return -EIO; | |
358 | } | |
359 | ||
360 | /* | |
361 | * Prepare controller for a transaction and call i2c_davinci_xfer_msg | |
362 | */ | |
363 | static int | |
364 | i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
365 | { | |
366 | struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); | |
367 | int i; | |
368 | int ret; | |
369 | ||
08882d20 | 370 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
95a7f10e VB |
371 | |
372 | ret = i2c_davinci_wait_bus_not_busy(dev, 1); | |
373 | if (ret < 0) { | |
374 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
375 | return ret; | |
376 | } | |
377 | ||
378 | for (i = 0; i < num; i++) { | |
379 | ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
d868caa1 TK |
380 | dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, |
381 | ret); | |
95a7f10e VB |
382 | if (ret < 0) |
383 | return ret; | |
384 | } | |
95a7f10e VB |
385 | return num; |
386 | } | |
387 | ||
388 | static u32 i2c_davinci_func(struct i2c_adapter *adap) | |
389 | { | |
c6c7c729 | 390 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
95a7f10e VB |
391 | } |
392 | ||
5a0d5f5f TK |
393 | static void terminate_read(struct davinci_i2c_dev *dev) |
394 | { | |
395 | u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | |
396 | w |= DAVINCI_I2C_MDR_NACK; | |
397 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | |
398 | ||
399 | /* Throw away data */ | |
400 | davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); | |
401 | if (!dev->terminate) | |
402 | dev_err(dev->dev, "RDR IRQ while no data requested\n"); | |
403 | } | |
404 | static void terminate_write(struct davinci_i2c_dev *dev) | |
405 | { | |
406 | u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | |
407 | w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; | |
408 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | |
409 | ||
410 | if (!dev->terminate) | |
7605fa3b | 411 | dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); |
5a0d5f5f TK |
412 | } |
413 | ||
95a7f10e VB |
414 | /* |
415 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
416 | * occurs. | |
417 | */ | |
418 | static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) | |
419 | { | |
420 | struct davinci_i2c_dev *dev = dev_id; | |
421 | u32 stat; | |
422 | int count = 0; | |
423 | u16 w; | |
424 | ||
425 | while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { | |
08882d20 | 426 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
95a7f10e VB |
427 | if (count++ == 100) { |
428 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
429 | break; | |
430 | } | |
431 | ||
432 | switch (stat) { | |
433 | case DAVINCI_I2C_IVR_AL: | |
5a0d5f5f | 434 | /* Arbitration lost, must retry */ |
95a7f10e | 435 | dev->cmd_err |= DAVINCI_I2C_STR_AL; |
5a0d5f5f | 436 | dev->buf_len = 0; |
95a7f10e VB |
437 | complete(&dev->cmd_complete); |
438 | break; | |
439 | ||
440 | case DAVINCI_I2C_IVR_NACK: | |
441 | dev->cmd_err |= DAVINCI_I2C_STR_NACK; | |
5a0d5f5f | 442 | dev->buf_len = 0; |
95a7f10e VB |
443 | complete(&dev->cmd_complete); |
444 | break; | |
445 | ||
446 | case DAVINCI_I2C_IVR_ARDY: | |
b73a9aec TK |
447 | davinci_i2c_write_reg(dev, |
448 | DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); | |
c6c7c729 DB |
449 | if (((dev->buf_len == 0) && (dev->stop != 0)) || |
450 | (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { | |
451 | w = davinci_i2c_read_reg(dev, | |
452 | DAVINCI_I2C_MDR_REG); | |
453 | w |= DAVINCI_I2C_MDR_STP; | |
454 | davinci_i2c_write_reg(dev, | |
455 | DAVINCI_I2C_MDR_REG, w); | |
456 | } | |
95a7f10e VB |
457 | complete(&dev->cmd_complete); |
458 | break; | |
459 | ||
460 | case DAVINCI_I2C_IVR_RDR: | |
461 | if (dev->buf_len) { | |
462 | *dev->buf++ = | |
463 | davinci_i2c_read_reg(dev, | |
464 | DAVINCI_I2C_DRR_REG); | |
465 | dev->buf_len--; | |
466 | if (dev->buf_len) | |
467 | continue; | |
468 | ||
95a7f10e | 469 | davinci_i2c_write_reg(dev, |
b73a9aec TK |
470 | DAVINCI_I2C_STR_REG, |
471 | DAVINCI_I2C_IMR_RRDY); | |
5a0d5f5f TK |
472 | } else { |
473 | /* signal can terminate transfer */ | |
474 | terminate_read(dev); | |
475 | } | |
95a7f10e VB |
476 | break; |
477 | ||
478 | case DAVINCI_I2C_IVR_XRDY: | |
479 | if (dev->buf_len) { | |
480 | davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, | |
481 | *dev->buf++); | |
482 | dev->buf_len--; | |
483 | if (dev->buf_len) | |
484 | continue; | |
485 | ||
486 | w = davinci_i2c_read_reg(dev, | |
487 | DAVINCI_I2C_IMR_REG); | |
488 | MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0); | |
489 | davinci_i2c_write_reg(dev, | |
490 | DAVINCI_I2C_IMR_REG, | |
491 | w); | |
5a0d5f5f TK |
492 | } else { |
493 | /* signal can terminate transfer */ | |
494 | terminate_write(dev); | |
495 | } | |
95a7f10e VB |
496 | break; |
497 | ||
498 | case DAVINCI_I2C_IVR_SCD: | |
b73a9aec TK |
499 | davinci_i2c_write_reg(dev, |
500 | DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); | |
95a7f10e VB |
501 | complete(&dev->cmd_complete); |
502 | break; | |
503 | ||
504 | case DAVINCI_I2C_IVR_AAS: | |
7605fa3b DB |
505 | dev_dbg(dev->dev, "Address as slave interrupt\n"); |
506 | break; | |
507 | ||
508 | default: | |
509 | dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); | |
510 | break; | |
511 | } | |
512 | } | |
95a7f10e VB |
513 | |
514 | return count ? IRQ_HANDLED : IRQ_NONE; | |
515 | } | |
516 | ||
517 | static struct i2c_algorithm i2c_davinci_algo = { | |
518 | .master_xfer = i2c_davinci_xfer, | |
519 | .functionality = i2c_davinci_func, | |
520 | }; | |
521 | ||
522 | static int davinci_i2c_probe(struct platform_device *pdev) | |
523 | { | |
524 | struct davinci_i2c_dev *dev; | |
525 | struct i2c_adapter *adap; | |
526 | struct resource *mem, *irq, *ioarea; | |
527 | int r; | |
528 | ||
529 | /* NOTE: driver uses the static register mapping */ | |
530 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
531 | if (!mem) { | |
532 | dev_err(&pdev->dev, "no mem resource?\n"); | |
533 | return -ENODEV; | |
534 | } | |
535 | ||
536 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
537 | if (!irq) { | |
538 | dev_err(&pdev->dev, "no irq resource?\n"); | |
539 | return -ENODEV; | |
540 | } | |
541 | ||
59330825 | 542 | ioarea = request_mem_region(mem->start, resource_size(mem), |
95a7f10e VB |
543 | pdev->name); |
544 | if (!ioarea) { | |
545 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
546 | return -EBUSY; | |
547 | } | |
548 | ||
549 | dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL); | |
550 | if (!dev) { | |
551 | r = -ENOMEM; | |
552 | goto err_release_region; | |
553 | } | |
554 | ||
2e743787 | 555 | init_completion(&dev->cmd_complete); |
95a7f10e VB |
556 | dev->dev = get_device(&pdev->dev); |
557 | dev->irq = irq->start; | |
558 | platform_set_drvdata(pdev, dev); | |
559 | ||
e164ddee | 560 | dev->clk = clk_get(&pdev->dev, NULL); |
95a7f10e VB |
561 | if (IS_ERR(dev->clk)) { |
562 | r = -ENODEV; | |
563 | goto err_free_mem; | |
564 | } | |
565 | clk_enable(dev->clk); | |
566 | ||
567 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
568 | i2c_davinci_init(dev); | |
569 | ||
570 | r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev); | |
571 | if (r) { | |
572 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | |
573 | goto err_unuse_clocks; | |
574 | } | |
575 | ||
576 | adap = &dev->adapter; | |
577 | i2c_set_adapdata(adap, dev); | |
578 | adap->owner = THIS_MODULE; | |
579 | adap->class = I2C_CLASS_HWMON; | |
580 | strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); | |
581 | adap->algo = &i2c_davinci_algo; | |
582 | adap->dev.parent = &pdev->dev; | |
98a679ca | 583 | adap->timeout = DAVINCI_I2C_TIMEOUT; |
95a7f10e VB |
584 | |
585 | adap->nr = pdev->id; | |
586 | r = i2c_add_numbered_adapter(adap); | |
587 | if (r) { | |
588 | dev_err(&pdev->dev, "failure adding adapter\n"); | |
589 | goto err_free_irq; | |
590 | } | |
591 | ||
592 | return 0; | |
593 | ||
594 | err_free_irq: | |
595 | free_irq(dev->irq, dev); | |
596 | err_unuse_clocks: | |
597 | clk_disable(dev->clk); | |
598 | clk_put(dev->clk); | |
599 | dev->clk = NULL; | |
600 | err_free_mem: | |
601 | platform_set_drvdata(pdev, NULL); | |
602 | put_device(&pdev->dev); | |
603 | kfree(dev); | |
604 | err_release_region: | |
59330825 | 605 | release_mem_region(mem->start, resource_size(mem)); |
95a7f10e VB |
606 | |
607 | return r; | |
608 | } | |
609 | ||
610 | static int davinci_i2c_remove(struct platform_device *pdev) | |
611 | { | |
612 | struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); | |
613 | struct resource *mem; | |
614 | ||
615 | platform_set_drvdata(pdev, NULL); | |
616 | i2c_del_adapter(&dev->adapter); | |
617 | put_device(&pdev->dev); | |
618 | ||
619 | clk_disable(dev->clk); | |
620 | clk_put(dev->clk); | |
621 | dev->clk = NULL; | |
622 | ||
623 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); | |
624 | free_irq(IRQ_I2C, dev); | |
625 | kfree(dev); | |
626 | ||
627 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
59330825 | 628 | release_mem_region(mem->start, resource_size(mem)); |
95a7f10e VB |
629 | return 0; |
630 | } | |
631 | ||
add8eda7 KS |
632 | /* work with hotplug and coldplug */ |
633 | MODULE_ALIAS("platform:i2c_davinci"); | |
634 | ||
95a7f10e VB |
635 | static struct platform_driver davinci_i2c_driver = { |
636 | .probe = davinci_i2c_probe, | |
637 | .remove = davinci_i2c_remove, | |
638 | .driver = { | |
639 | .name = "i2c_davinci", | |
640 | .owner = THIS_MODULE, | |
641 | }, | |
642 | }; | |
643 | ||
644 | /* I2C may be needed to bring up other drivers */ | |
645 | static int __init davinci_i2c_init_driver(void) | |
646 | { | |
647 | return platform_driver_register(&davinci_i2c_driver); | |
648 | } | |
649 | subsys_initcall(davinci_i2c_init_driver); | |
650 | ||
651 | static void __exit davinci_i2c_exit_driver(void) | |
652 | { | |
653 | platform_driver_unregister(&davinci_i2c_driver); | |
654 | } | |
655 | module_exit(davinci_i2c_exit_driver); | |
656 | ||
657 | MODULE_AUTHOR("Texas Instruments India"); | |
658 | MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); | |
659 | MODULE_LICENSE("GPL"); |