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1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
1ab52cf9 BS |
21 | * ---------------------------------------------------------------------------- |
22 | * | |
23 | */ | |
e68bb91b | 24 | #include <linux/export.h> |
1ab52cf9 | 25 | #include <linux/errno.h> |
1ab52cf9 | 26 | #include <linux/err.h> |
2373f6b9 | 27 | #include <linux/i2c.h> |
1ab52cf9 | 28 | #include <linux/interrupt.h> |
1ab52cf9 | 29 | #include <linux/io.h> |
18dbdda8 | 30 | #include <linux/pm_runtime.h> |
2373f6b9 | 31 | #include <linux/delay.h> |
9dd3162d | 32 | #include <linux/module.h> |
2373f6b9 | 33 | #include "i2c-designware-core.h" |
ce6eb574 | 34 | |
f3fa9f3d DB |
35 | /* |
36 | * Registers offset | |
37 | */ | |
38 | #define DW_IC_CON 0x0 | |
39 | #define DW_IC_TAR 0x4 | |
40 | #define DW_IC_DATA_CMD 0x10 | |
41 | #define DW_IC_SS_SCL_HCNT 0x14 | |
42 | #define DW_IC_SS_SCL_LCNT 0x18 | |
43 | #define DW_IC_FS_SCL_HCNT 0x1c | |
44 | #define DW_IC_FS_SCL_LCNT 0x20 | |
45 | #define DW_IC_INTR_STAT 0x2c | |
46 | #define DW_IC_INTR_MASK 0x30 | |
47 | #define DW_IC_RAW_INTR_STAT 0x34 | |
48 | #define DW_IC_RX_TL 0x38 | |
49 | #define DW_IC_TX_TL 0x3c | |
50 | #define DW_IC_CLR_INTR 0x40 | |
51 | #define DW_IC_CLR_RX_UNDER 0x44 | |
52 | #define DW_IC_CLR_RX_OVER 0x48 | |
53 | #define DW_IC_CLR_TX_OVER 0x4c | |
54 | #define DW_IC_CLR_RD_REQ 0x50 | |
55 | #define DW_IC_CLR_TX_ABRT 0x54 | |
56 | #define DW_IC_CLR_RX_DONE 0x58 | |
57 | #define DW_IC_CLR_ACTIVITY 0x5c | |
58 | #define DW_IC_CLR_STOP_DET 0x60 | |
59 | #define DW_IC_CLR_START_DET 0x64 | |
60 | #define DW_IC_CLR_GEN_CALL 0x68 | |
61 | #define DW_IC_ENABLE 0x6c | |
62 | #define DW_IC_STATUS 0x70 | |
63 | #define DW_IC_TXFLR 0x74 | |
64 | #define DW_IC_RXFLR 0x78 | |
9803f868 | 65 | #define DW_IC_SDA_HOLD 0x7c |
f3fa9f3d | 66 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
3ca4ed87 | 67 | #define DW_IC_ENABLE_STATUS 0x9c |
f3fa9f3d | 68 | #define DW_IC_COMP_PARAM_1 0xf4 |
9803f868 CR |
69 | #define DW_IC_COMP_VERSION 0xf8 |
70 | #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A | |
f3fa9f3d DB |
71 | #define DW_IC_COMP_TYPE 0xfc |
72 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | |
73 | ||
74 | #define DW_IC_INTR_RX_UNDER 0x001 | |
75 | #define DW_IC_INTR_RX_OVER 0x002 | |
76 | #define DW_IC_INTR_RX_FULL 0x004 | |
77 | #define DW_IC_INTR_TX_OVER 0x008 | |
78 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
79 | #define DW_IC_INTR_RD_REQ 0x020 | |
80 | #define DW_IC_INTR_TX_ABRT 0x040 | |
81 | #define DW_IC_INTR_RX_DONE 0x080 | |
82 | #define DW_IC_INTR_ACTIVITY 0x100 | |
83 | #define DW_IC_INTR_STOP_DET 0x200 | |
84 | #define DW_IC_INTR_START_DET 0x400 | |
85 | #define DW_IC_INTR_GEN_CALL 0x800 | |
86 | ||
87 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | |
88 | DW_IC_INTR_TX_EMPTY | \ | |
89 | DW_IC_INTR_TX_ABRT | \ | |
90 | DW_IC_INTR_STOP_DET) | |
91 | ||
92 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
93 | ||
94 | #define DW_IC_ERR_TX_ABRT 0x1 | |
95 | ||
bd63ace4 CCE |
96 | #define DW_IC_TAR_10BITADDR_MASTER BIT(12) |
97 | ||
f3fa9f3d DB |
98 | /* |
99 | * status codes | |
100 | */ | |
101 | #define STATUS_IDLE 0x0 | |
102 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
103 | #define STATUS_READ_IN_PROGRESS 0x2 | |
104 | ||
105 | #define TIMEOUT 20 /* ms */ | |
106 | ||
107 | /* | |
108 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
109 | * | |
110 | * only expected abort codes are listed here | |
111 | * refer to the datasheet for the full list | |
112 | */ | |
113 | #define ABRT_7B_ADDR_NOACK 0 | |
114 | #define ABRT_10ADDR1_NOACK 1 | |
115 | #define ABRT_10ADDR2_NOACK 2 | |
116 | #define ABRT_TXDATA_NOACK 3 | |
117 | #define ABRT_GCALL_NOACK 4 | |
118 | #define ABRT_GCALL_READ 5 | |
119 | #define ABRT_SBYTE_ACKDET 7 | |
120 | #define ABRT_SBYTE_NORSTRT 9 | |
121 | #define ABRT_10B_RD_NORSTRT 10 | |
122 | #define ABRT_MASTER_DIS 11 | |
123 | #define ARB_LOST 12 | |
124 | ||
125 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | |
126 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
127 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
128 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
129 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
130 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
131 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
132 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
133 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
134 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
135 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
136 | ||
137 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
138 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
139 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
140 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
141 | DW_IC_TX_ABRT_GCALL_NOACK) | |
142 | ||
1ab52cf9 | 143 | static char *abort_sources[] = { |
a0e06ea6 | 144 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 145 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 146 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 147 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 148 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 149 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 150 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 151 | "data not acknowledged", |
a0e06ea6 | 152 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 153 | "no acknowledgement for a general call", |
a0e06ea6 | 154 | [ABRT_GCALL_READ] = |
1ab52cf9 | 155 | "read after general call", |
a0e06ea6 | 156 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 157 | "start byte acknowledged", |
a0e06ea6 | 158 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 159 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 160 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 161 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 162 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 163 | "trying to use disabled adapter", |
a0e06ea6 | 164 | [ARB_LOST] = |
1ab52cf9 BS |
165 | "lost arbitration", |
166 | }; | |
167 | ||
8a437459 | 168 | static u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
7f279601 | 169 | { |
a8a9f3fe | 170 | u32 value; |
18c4089e | 171 | |
a8a9f3fe | 172 | if (dev->accessor_flags & ACCESS_16BIT) |
67105c5a JZ |
173 | value = readw_relaxed(dev->base + offset) | |
174 | (readw_relaxed(dev->base + offset + 2) << 16); | |
a8a9f3fe | 175 | else |
67105c5a | 176 | value = readl_relaxed(dev->base + offset); |
a8a9f3fe SR |
177 | |
178 | if (dev->accessor_flags & ACCESS_SWAP) | |
18c4089e JHD |
179 | return swab32(value); |
180 | else | |
181 | return value; | |
7f279601 JHD |
182 | } |
183 | ||
8a437459 | 184 | static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
7f279601 | 185 | { |
a8a9f3fe | 186 | if (dev->accessor_flags & ACCESS_SWAP) |
18c4089e JHD |
187 | b = swab32(b); |
188 | ||
a8a9f3fe | 189 | if (dev->accessor_flags & ACCESS_16BIT) { |
67105c5a JZ |
190 | writew_relaxed((u16)b, dev->base + offset); |
191 | writew_relaxed((u16)(b >> 16), dev->base + offset + 2); | |
a8a9f3fe | 192 | } else { |
67105c5a | 193 | writel_relaxed(b, dev->base + offset); |
a8a9f3fe | 194 | } |
7f279601 JHD |
195 | } |
196 | ||
d60c7e81 SK |
197 | static u32 |
198 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
199 | { | |
200 | /* | |
201 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
202 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
203 | * will result in violation of the tHD;STA spec. | |
204 | */ | |
205 | if (cond) | |
206 | /* | |
207 | * Conditional expression: | |
208 | * | |
209 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
210 | * | |
211 | * This is based on the DW manuals, and represents an ideal | |
212 | * configuration. The resulting I2C bus speed will be | |
213 | * faster than any of the others. | |
214 | * | |
215 | * If your hardware is free from tHD;STA issue, try this one. | |
216 | */ | |
6468276b | 217 | return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset; |
d60c7e81 SK |
218 | else |
219 | /* | |
220 | * Conditional expression: | |
221 | * | |
222 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
223 | * | |
224 | * This is just experimental rule; the tHD;STA period turned | |
225 | * out to be proportinal to (_HCNT + 3). With this setting, | |
226 | * we could meet both tHIGH and tHD;STA timing specs. | |
227 | * | |
228 | * If unsure, you'd better to take this alternative. | |
229 | * | |
230 | * The reason why we need to take into account "tf" here, | |
231 | * is the same as described in i2c_dw_scl_lcnt(). | |
232 | */ | |
6468276b RB |
233 | return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000 |
234 | - 3 + offset; | |
d60c7e81 SK |
235 | } |
236 | ||
237 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
238 | { | |
239 | /* | |
240 | * Conditional expression: | |
241 | * | |
242 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
243 | * | |
244 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
245 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
246 | * In order to meet the tLOW timing spec, we need to take into | |
247 | * account the fall time of SCL signal (tf). Default tf value | |
248 | * should be 0.3 us, for safety. | |
249 | */ | |
6468276b | 250 | return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset; |
d60c7e81 SK |
251 | } |
252 | ||
3ca4ed87 MW |
253 | static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) |
254 | { | |
255 | int timeout = 100; | |
256 | ||
257 | do { | |
258 | dw_writel(dev, enable, DW_IC_ENABLE); | |
259 | if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) | |
260 | return; | |
261 | ||
262 | /* | |
263 | * Wait 10 times the signaling period of the highest I2C | |
264 | * transfer supported by the driver (for 400KHz this is | |
265 | * 25us) as described in the DesignWare I2C databook. | |
266 | */ | |
267 | usleep_range(25, 250); | |
268 | } while (timeout--); | |
269 | ||
270 | dev_warn(dev->dev, "timeout in %sabling adapter\n", | |
271 | enable ? "en" : "dis"); | |
272 | } | |
273 | ||
b33af11d SS |
274 | static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) |
275 | { | |
276 | /* | |
277 | * Clock is not necessary if we got LCNT/HCNT values directly from | |
278 | * the platform code. | |
279 | */ | |
280 | if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) | |
281 | return 0; | |
282 | return dev->get_clk_rate_khz(dev); | |
283 | } | |
284 | ||
1ab52cf9 BS |
285 | /** |
286 | * i2c_dw_init() - initialize the designware i2c master hardware | |
287 | * @dev: device private data | |
288 | * | |
289 | * This functions configures and enables the I2C master. | |
290 | * This function is called during I2C init function, and in case of timeout at | |
291 | * run time. | |
292 | */ | |
2373f6b9 | 293 | int i2c_dw_init(struct dw_i2c_dev *dev) |
1ab52cf9 | 294 | { |
e18563fc | 295 | u32 hcnt, lcnt; |
4a423a8c | 296 | u32 reg; |
6468276b | 297 | u32 sda_falling_time, scl_falling_time; |
c0601d28 DB |
298 | int ret; |
299 | ||
300 | if (dev->acquire_lock) { | |
301 | ret = dev->acquire_lock(dev); | |
302 | if (ret) { | |
303 | dev_err(dev->dev, "couldn't acquire bus ownership\n"); | |
304 | return ret; | |
305 | } | |
306 | } | |
4a423a8c | 307 | |
4a423a8c DB |
308 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
309 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe SR |
310 | /* Configure register endianess access */ |
311 | dev->accessor_flags |= ACCESS_SWAP; | |
312 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
313 | /* Configure register access mode 16bit */ | |
314 | dev->accessor_flags |= ACCESS_16BIT; | |
315 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
4a423a8c DB |
316 | dev_err(dev->dev, "Unknown Synopsys component type: " |
317 | "0x%08x\n", reg); | |
c0601d28 DB |
318 | if (dev->release_lock) |
319 | dev->release_lock(dev); | |
4a423a8c DB |
320 | return -ENODEV; |
321 | } | |
1ab52cf9 BS |
322 | |
323 | /* Disable the adapter */ | |
3ca4ed87 | 324 | __i2c_dw_enable(dev, false); |
1ab52cf9 BS |
325 | |
326 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 | 327 | |
6468276b RB |
328 | sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ |
329 | scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ | |
330 | ||
42ffd390 | 331 | /* Set SCL timing parameters for standard-mode */ |
defc0b2f MW |
332 | if (dev->ss_hcnt && dev->ss_lcnt) { |
333 | hcnt = dev->ss_hcnt; | |
334 | lcnt = dev->ss_lcnt; | |
42ffd390 | 335 | } else { |
b33af11d | 336 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
337 | 4000, /* tHD;STA = tHIGH = 4.0 us */ |
338 | sda_falling_time, | |
339 | 0, /* 0: DW default, 1: Ideal */ | |
340 | 0); /* No offset */ | |
b33af11d | 341 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
342 | 4700, /* tLOW = 4.7 us */ |
343 | scl_falling_time, | |
344 | 0); /* No offset */ | |
defc0b2f | 345 | } |
7f279601 JHD |
346 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
347 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
348 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
349 | ||
42ffd390 | 350 | /* Set SCL timing parameters for fast-mode */ |
defc0b2f MW |
351 | if (dev->fs_hcnt && dev->fs_lcnt) { |
352 | hcnt = dev->fs_hcnt; | |
353 | lcnt = dev->fs_lcnt; | |
42ffd390 | 354 | } else { |
b33af11d | 355 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
356 | 600, /* tHD;STA = tHIGH = 0.6 us */ |
357 | sda_falling_time, | |
358 | 0, /* 0: DW default, 1: Ideal */ | |
359 | 0); /* No offset */ | |
b33af11d | 360 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
361 | 1300, /* tLOW = 1.3 us */ |
362 | scl_falling_time, | |
363 | 0); /* No offset */ | |
defc0b2f | 364 | } |
7f279601 JHD |
365 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
366 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 367 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 368 | |
9803f868 | 369 | /* Configure SDA Hold Time if required */ |
664d58bf ZL |
370 | reg = dw_readl(dev, DW_IC_COMP_VERSION); |
371 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { | |
372 | if (dev->sda_hold_time) { | |
9803f868 | 373 | dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); |
664d58bf ZL |
374 | } else { |
375 | /* Keep previous hold time setting if no one set it */ | |
376 | dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD); | |
377 | } | |
378 | } else { | |
379 | dev_warn(dev->dev, | |
380 | "Hardware too old to adjust SDA hold time.\n"); | |
9803f868 CR |
381 | } |
382 | ||
4cb6d1d6 | 383 | /* Configure Tx/Rx FIFO threshold levels */ |
d39f77b0 | 384 | dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL); |
7f279601 | 385 | dw_writel(dev, 0, DW_IC_RX_TL); |
4cb6d1d6 | 386 | |
1ab52cf9 | 387 | /* configure the i2c master */ |
e18563fc | 388 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
c0601d28 DB |
389 | |
390 | if (dev->release_lock) | |
391 | dev->release_lock(dev); | |
4a423a8c | 392 | return 0; |
1ab52cf9 | 393 | } |
e68bb91b | 394 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
1ab52cf9 BS |
395 | |
396 | /* | |
397 | * Waiting for bus not busy | |
398 | */ | |
399 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
400 | { | |
401 | int timeout = TIMEOUT; | |
402 | ||
7f279601 | 403 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
404 | if (timeout <= 0) { |
405 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
406 | return -ETIMEDOUT; | |
407 | } | |
408 | timeout--; | |
1451b91f | 409 | usleep_range(1000, 1100); |
1ab52cf9 BS |
410 | } |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
81e798b7 SK |
415 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
416 | { | |
417 | struct i2c_msg *msgs = dev->msgs; | |
bd63ace4 | 418 | u32 ic_con, ic_tar = 0; |
81e798b7 SK |
419 | |
420 | /* Disable the adapter */ | |
3ca4ed87 | 421 | __i2c_dw_enable(dev, false); |
81e798b7 | 422 | |
81e798b7 | 423 | /* if the slave address is ten bit address, enable 10BITADDR */ |
7f279601 | 424 | ic_con = dw_readl(dev, DW_IC_CON); |
bd63ace4 | 425 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { |
81e798b7 | 426 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
bd63ace4 CCE |
427 | /* |
428 | * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing | |
429 | * mode has to be enabled via bit 12 of IC_TAR register. | |
430 | * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be | |
431 | * detected from registers. | |
432 | */ | |
433 | ic_tar = DW_IC_TAR_10BITADDR_MASTER; | |
434 | } else { | |
81e798b7 | 435 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
bd63ace4 CCE |
436 | } |
437 | ||
7f279601 | 438 | dw_writel(dev, ic_con, DW_IC_CON); |
81e798b7 | 439 | |
bd63ace4 CCE |
440 | /* |
441 | * Set the slave (target) address and enable 10-bit addressing mode | |
442 | * if applicable. | |
443 | */ | |
444 | dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR); | |
445 | ||
47bb27e7 DW |
446 | /* enforce disabled interrupts (due to HW issues) */ |
447 | i2c_dw_disable_int(dev); | |
448 | ||
81e798b7 | 449 | /* Enable the adapter */ |
3ca4ed87 | 450 | __i2c_dw_enable(dev, true); |
201d6a70 | 451 | |
2a2d95e9 | 452 | /* Clear and enable interrupts */ |
c335631a | 453 | dw_readl(dev, DW_IC_CLR_INTR); |
7f279601 | 454 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
455 | } |
456 | ||
1ab52cf9 | 457 | /* |
201d6a70 SK |
458 | * Initiate (and continue) low level master read/write transaction. |
459 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
460 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
461 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 462 | */ |
bccd780f | 463 | static void |
e77cf232 | 464 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 465 | { |
1ab52cf9 | 466 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 467 | u32 intr_mask; |
ae72222d | 468 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
469 | u32 addr = msgs[dev->msg_write_idx].addr; |
470 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 471 | u8 *buf = dev->tx_buf; |
82564245 | 472 | bool need_restart = false; |
1ab52cf9 | 473 | |
201d6a70 | 474 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 475 | |
6d2ea487 | 476 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
477 | /* |
478 | * if target address has changed, we need to | |
1ab52cf9 BS |
479 | * reprogram the target address in the i2c |
480 | * adapter when we are done with this transfer | |
481 | */ | |
8f588e40 SK |
482 | if (msgs[dev->msg_write_idx].addr != addr) { |
483 | dev_err(dev->dev, | |
484 | "%s: invalid target address\n", __func__); | |
485 | dev->msg_err = -EINVAL; | |
486 | break; | |
487 | } | |
1ab52cf9 BS |
488 | |
489 | if (msgs[dev->msg_write_idx].len == 0) { | |
490 | dev_err(dev->dev, | |
491 | "%s: invalid message length\n", __func__); | |
492 | dev->msg_err = -EINVAL; | |
8f588e40 | 493 | break; |
1ab52cf9 BS |
494 | } |
495 | ||
496 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
497 | /* new i2c_msg */ | |
26ea15b1 | 498 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 | 499 | buf_len = msgs[dev->msg_write_idx].len; |
82564245 CCE |
500 | |
501 | /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and | |
502 | * IC_RESTART_EN are set, we must manually | |
503 | * set restart bit between messages. | |
504 | */ | |
505 | if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && | |
506 | (dev->msg_write_idx > 0)) | |
507 | need_restart = true; | |
1ab52cf9 BS |
508 | } |
509 | ||
7f279601 JHD |
510 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
511 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 512 | |
1ab52cf9 | 513 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
17a76b4b MW |
514 | u32 cmd = 0; |
515 | ||
516 | /* | |
517 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must | |
518 | * manually set the stop bit. However, it cannot be | |
519 | * detected from the registers so we set it always | |
520 | * when writing/reading the last byte. | |
521 | */ | |
522 | if (dev->msg_write_idx == dev->msgs_num - 1 && | |
523 | buf_len == 1) | |
524 | cmd |= BIT(9); | |
525 | ||
82564245 CCE |
526 | if (need_restart) { |
527 | cmd |= BIT(10); | |
528 | need_restart = false; | |
529 | } | |
530 | ||
1ab52cf9 | 531 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
e6f34cea JA |
532 | |
533 | /* avoid rx buffer overrun */ | |
534 | if (rx_limit - dev->rx_outstanding <= 0) | |
535 | break; | |
536 | ||
17a76b4b | 537 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
1ab52cf9 | 538 | rx_limit--; |
e6f34cea | 539 | dev->rx_outstanding++; |
1ab52cf9 | 540 | } else |
17a76b4b | 541 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
542 | tx_limit--; buf_len--; |
543 | } | |
c70c5cd3 | 544 | |
26ea15b1 | 545 | dev->tx_buf = buf; |
c70c5cd3 SK |
546 | dev->tx_buf_len = buf_len; |
547 | ||
548 | if (buf_len > 0) { | |
549 | /* more bytes to be written */ | |
c70c5cd3 SK |
550 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
551 | break; | |
69151e53 | 552 | } else |
c70c5cd3 | 553 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
554 | } |
555 | ||
69151e53 SK |
556 | /* |
557 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
558 | * interrupt any more. | |
559 | */ | |
560 | if (dev->msg_write_idx == dev->msgs_num) | |
561 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
562 | ||
8f588e40 SK |
563 | if (dev->msg_err) |
564 | intr_mask = 0; | |
565 | ||
2373f6b9 | 566 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
567 | } |
568 | ||
569 | static void | |
78839bd0 | 570 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 571 | { |
1ab52cf9 | 572 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 573 | int rx_valid; |
1ab52cf9 | 574 | |
6d2ea487 | 575 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 576 | u32 len; |
1ab52cf9 BS |
577 | u8 *buf; |
578 | ||
579 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
580 | continue; | |
581 | ||
1ab52cf9 BS |
582 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
583 | len = msgs[dev->msg_read_idx].len; | |
584 | buf = msgs[dev->msg_read_idx].buf; | |
585 | } else { | |
586 | len = dev->rx_buf_len; | |
587 | buf = dev->rx_buf; | |
588 | } | |
589 | ||
7f279601 | 590 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 591 | |
e6f34cea | 592 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
7f279601 | 593 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
e6f34cea JA |
594 | dev->rx_outstanding--; |
595 | } | |
1ab52cf9 BS |
596 | |
597 | if (len > 0) { | |
598 | dev->status |= STATUS_READ_IN_PROGRESS; | |
599 | dev->rx_buf_len = len; | |
600 | dev->rx_buf = buf; | |
601 | return; | |
602 | } else | |
603 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
604 | } | |
605 | } | |
606 | ||
ce6eb574 SK |
607 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
608 | { | |
609 | unsigned long abort_source = dev->abort_source; | |
610 | int i; | |
611 | ||
6d1ea0f6 | 612 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 613 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
614 | dev_dbg(dev->dev, |
615 | "%s: %s\n", __func__, abort_sources[i]); | |
616 | return -EREMOTEIO; | |
617 | } | |
618 | ||
984b3f57 | 619 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
620 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
621 | ||
622 | if (abort_source & DW_IC_TX_ARB_LOST) | |
623 | return -EAGAIN; | |
ce6eb574 SK |
624 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
625 | return -EINVAL; /* wrong msgs[] data */ | |
626 | else | |
627 | return -EIO; | |
628 | } | |
629 | ||
1ab52cf9 BS |
630 | /* |
631 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
632 | */ | |
d80d1341 | 633 | static int |
1ab52cf9 BS |
634 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
635 | { | |
636 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
637 | int ret; | |
638 | ||
639 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
640 | ||
18dbdda8 | 641 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 | 642 | |
16735d02 | 643 | reinit_completion(&dev->cmd_complete); |
1ab52cf9 BS |
644 | dev->msgs = msgs; |
645 | dev->msgs_num = num; | |
646 | dev->cmd_err = 0; | |
647 | dev->msg_write_idx = 0; | |
648 | dev->msg_read_idx = 0; | |
649 | dev->msg_err = 0; | |
650 | dev->status = STATUS_IDLE; | |
ce6eb574 | 651 | dev->abort_source = 0; |
e6f34cea | 652 | dev->rx_outstanding = 0; |
1ab52cf9 | 653 | |
c0601d28 DB |
654 | if (dev->acquire_lock) { |
655 | ret = dev->acquire_lock(dev); | |
656 | if (ret) { | |
657 | dev_err(dev->dev, "couldn't acquire bus ownership\n"); | |
658 | goto done_nolock; | |
659 | } | |
660 | } | |
661 | ||
1ab52cf9 BS |
662 | ret = i2c_dw_wait_bus_not_busy(dev); |
663 | if (ret < 0) | |
664 | goto done; | |
665 | ||
666 | /* start the transfers */ | |
81e798b7 | 667 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
668 | |
669 | /* wait for tx to complete */ | |
d0bcd8df | 670 | if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { |
1ab52cf9 | 671 | dev_err(dev->dev, "controller timed out\n"); |
38d7fade | 672 | /* i2c_dw_init implicitly disables the adapter */ |
1ab52cf9 BS |
673 | i2c_dw_init(dev); |
674 | ret = -ETIMEDOUT; | |
675 | goto done; | |
e42dba56 | 676 | } |
1ab52cf9 | 677 | |
38d7fade | 678 | /* |
e3c97650 BS |
679 | * We must disable the adapter before returning and signaling the end |
680 | * of the current transfer. Otherwise the hardware might continue | |
681 | * generating interrupts which in turn causes a race condition with | |
682 | * the following transfer. Needs some more investigation if the | |
683 | * additional interrupts are a hardware bug or this driver doesn't | |
684 | * handle them correctly yet. | |
38d7fade CR |
685 | */ |
686 | __i2c_dw_enable(dev, false); | |
687 | ||
1ab52cf9 BS |
688 | if (dev->msg_err) { |
689 | ret = dev->msg_err; | |
690 | goto done; | |
691 | } | |
692 | ||
693 | /* no error */ | |
694 | if (likely(!dev->cmd_err)) { | |
1ab52cf9 BS |
695 | ret = num; |
696 | goto done; | |
697 | } | |
698 | ||
699 | /* We have an error */ | |
700 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
701 | ret = i2c_dw_handle_tx_abort(dev); |
702 | goto done; | |
1ab52cf9 BS |
703 | } |
704 | ret = -EIO; | |
705 | ||
706 | done: | |
c0601d28 DB |
707 | if (dev->release_lock) |
708 | dev->release_lock(dev); | |
709 | ||
710 | done_nolock: | |
43452335 MW |
711 | pm_runtime_mark_last_busy(dev->dev); |
712 | pm_runtime_put_autosuspend(dev->dev); | |
1ab52cf9 BS |
713 | |
714 | return ret; | |
715 | } | |
716 | ||
d80d1341 | 717 | static u32 i2c_dw_func(struct i2c_adapter *adap) |
1ab52cf9 | 718 | { |
2fa8326b DB |
719 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
720 | return dev->functionality; | |
1ab52cf9 | 721 | } |
d80d1341 JN |
722 | |
723 | static struct i2c_algorithm i2c_dw_algo = { | |
724 | .master_xfer = i2c_dw_xfer, | |
725 | .functionality = i2c_dw_func, | |
726 | }; | |
1ab52cf9 | 727 | |
e28000a3 SK |
728 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
729 | { | |
730 | u32 stat; | |
731 | ||
732 | /* | |
733 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
734 | * Ths unmasked raw version of interrupt status bits are available | |
735 | * in the IC_RAW_INTR_STAT register. | |
736 | * | |
737 | * That is, | |
2373f6b9 | 738 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 739 | * equals to, |
2373f6b9 | 740 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
741 | * |
742 | * The raw version might be useful for debugging purposes. | |
743 | */ | |
7f279601 | 744 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
745 | |
746 | /* | |
747 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
748 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 749 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
750 | * |
751 | * Instead, use the separately-prepared IC_CLR_* registers. | |
752 | */ | |
753 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 754 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 755 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 756 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 757 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 758 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 759 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 760 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
761 | if (stat & DW_IC_INTR_TX_ABRT) { |
762 | /* | |
763 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
764 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
765 | */ | |
7f279601 JHD |
766 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
767 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
768 | } |
769 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 770 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 771 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 772 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 773 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 774 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 775 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 776 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 777 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 778 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
779 | |
780 | return stat; | |
781 | } | |
782 | ||
1ab52cf9 BS |
783 | /* |
784 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
785 | * occurs. | |
786 | */ | |
d80d1341 | 787 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
1ab52cf9 BS |
788 | { |
789 | struct dw_i2c_dev *dev = dev_id; | |
af06cf6c DB |
790 | u32 stat, enabled; |
791 | ||
792 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
793 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
fb427466 | 794 | dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat); |
af06cf6c DB |
795 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) |
796 | return IRQ_NONE; | |
1ab52cf9 | 797 | |
e28000a3 | 798 | stat = i2c_dw_read_clear_intrbits(dev); |
e28000a3 | 799 | |
1ab52cf9 | 800 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
801 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
802 | dev->status = STATUS_IDLE; | |
597fe310 SK |
803 | |
804 | /* | |
805 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
806 | * buffers are flushed. Make sure to skip them. | |
807 | */ | |
7f279601 | 808 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 809 | goto tx_aborted; |
07745399 SK |
810 | } |
811 | ||
21a89d41 | 812 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 813 | i2c_dw_read(dev); |
21a89d41 SK |
814 | |
815 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 816 | i2c_dw_xfer_msg(dev); |
07745399 SK |
817 | |
818 | /* | |
819 | * No need to modify or disable the interrupt mask here. | |
820 | * i2c_dw_xfer_msg() will take care of it according to | |
821 | * the current transmit status. | |
822 | */ | |
1ab52cf9 | 823 | |
597fe310 | 824 | tx_aborted: |
8f588e40 | 825 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 | 826 | complete(&dev->cmd_complete); |
2d244c81 XY |
827 | else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) { |
828 | /* workaround to trigger pending interrupt */ | |
829 | stat = dw_readl(dev, DW_IC_INTR_MASK); | |
830 | i2c_dw_disable_int(dev); | |
831 | dw_writel(dev, stat, DW_IC_INTR_MASK); | |
832 | } | |
1ab52cf9 BS |
833 | |
834 | return IRQ_HANDLED; | |
835 | } | |
f3fa9f3d | 836 | |
18dbdda8 DB |
837 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
838 | { | |
f3fa9f3d | 839 | /* Disable controller */ |
3ca4ed87 | 840 | __i2c_dw_enable(dev, false); |
f3fa9f3d DB |
841 | |
842 | /* Disable all interupts */ | |
843 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
844 | dw_readl(dev, DW_IC_CLR_INTR); | |
845 | } | |
e68bb91b | 846 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
f3fa9f3d | 847 | |
f3fa9f3d DB |
848 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) |
849 | { | |
850 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
851 | } | |
e68bb91b | 852 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
f3fa9f3d DB |
853 | |
854 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) | |
855 | { | |
856 | return dw_readl(dev, DW_IC_COMP_PARAM_1); | |
857 | } | |
e68bb91b | 858 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |
9dd3162d | 859 | |
d80d1341 JN |
860 | int i2c_dw_probe(struct dw_i2c_dev *dev) |
861 | { | |
862 | struct i2c_adapter *adap = &dev->adapter; | |
863 | int r; | |
864 | ||
865 | init_completion(&dev->cmd_complete); | |
d80d1341 JN |
866 | |
867 | r = i2c_dw_init(dev); | |
868 | if (r) | |
869 | return r; | |
870 | ||
871 | snprintf(adap->name, sizeof(adap->name), | |
872 | "Synopsys DesignWare I2C adapter"); | |
8d22f309 | 873 | adap->retries = 3; |
d80d1341 JN |
874 | adap->algo = &i2c_dw_algo; |
875 | adap->dev.parent = dev->dev; | |
876 | i2c_set_adapdata(adap, dev); | |
877 | ||
878 | i2c_dw_disable_int(dev); | |
08c6e8cc AS |
879 | r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, |
880 | IRQF_SHARED | IRQF_COND_SUSPEND, | |
d80d1341 JN |
881 | dev_name(dev->dev), dev); |
882 | if (r) { | |
883 | dev_err(dev->dev, "failure requesting irq %i: %d\n", | |
884 | dev->irq, r); | |
885 | return r; | |
886 | } | |
887 | ||
cd998ded JN |
888 | /* |
889 | * Increment PM usage count during adapter registration in order to | |
890 | * avoid possible spurious runtime suspend when adapter device is | |
891 | * registered to the device core and immediate resume in case bus has | |
892 | * registered I2C slaves that do I2C transfers in their probe. | |
893 | */ | |
894 | pm_runtime_get_noresume(dev->dev); | |
d80d1341 JN |
895 | r = i2c_add_numbered_adapter(adap); |
896 | if (r) | |
897 | dev_err(dev->dev, "failure adding adapter: %d\n", r); | |
cd998ded | 898 | pm_runtime_put_noidle(dev->dev); |
d80d1341 JN |
899 | |
900 | return r; | |
901 | } | |
902 | EXPORT_SYMBOL_GPL(i2c_dw_probe); | |
903 | ||
9dd3162d MW |
904 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); |
905 | MODULE_LICENSE("GPL"); |