]>
Commit | Line | Data |
---|---|---|
1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
1ab52cf9 BS |
21 | * ---------------------------------------------------------------------------- |
22 | * | |
23 | */ | |
e68bb91b | 24 | #include <linux/export.h> |
1ab52cf9 | 25 | #include <linux/errno.h> |
1ab52cf9 | 26 | #include <linux/err.h> |
2373f6b9 | 27 | #include <linux/i2c.h> |
1ab52cf9 | 28 | #include <linux/interrupt.h> |
1ab52cf9 | 29 | #include <linux/io.h> |
18dbdda8 | 30 | #include <linux/pm_runtime.h> |
2373f6b9 | 31 | #include <linux/delay.h> |
9dd3162d | 32 | #include <linux/module.h> |
2373f6b9 | 33 | #include "i2c-designware-core.h" |
ce6eb574 | 34 | |
f3fa9f3d DB |
35 | /* |
36 | * Registers offset | |
37 | */ | |
38 | #define DW_IC_CON 0x0 | |
39 | #define DW_IC_TAR 0x4 | |
40 | #define DW_IC_DATA_CMD 0x10 | |
41 | #define DW_IC_SS_SCL_HCNT 0x14 | |
42 | #define DW_IC_SS_SCL_LCNT 0x18 | |
43 | #define DW_IC_FS_SCL_HCNT 0x1c | |
44 | #define DW_IC_FS_SCL_LCNT 0x20 | |
b6e67145 WV |
45 | #define DW_IC_HS_SCL_HCNT 0x24 |
46 | #define DW_IC_HS_SCL_LCNT 0x28 | |
f3fa9f3d DB |
47 | #define DW_IC_INTR_STAT 0x2c |
48 | #define DW_IC_INTR_MASK 0x30 | |
49 | #define DW_IC_RAW_INTR_STAT 0x34 | |
50 | #define DW_IC_RX_TL 0x38 | |
51 | #define DW_IC_TX_TL 0x3c | |
52 | #define DW_IC_CLR_INTR 0x40 | |
53 | #define DW_IC_CLR_RX_UNDER 0x44 | |
54 | #define DW_IC_CLR_RX_OVER 0x48 | |
55 | #define DW_IC_CLR_TX_OVER 0x4c | |
56 | #define DW_IC_CLR_RD_REQ 0x50 | |
57 | #define DW_IC_CLR_TX_ABRT 0x54 | |
58 | #define DW_IC_CLR_RX_DONE 0x58 | |
59 | #define DW_IC_CLR_ACTIVITY 0x5c | |
60 | #define DW_IC_CLR_STOP_DET 0x60 | |
61 | #define DW_IC_CLR_START_DET 0x64 | |
62 | #define DW_IC_CLR_GEN_CALL 0x68 | |
63 | #define DW_IC_ENABLE 0x6c | |
64 | #define DW_IC_STATUS 0x70 | |
65 | #define DW_IC_TXFLR 0x74 | |
66 | #define DW_IC_RXFLR 0x78 | |
9803f868 | 67 | #define DW_IC_SDA_HOLD 0x7c |
f3fa9f3d | 68 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
3ca4ed87 | 69 | #define DW_IC_ENABLE_STATUS 0x9c |
f3fa9f3d | 70 | #define DW_IC_COMP_PARAM_1 0xf4 |
9803f868 CR |
71 | #define DW_IC_COMP_VERSION 0xf8 |
72 | #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A | |
f3fa9f3d DB |
73 | #define DW_IC_COMP_TYPE 0xfc |
74 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | |
75 | ||
76 | #define DW_IC_INTR_RX_UNDER 0x001 | |
77 | #define DW_IC_INTR_RX_OVER 0x002 | |
78 | #define DW_IC_INTR_RX_FULL 0x004 | |
79 | #define DW_IC_INTR_TX_OVER 0x008 | |
80 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
81 | #define DW_IC_INTR_RD_REQ 0x020 | |
82 | #define DW_IC_INTR_TX_ABRT 0x040 | |
83 | #define DW_IC_INTR_RX_DONE 0x080 | |
84 | #define DW_IC_INTR_ACTIVITY 0x100 | |
85 | #define DW_IC_INTR_STOP_DET 0x200 | |
86 | #define DW_IC_INTR_START_DET 0x400 | |
87 | #define DW_IC_INTR_GEN_CALL 0x800 | |
88 | ||
89 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | |
90 | DW_IC_INTR_TX_EMPTY | \ | |
91 | DW_IC_INTR_TX_ABRT | \ | |
92 | DW_IC_INTR_STOP_DET) | |
93 | ||
89119f08 | 94 | #define DW_IC_STATUS_ACTIVITY 0x1 |
f3fa9f3d | 95 | |
171e23e1 JN |
96 | #define DW_IC_SDA_HOLD_RX_SHIFT 16 |
97 | #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT) | |
98 | ||
f3fa9f3d DB |
99 | #define DW_IC_ERR_TX_ABRT 0x1 |
100 | ||
bd63ace4 CCE |
101 | #define DW_IC_TAR_10BITADDR_MASTER BIT(12) |
102 | ||
b6e67145 WV |
103 | #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) |
104 | #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) | |
105 | ||
f3fa9f3d DB |
106 | /* |
107 | * status codes | |
108 | */ | |
109 | #define STATUS_IDLE 0x0 | |
110 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
111 | #define STATUS_READ_IN_PROGRESS 0x2 | |
112 | ||
113 | #define TIMEOUT 20 /* ms */ | |
114 | ||
115 | /* | |
116 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
117 | * | |
118 | * only expected abort codes are listed here | |
119 | * refer to the datasheet for the full list | |
120 | */ | |
121 | #define ABRT_7B_ADDR_NOACK 0 | |
122 | #define ABRT_10ADDR1_NOACK 1 | |
123 | #define ABRT_10ADDR2_NOACK 2 | |
124 | #define ABRT_TXDATA_NOACK 3 | |
125 | #define ABRT_GCALL_NOACK 4 | |
126 | #define ABRT_GCALL_READ 5 | |
127 | #define ABRT_SBYTE_ACKDET 7 | |
128 | #define ABRT_SBYTE_NORSTRT 9 | |
129 | #define ABRT_10B_RD_NORSTRT 10 | |
130 | #define ABRT_MASTER_DIS 11 | |
131 | #define ARB_LOST 12 | |
132 | ||
133 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | |
134 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
135 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
136 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
137 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
138 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
139 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
140 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
141 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
142 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
143 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
144 | ||
145 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
146 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
147 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
148 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
149 | DW_IC_TX_ABRT_GCALL_NOACK) | |
150 | ||
1ab52cf9 | 151 | static char *abort_sources[] = { |
a0e06ea6 | 152 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 153 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 154 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 155 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 156 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 157 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 158 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 159 | "data not acknowledged", |
a0e06ea6 | 160 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 161 | "no acknowledgement for a general call", |
a0e06ea6 | 162 | [ABRT_GCALL_READ] = |
1ab52cf9 | 163 | "read after general call", |
a0e06ea6 | 164 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 165 | "start byte acknowledged", |
a0e06ea6 | 166 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 167 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 168 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 169 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 170 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 171 | "trying to use disabled adapter", |
a0e06ea6 | 172 | [ARB_LOST] = |
1ab52cf9 BS |
173 | "lost arbitration", |
174 | }; | |
175 | ||
8a437459 | 176 | static u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
7f279601 | 177 | { |
a8a9f3fe | 178 | u32 value; |
18c4089e | 179 | |
a8a9f3fe | 180 | if (dev->accessor_flags & ACCESS_16BIT) |
67105c5a JZ |
181 | value = readw_relaxed(dev->base + offset) | |
182 | (readw_relaxed(dev->base + offset + 2) << 16); | |
a8a9f3fe | 183 | else |
67105c5a | 184 | value = readl_relaxed(dev->base + offset); |
a8a9f3fe SR |
185 | |
186 | if (dev->accessor_flags & ACCESS_SWAP) | |
18c4089e JHD |
187 | return swab32(value); |
188 | else | |
189 | return value; | |
7f279601 JHD |
190 | } |
191 | ||
8a437459 | 192 | static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
7f279601 | 193 | { |
a8a9f3fe | 194 | if (dev->accessor_flags & ACCESS_SWAP) |
18c4089e JHD |
195 | b = swab32(b); |
196 | ||
a8a9f3fe | 197 | if (dev->accessor_flags & ACCESS_16BIT) { |
67105c5a JZ |
198 | writew_relaxed((u16)b, dev->base + offset); |
199 | writew_relaxed((u16)(b >> 16), dev->base + offset + 2); | |
a8a9f3fe | 200 | } else { |
67105c5a | 201 | writel_relaxed(b, dev->base + offset); |
a8a9f3fe | 202 | } |
7f279601 JHD |
203 | } |
204 | ||
d60c7e81 SK |
205 | static u32 |
206 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
207 | { | |
208 | /* | |
209 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
210 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
211 | * will result in violation of the tHD;STA spec. | |
212 | */ | |
213 | if (cond) | |
214 | /* | |
215 | * Conditional expression: | |
216 | * | |
217 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
218 | * | |
219 | * This is based on the DW manuals, and represents an ideal | |
220 | * configuration. The resulting I2C bus speed will be | |
221 | * faster than any of the others. | |
222 | * | |
223 | * If your hardware is free from tHD;STA issue, try this one. | |
224 | */ | |
6468276b | 225 | return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset; |
d60c7e81 SK |
226 | else |
227 | /* | |
228 | * Conditional expression: | |
229 | * | |
230 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
231 | * | |
232 | * This is just experimental rule; the tHD;STA period turned | |
233 | * out to be proportinal to (_HCNT + 3). With this setting, | |
234 | * we could meet both tHIGH and tHD;STA timing specs. | |
235 | * | |
236 | * If unsure, you'd better to take this alternative. | |
237 | * | |
238 | * The reason why we need to take into account "tf" here, | |
239 | * is the same as described in i2c_dw_scl_lcnt(). | |
240 | */ | |
6468276b RB |
241 | return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000 |
242 | - 3 + offset; | |
d60c7e81 SK |
243 | } |
244 | ||
245 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
246 | { | |
247 | /* | |
248 | * Conditional expression: | |
249 | * | |
250 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
251 | * | |
252 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
253 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
254 | * In order to meet the tLOW timing spec, we need to take into | |
255 | * account the fall time of SCL signal (tf). Default tf value | |
256 | * should be 0.3 us, for safety. | |
257 | */ | |
6468276b | 258 | return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset; |
d60c7e81 SK |
259 | } |
260 | ||
3ca4ed87 | 261 | static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) |
2702ea7d JRS |
262 | { |
263 | dw_writel(dev, enable, DW_IC_ENABLE); | |
264 | } | |
265 | ||
266 | static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable) | |
3ca4ed87 MW |
267 | { |
268 | int timeout = 100; | |
269 | ||
270 | do { | |
2702ea7d | 271 | __i2c_dw_enable(dev, enable); |
3ca4ed87 MW |
272 | if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) |
273 | return; | |
274 | ||
275 | /* | |
276 | * Wait 10 times the signaling period of the highest I2C | |
277 | * transfer supported by the driver (for 400KHz this is | |
278 | * 25us) as described in the DesignWare I2C databook. | |
279 | */ | |
280 | usleep_range(25, 250); | |
281 | } while (timeout--); | |
282 | ||
283 | dev_warn(dev->dev, "timeout in %sabling adapter\n", | |
284 | enable ? "en" : "dis"); | |
285 | } | |
286 | ||
b33af11d SS |
287 | static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) |
288 | { | |
289 | /* | |
290 | * Clock is not necessary if we got LCNT/HCNT values directly from | |
291 | * the platform code. | |
292 | */ | |
293 | if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) | |
294 | return 0; | |
295 | return dev->get_clk_rate_khz(dev); | |
296 | } | |
297 | ||
8c5660bb LDM |
298 | static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) |
299 | { | |
300 | int ret; | |
301 | ||
302 | if (!dev->acquire_lock) | |
303 | return 0; | |
304 | ||
305 | ret = dev->acquire_lock(dev); | |
306 | if (!ret) | |
307 | return 0; | |
308 | ||
309 | dev_err(dev->dev, "couldn't acquire bus ownership\n"); | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
314 | static void i2c_dw_release_lock(struct dw_i2c_dev *dev) | |
315 | { | |
316 | if (dev->release_lock) | |
317 | dev->release_lock(dev); | |
318 | } | |
319 | ||
1ab52cf9 BS |
320 | /** |
321 | * i2c_dw_init() - initialize the designware i2c master hardware | |
322 | * @dev: device private data | |
323 | * | |
324 | * This functions configures and enables the I2C master. | |
325 | * This function is called during I2C init function, and in case of timeout at | |
326 | * run time. | |
327 | */ | |
2373f6b9 | 328 | int i2c_dw_init(struct dw_i2c_dev *dev) |
1ab52cf9 | 329 | { |
e18563fc | 330 | u32 hcnt, lcnt; |
b6e67145 | 331 | u32 reg, comp_param1; |
6468276b | 332 | u32 sda_falling_time, scl_falling_time; |
c0601d28 DB |
333 | int ret; |
334 | ||
8c5660bb LDM |
335 | ret = i2c_dw_acquire_lock(dev); |
336 | if (ret) | |
337 | return ret; | |
4a423a8c | 338 | |
4a423a8c DB |
339 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
340 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe SR |
341 | /* Configure register endianess access */ |
342 | dev->accessor_flags |= ACCESS_SWAP; | |
343 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
344 | /* Configure register access mode 16bit */ | |
345 | dev->accessor_flags |= ACCESS_16BIT; | |
346 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
4a423a8c DB |
347 | dev_err(dev->dev, "Unknown Synopsys component type: " |
348 | "0x%08x\n", reg); | |
8c5660bb | 349 | i2c_dw_release_lock(dev); |
4a423a8c DB |
350 | return -ENODEV; |
351 | } | |
1ab52cf9 | 352 | |
b6e67145 WV |
353 | comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); |
354 | ||
1ab52cf9 | 355 | /* Disable the adapter */ |
2702ea7d | 356 | __i2c_dw_enable_and_wait(dev, false); |
1ab52cf9 BS |
357 | |
358 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 | 359 | |
6468276b RB |
360 | sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ |
361 | scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ | |
362 | ||
42ffd390 | 363 | /* Set SCL timing parameters for standard-mode */ |
defc0b2f MW |
364 | if (dev->ss_hcnt && dev->ss_lcnt) { |
365 | hcnt = dev->ss_hcnt; | |
366 | lcnt = dev->ss_lcnt; | |
42ffd390 | 367 | } else { |
b33af11d | 368 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
369 | 4000, /* tHD;STA = tHIGH = 4.0 us */ |
370 | sda_falling_time, | |
371 | 0, /* 0: DW default, 1: Ideal */ | |
372 | 0); /* No offset */ | |
b33af11d | 373 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
374 | 4700, /* tLOW = 4.7 us */ |
375 | scl_falling_time, | |
376 | 0); /* No offset */ | |
defc0b2f | 377 | } |
7f279601 JHD |
378 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
379 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
380 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
381 | ||
d608c3d9 WV |
382 | /* Set SCL timing parameters for fast-mode or fast-mode plus */ |
383 | if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) { | |
384 | hcnt = dev->fp_hcnt; | |
385 | lcnt = dev->fp_lcnt; | |
386 | } else if (dev->fs_hcnt && dev->fs_lcnt) { | |
defc0b2f MW |
387 | hcnt = dev->fs_hcnt; |
388 | lcnt = dev->fs_lcnt; | |
42ffd390 | 389 | } else { |
b33af11d | 390 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
391 | 600, /* tHD;STA = tHIGH = 0.6 us */ |
392 | sda_falling_time, | |
393 | 0, /* 0: DW default, 1: Ideal */ | |
394 | 0); /* No offset */ | |
b33af11d | 395 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
396 | 1300, /* tLOW = 1.3 us */ |
397 | scl_falling_time, | |
398 | 0); /* No offset */ | |
defc0b2f | 399 | } |
7f279601 JHD |
400 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
401 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 402 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 403 | |
b6e67145 WV |
404 | if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == |
405 | DW_IC_CON_SPEED_HIGH) { | |
406 | if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) | |
407 | != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { | |
408 | dev_err(dev->dev, "High Speed not supported!\n"); | |
409 | dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; | |
410 | dev->master_cfg |= DW_IC_CON_SPEED_FAST; | |
411 | } else if (dev->hs_hcnt && dev->hs_lcnt) { | |
412 | hcnt = dev->hs_hcnt; | |
413 | lcnt = dev->hs_lcnt; | |
414 | dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT); | |
415 | dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT); | |
416 | dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n", | |
417 | hcnt, lcnt); | |
418 | } | |
419 | } | |
420 | ||
9803f868 | 421 | /* Configure SDA Hold Time if required */ |
664d58bf ZL |
422 | reg = dw_readl(dev, DW_IC_COMP_VERSION); |
423 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { | |
171e23e1 | 424 | if (!dev->sda_hold_time) { |
664d58bf ZL |
425 | /* Keep previous hold time setting if no one set it */ |
426 | dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD); | |
427 | } | |
171e23e1 JN |
428 | /* |
429 | * Workaround for avoiding TX arbitration lost in case I2C | |
430 | * slave pulls SDA down "too quickly" after falling egde of | |
431 | * SCL by enabling non-zero SDA RX hold. Specification says it | |
432 | * extends incoming SDA low to high transition while SCL is | |
433 | * high but it apprears to help also above issue. | |
434 | */ | |
435 | if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) | |
436 | dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; | |
437 | dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); | |
664d58bf ZL |
438 | } else { |
439 | dev_warn(dev->dev, | |
440 | "Hardware too old to adjust SDA hold time.\n"); | |
9803f868 CR |
441 | } |
442 | ||
4cb6d1d6 | 443 | /* Configure Tx/Rx FIFO threshold levels */ |
d39f77b0 | 444 | dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL); |
7f279601 | 445 | dw_writel(dev, 0, DW_IC_RX_TL); |
4cb6d1d6 | 446 | |
1ab52cf9 | 447 | /* configure the i2c master */ |
e18563fc | 448 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
c0601d28 | 449 | |
8c5660bb LDM |
450 | i2c_dw_release_lock(dev); |
451 | ||
4a423a8c | 452 | return 0; |
1ab52cf9 | 453 | } |
e68bb91b | 454 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
1ab52cf9 BS |
455 | |
456 | /* | |
457 | * Waiting for bus not busy | |
458 | */ | |
459 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
460 | { | |
461 | int timeout = TIMEOUT; | |
462 | ||
7f279601 | 463 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
464 | if (timeout <= 0) { |
465 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
466 | return -ETIMEDOUT; | |
467 | } | |
468 | timeout--; | |
1451b91f | 469 | usleep_range(1000, 1100); |
1ab52cf9 BS |
470 | } |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
81e798b7 SK |
475 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
476 | { | |
477 | struct i2c_msg *msgs = dev->msgs; | |
12688dc2 | 478 | u32 ic_con, ic_tar = 0; |
81e798b7 | 479 | |
89119f08 JN |
480 | /* Disable the adapter */ |
481 | __i2c_dw_enable_and_wait(dev, false); | |
81e798b7 | 482 | |
81e798b7 | 483 | /* if the slave address is ten bit address, enable 10BITADDR */ |
12688dc2 JN |
484 | ic_con = dw_readl(dev, DW_IC_CON); |
485 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { | |
486 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
bd63ace4 CCE |
487 | /* |
488 | * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing | |
12688dc2 JN |
489 | * mode has to be enabled via bit 12 of IC_TAR register. |
490 | * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be | |
491 | * detected from registers. | |
bd63ace4 | 492 | */ |
12688dc2 | 493 | ic_tar = DW_IC_TAR_10BITADDR_MASTER; |
bd63ace4 | 494 | } else { |
12688dc2 | 495 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
63d0f0a6 | 496 | } |
81e798b7 | 497 | |
12688dc2 JN |
498 | dw_writel(dev, ic_con, DW_IC_CON); |
499 | ||
bd63ace4 CCE |
500 | /* |
501 | * Set the slave (target) address and enable 10-bit addressing mode | |
502 | * if applicable. | |
503 | */ | |
504 | dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR); | |
505 | ||
47bb27e7 DW |
506 | /* enforce disabled interrupts (due to HW issues) */ |
507 | i2c_dw_disable_int(dev); | |
508 | ||
89119f08 JN |
509 | /* Enable the adapter */ |
510 | __i2c_dw_enable(dev, true); | |
201d6a70 | 511 | |
2a2d95e9 | 512 | /* Clear and enable interrupts */ |
c335631a | 513 | dw_readl(dev, DW_IC_CLR_INTR); |
7f279601 | 514 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
515 | } |
516 | ||
1ab52cf9 | 517 | /* |
201d6a70 SK |
518 | * Initiate (and continue) low level master read/write transaction. |
519 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
520 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
521 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 522 | */ |
bccd780f | 523 | static void |
e77cf232 | 524 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 525 | { |
1ab52cf9 | 526 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 527 | u32 intr_mask; |
ae72222d | 528 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
529 | u32 addr = msgs[dev->msg_write_idx].addr; |
530 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 531 | u8 *buf = dev->tx_buf; |
82564245 | 532 | bool need_restart = false; |
1ab52cf9 | 533 | |
201d6a70 | 534 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 535 | |
6d2ea487 | 536 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
c3ae1060 TH |
537 | u32 flags = msgs[dev->msg_write_idx].flags; |
538 | ||
a0e06ea6 SK |
539 | /* |
540 | * if target address has changed, we need to | |
1ab52cf9 BS |
541 | * reprogram the target address in the i2c |
542 | * adapter when we are done with this transfer | |
543 | */ | |
8f588e40 SK |
544 | if (msgs[dev->msg_write_idx].addr != addr) { |
545 | dev_err(dev->dev, | |
546 | "%s: invalid target address\n", __func__); | |
547 | dev->msg_err = -EINVAL; | |
548 | break; | |
549 | } | |
1ab52cf9 BS |
550 | |
551 | if (msgs[dev->msg_write_idx].len == 0) { | |
552 | dev_err(dev->dev, | |
553 | "%s: invalid message length\n", __func__); | |
554 | dev->msg_err = -EINVAL; | |
8f588e40 | 555 | break; |
1ab52cf9 BS |
556 | } |
557 | ||
558 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
559 | /* new i2c_msg */ | |
26ea15b1 | 560 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 | 561 | buf_len = msgs[dev->msg_write_idx].len; |
82564245 CCE |
562 | |
563 | /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and | |
564 | * IC_RESTART_EN are set, we must manually | |
565 | * set restart bit between messages. | |
566 | */ | |
567 | if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && | |
568 | (dev->msg_write_idx > 0)) | |
569 | need_restart = true; | |
1ab52cf9 BS |
570 | } |
571 | ||
7f279601 JHD |
572 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
573 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 574 | |
1ab52cf9 | 575 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
17a76b4b MW |
576 | u32 cmd = 0; |
577 | ||
578 | /* | |
579 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must | |
580 | * manually set the stop bit. However, it cannot be | |
581 | * detected from the registers so we set it always | |
582 | * when writing/reading the last byte. | |
583 | */ | |
c3ae1060 TH |
584 | |
585 | /* | |
586 | * i2c-core.c always sets the buffer length of | |
587 | * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will | |
588 | * be adjusted when receiving the first byte. | |
589 | * Thus we can't stop the transaction here. | |
590 | */ | |
17a76b4b | 591 | if (dev->msg_write_idx == dev->msgs_num - 1 && |
c3ae1060 | 592 | buf_len == 1 && !(flags & I2C_M_RECV_LEN)) |
17a76b4b MW |
593 | cmd |= BIT(9); |
594 | ||
82564245 CCE |
595 | if (need_restart) { |
596 | cmd |= BIT(10); | |
597 | need_restart = false; | |
598 | } | |
599 | ||
1ab52cf9 | 600 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
e6f34cea JA |
601 | |
602 | /* avoid rx buffer overrun */ | |
4d6d5f1d | 603 | if (dev->rx_outstanding >= dev->rx_fifo_depth) |
e6f34cea JA |
604 | break; |
605 | ||
17a76b4b | 606 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
1ab52cf9 | 607 | rx_limit--; |
e6f34cea | 608 | dev->rx_outstanding++; |
1ab52cf9 | 609 | } else |
17a76b4b | 610 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
611 | tx_limit--; buf_len--; |
612 | } | |
c70c5cd3 | 613 | |
26ea15b1 | 614 | dev->tx_buf = buf; |
c70c5cd3 SK |
615 | dev->tx_buf_len = buf_len; |
616 | ||
c3ae1060 TH |
617 | /* |
618 | * Because we don't know the buffer length in the | |
619 | * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop | |
620 | * the transaction here. | |
621 | */ | |
622 | if (buf_len > 0 || flags & I2C_M_RECV_LEN) { | |
c70c5cd3 | 623 | /* more bytes to be written */ |
c70c5cd3 SK |
624 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
625 | break; | |
69151e53 | 626 | } else |
c70c5cd3 | 627 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
628 | } |
629 | ||
69151e53 SK |
630 | /* |
631 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
632 | * interrupt any more. | |
633 | */ | |
634 | if (dev->msg_write_idx == dev->msgs_num) | |
635 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
636 | ||
8f588e40 SK |
637 | if (dev->msg_err) |
638 | intr_mask = 0; | |
639 | ||
2373f6b9 | 640 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
641 | } |
642 | ||
c3ae1060 TH |
643 | static u8 |
644 | i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len) | |
645 | { | |
646 | struct i2c_msg *msgs = dev->msgs; | |
647 | u32 flags = msgs[dev->msg_read_idx].flags; | |
648 | ||
649 | /* | |
650 | * Adjust the buffer length and mask the flag | |
651 | * after receiving the first byte. | |
652 | */ | |
653 | len += (flags & I2C_CLIENT_PEC) ? 2 : 1; | |
654 | dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); | |
655 | msgs[dev->msg_read_idx].len = len; | |
656 | msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; | |
657 | ||
658 | return len; | |
659 | } | |
660 | ||
1ab52cf9 | 661 | static void |
78839bd0 | 662 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 663 | { |
1ab52cf9 | 664 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 665 | int rx_valid; |
1ab52cf9 | 666 | |
6d2ea487 | 667 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 668 | u32 len; |
1ab52cf9 BS |
669 | u8 *buf; |
670 | ||
671 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
672 | continue; | |
673 | ||
1ab52cf9 BS |
674 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
675 | len = msgs[dev->msg_read_idx].len; | |
676 | buf = msgs[dev->msg_read_idx].buf; | |
677 | } else { | |
678 | len = dev->rx_buf_len; | |
679 | buf = dev->rx_buf; | |
680 | } | |
681 | ||
7f279601 | 682 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 683 | |
e6f34cea | 684 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
c3ae1060 TH |
685 | u32 flags = msgs[dev->msg_read_idx].flags; |
686 | ||
687 | *buf = dw_readl(dev, DW_IC_DATA_CMD); | |
688 | /* Ensure length byte is a valid value */ | |
689 | if (flags & I2C_M_RECV_LEN && | |
690 | *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) { | |
691 | len = i2c_dw_recv_len(dev, *buf); | |
692 | } | |
693 | buf++; | |
e6f34cea JA |
694 | dev->rx_outstanding--; |
695 | } | |
1ab52cf9 BS |
696 | |
697 | if (len > 0) { | |
698 | dev->status |= STATUS_READ_IN_PROGRESS; | |
699 | dev->rx_buf_len = len; | |
700 | dev->rx_buf = buf; | |
701 | return; | |
702 | } else | |
703 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
704 | } | |
705 | } | |
706 | ||
ce6eb574 SK |
707 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
708 | { | |
709 | unsigned long abort_source = dev->abort_source; | |
710 | int i; | |
711 | ||
6d1ea0f6 | 712 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 713 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
714 | dev_dbg(dev->dev, |
715 | "%s: %s\n", __func__, abort_sources[i]); | |
716 | return -EREMOTEIO; | |
717 | } | |
718 | ||
984b3f57 | 719 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
720 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
721 | ||
722 | if (abort_source & DW_IC_TX_ARB_LOST) | |
723 | return -EAGAIN; | |
ce6eb574 SK |
724 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
725 | return -EINVAL; /* wrong msgs[] data */ | |
726 | else | |
727 | return -EIO; | |
728 | } | |
729 | ||
1ab52cf9 | 730 | /* |
89119f08 | 731 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
1ab52cf9 | 732 | */ |
d80d1341 | 733 | static int |
1ab52cf9 BS |
734 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
735 | { | |
736 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
737 | int ret; | |
738 | ||
739 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
740 | ||
18dbdda8 | 741 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 | 742 | |
16735d02 | 743 | reinit_completion(&dev->cmd_complete); |
1ab52cf9 BS |
744 | dev->msgs = msgs; |
745 | dev->msgs_num = num; | |
746 | dev->cmd_err = 0; | |
747 | dev->msg_write_idx = 0; | |
748 | dev->msg_read_idx = 0; | |
749 | dev->msg_err = 0; | |
750 | dev->status = STATUS_IDLE; | |
ce6eb574 | 751 | dev->abort_source = 0; |
e6f34cea | 752 | dev->rx_outstanding = 0; |
1ab52cf9 | 753 | |
8c5660bb LDM |
754 | ret = i2c_dw_acquire_lock(dev); |
755 | if (ret) | |
756 | goto done_nolock; | |
c0601d28 | 757 | |
1ab52cf9 BS |
758 | ret = i2c_dw_wait_bus_not_busy(dev); |
759 | if (ret < 0) | |
760 | goto done; | |
761 | ||
762 | /* start the transfers */ | |
81e798b7 | 763 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
764 | |
765 | /* wait for tx to complete */ | |
d0bcd8df | 766 | if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { |
1ab52cf9 | 767 | dev_err(dev->dev, "controller timed out\n"); |
38d7fade | 768 | /* i2c_dw_init implicitly disables the adapter */ |
1ab52cf9 BS |
769 | i2c_dw_init(dev); |
770 | ret = -ETIMEDOUT; | |
771 | goto done; | |
e42dba56 | 772 | } |
1ab52cf9 | 773 | |
89119f08 JN |
774 | /* |
775 | * We must disable the adapter before returning and signaling the end | |
776 | * of the current transfer. Otherwise the hardware might continue | |
777 | * generating interrupts which in turn causes a race condition with | |
778 | * the following transfer. Needs some more investigation if the | |
779 | * additional interrupts are a hardware bug or this driver doesn't | |
780 | * handle them correctly yet. | |
781 | */ | |
782 | __i2c_dw_enable(dev, false); | |
783 | ||
1ab52cf9 BS |
784 | if (dev->msg_err) { |
785 | ret = dev->msg_err; | |
786 | goto done; | |
787 | } | |
788 | ||
789 | /* no error */ | |
2bf413d5 | 790 | if (likely(!dev->cmd_err && !dev->status)) { |
1ab52cf9 BS |
791 | ret = num; |
792 | goto done; | |
793 | } | |
794 | ||
795 | /* We have an error */ | |
796 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
797 | ret = i2c_dw_handle_tx_abort(dev); |
798 | goto done; | |
1ab52cf9 | 799 | } |
2bf413d5 RK |
800 | |
801 | if (dev->status) | |
802 | dev_err(dev->dev, | |
803 | "transfer terminated early - interrupt latency too high?\n"); | |
804 | ||
1ab52cf9 BS |
805 | ret = -EIO; |
806 | ||
807 | done: | |
8c5660bb | 808 | i2c_dw_release_lock(dev); |
c0601d28 DB |
809 | |
810 | done_nolock: | |
43452335 MW |
811 | pm_runtime_mark_last_busy(dev->dev); |
812 | pm_runtime_put_autosuspend(dev->dev); | |
1ab52cf9 BS |
813 | |
814 | return ret; | |
815 | } | |
816 | ||
d80d1341 | 817 | static u32 i2c_dw_func(struct i2c_adapter *adap) |
1ab52cf9 | 818 | { |
2fa8326b DB |
819 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
820 | return dev->functionality; | |
1ab52cf9 | 821 | } |
d80d1341 JN |
822 | |
823 | static struct i2c_algorithm i2c_dw_algo = { | |
824 | .master_xfer = i2c_dw_xfer, | |
825 | .functionality = i2c_dw_func, | |
826 | }; | |
1ab52cf9 | 827 | |
e28000a3 SK |
828 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
829 | { | |
830 | u32 stat; | |
831 | ||
832 | /* | |
833 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
834 | * Ths unmasked raw version of interrupt status bits are available | |
835 | * in the IC_RAW_INTR_STAT register. | |
836 | * | |
837 | * That is, | |
2373f6b9 | 838 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 839 | * equals to, |
2373f6b9 | 840 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
841 | * |
842 | * The raw version might be useful for debugging purposes. | |
843 | */ | |
7f279601 | 844 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
845 | |
846 | /* | |
847 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
848 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 849 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
850 | * |
851 | * Instead, use the separately-prepared IC_CLR_* registers. | |
852 | */ | |
853 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 854 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 855 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 856 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 857 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 858 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 859 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 860 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
861 | if (stat & DW_IC_INTR_TX_ABRT) { |
862 | /* | |
863 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
864 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
865 | */ | |
7f279601 JHD |
866 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
867 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
868 | } |
869 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 870 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 871 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 872 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 873 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 874 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 875 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 876 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 877 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 878 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
879 | |
880 | return stat; | |
881 | } | |
882 | ||
1ab52cf9 BS |
883 | /* |
884 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
885 | * occurs. | |
886 | */ | |
d80d1341 | 887 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
1ab52cf9 BS |
888 | { |
889 | struct dw_i2c_dev *dev = dev_id; | |
af06cf6c DB |
890 | u32 stat, enabled; |
891 | ||
892 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
893 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
fb427466 | 894 | dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat); |
af06cf6c DB |
895 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) |
896 | return IRQ_NONE; | |
1ab52cf9 | 897 | |
e28000a3 | 898 | stat = i2c_dw_read_clear_intrbits(dev); |
e28000a3 | 899 | |
1ab52cf9 | 900 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
901 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
902 | dev->status = STATUS_IDLE; | |
597fe310 SK |
903 | |
904 | /* | |
905 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
906 | * buffers are flushed. Make sure to skip them. | |
907 | */ | |
7f279601 | 908 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 909 | goto tx_aborted; |
07745399 SK |
910 | } |
911 | ||
21a89d41 | 912 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 913 | i2c_dw_read(dev); |
21a89d41 SK |
914 | |
915 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 916 | i2c_dw_xfer_msg(dev); |
07745399 SK |
917 | |
918 | /* | |
919 | * No need to modify or disable the interrupt mask here. | |
920 | * i2c_dw_xfer_msg() will take care of it according to | |
921 | * the current transmit status. | |
922 | */ | |
1ab52cf9 | 923 | |
597fe310 | 924 | tx_aborted: |
89119f08 | 925 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 | 926 | complete(&dev->cmd_complete); |
89119f08 | 927 | else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) { |
2d244c81 XY |
928 | /* workaround to trigger pending interrupt */ |
929 | stat = dw_readl(dev, DW_IC_INTR_MASK); | |
930 | i2c_dw_disable_int(dev); | |
931 | dw_writel(dev, stat, DW_IC_INTR_MASK); | |
932 | } | |
1ab52cf9 BS |
933 | |
934 | return IRQ_HANDLED; | |
935 | } | |
f3fa9f3d | 936 | |
18dbdda8 DB |
937 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
938 | { | |
f3fa9f3d | 939 | /* Disable controller */ |
2702ea7d | 940 | __i2c_dw_enable_and_wait(dev, false); |
f3fa9f3d DB |
941 | |
942 | /* Disable all interupts */ | |
943 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
944 | dw_readl(dev, DW_IC_CLR_INTR); | |
945 | } | |
e68bb91b | 946 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
f3fa9f3d | 947 | |
f3fa9f3d DB |
948 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) |
949 | { | |
950 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
951 | } | |
e68bb91b | 952 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
f3fa9f3d DB |
953 | |
954 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) | |
955 | { | |
956 | return dw_readl(dev, DW_IC_COMP_PARAM_1); | |
957 | } | |
e68bb91b | 958 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |
9dd3162d | 959 | |
d80d1341 JN |
960 | int i2c_dw_probe(struct dw_i2c_dev *dev) |
961 | { | |
962 | struct i2c_adapter *adap = &dev->adapter; | |
963 | int r; | |
964 | ||
965 | init_completion(&dev->cmd_complete); | |
d80d1341 JN |
966 | |
967 | r = i2c_dw_init(dev); | |
968 | if (r) | |
969 | return r; | |
970 | ||
971 | snprintf(adap->name, sizeof(adap->name), | |
972 | "Synopsys DesignWare I2C adapter"); | |
8d22f309 | 973 | adap->retries = 3; |
d80d1341 JN |
974 | adap->algo = &i2c_dw_algo; |
975 | adap->dev.parent = dev->dev; | |
976 | i2c_set_adapdata(adap, dev); | |
977 | ||
978 | i2c_dw_disable_int(dev); | |
08c6e8cc AS |
979 | r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, |
980 | IRQF_SHARED | IRQF_COND_SUSPEND, | |
d80d1341 JN |
981 | dev_name(dev->dev), dev); |
982 | if (r) { | |
983 | dev_err(dev->dev, "failure requesting irq %i: %d\n", | |
984 | dev->irq, r); | |
985 | return r; | |
986 | } | |
987 | ||
cd998ded JN |
988 | /* |
989 | * Increment PM usage count during adapter registration in order to | |
990 | * avoid possible spurious runtime suspend when adapter device is | |
991 | * registered to the device core and immediate resume in case bus has | |
992 | * registered I2C slaves that do I2C transfers in their probe. | |
993 | */ | |
994 | pm_runtime_get_noresume(dev->dev); | |
d80d1341 JN |
995 | r = i2c_add_numbered_adapter(adap); |
996 | if (r) | |
997 | dev_err(dev->dev, "failure adding adapter: %d\n", r); | |
cd998ded | 998 | pm_runtime_put_noidle(dev->dev); |
d80d1341 JN |
999 | |
1000 | return r; | |
1001 | } | |
1002 | EXPORT_SYMBOL_GPL(i2c_dw_probe); | |
1003 | ||
9dd3162d MW |
1004 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); |
1005 | MODULE_LICENSE("GPL"); |