[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-designware-pcidrv.c

/*
 * Synopsys DesignWare I2C adapter driver (master only).
 *
 * Based on the TI DAVINCI I2C adapter driver.
 *
 * Copyright (C) 2006 Texas Instruments.
 * Copyright (C) 2007 MontaVista Software Inc.
 * Copyright (C) 2009 Provigent Ltd.
 * Copyright (C) 2011 Intel corporation.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include "i2c-designware-core.h"

#define DRIVER_NAME "i2c-designware-pci"

enum dw_pci_ctl_id_t {
	moorestown_0,
	moorestown_1,
	moorestown_2,

	medfield_0,
	medfield_1,
	medfield_2,
	medfield_3,
	medfield_4,
	medfield_5,

	baytrail,
};

struct dw_scl_sda_cfg {
	u32 ss_hcnt;
	u32 fs_hcnt;
	u32 ss_lcnt;
	u32 fs_lcnt;
	u32 sda_hold;
};

struct dw_pci_controller {
	u32 bus_num;
	u32 bus_cfg;
	u32 tx_fifo_depth;
	u32 rx_fifo_depth;
	u32 clk_khz;
	u32 functionality;
	struct dw_scl_sda_cfg *scl_sda_cfg;
};

#define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |			\
				DW_IC_CON_SLAVE_DISABLE |	\
				DW_IC_CON_RESTART_EN)

#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |			\
					I2C_FUNC_SMBUS_BYTE |		\
					I2C_FUNC_SMBUS_BYTE_DATA |	\
					I2C_FUNC_SMBUS_WORD_DATA |	\
					I2C_FUNC_SMBUS_I2C_BLOCK)

/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
	.ss_hcnt = 0x200,
	.fs_hcnt = 0x55,
	.ss_lcnt = 0x200,
	.fs_lcnt = 0x99,
	.sda_hold = 0x6,
};

static struct  dw_pci_controller  dw_pci_controllers[] = {
	[moorestown_0] = {
		.bus_num     = 0,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[moorestown_1] = {
		.bus_num     = 1,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[moorestown_2] = {
		.bus_num     = 2,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_0] = {
		.bus_num     = 0,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_1] = {
		.bus_num     = 1,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_2] = {
		.bus_num     = 2,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_3] = {
		.bus_num     = 3,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_4] = {
		.bus_num     = 4,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[medfield_5] = {
		.bus_num     = 5,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz      = 25000,
	},
	[baytrail] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.clk_khz = 100000,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.scl_sda_cfg = &byt_config,
	},
};
static struct i2c_algorithm i2c_dw_algo = {
	.master_xfer	= i2c_dw_xfer,
	.functionality	= i2c_dw_func,
};

#ifdef CONFIG_PM
static int i2c_dw_pci_suspend(struct device *dev)
{
	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);

	i2c_dw_disable(pci_get_drvdata(pdev));
	return 0;
}

static int i2c_dw_pci_resume(struct device *dev)
{
	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);

	return i2c_dw_init(pci_get_drvdata(pdev));
}
#endif

static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
			    i2c_dw_pci_resume, NULL);

static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
{
	return dev->controller->clk_khz;
}

static int i2c_dw_pci_probe(struct pci_dev *pdev,
			    const struct pci_device_id *id)
{
	struct dw_i2c_dev *dev;
	struct i2c_adapter *adap;
	int r;
	struct  dw_pci_controller *controller;
	struct dw_scl_sda_cfg *cfg;

	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
		dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
			id->driver_data);
		return -EINVAL;
	}

	controller = &dw_pci_controllers[id->driver_data];

	r = pcim_enable_device(pdev);
	if (r) {
		dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
			r);
		return r;
	}

	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
	if (r) {
		dev_err(&pdev->dev, "I/O memory remapping failed\n");
		return r;
	}

	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
	if (!dev)
		return -ENOMEM;

	init_completion(&dev->cmd_complete);
	mutex_init(&dev->lock);
	dev->clk = NULL;
	dev->controller = controller;
	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
	dev->base = pcim_iomap_table(pdev)[0];
	dev->dev = &pdev->dev;
	dev->functionality = controller->functionality |
				DW_DEFAULT_FUNCTIONALITY;

	dev->master_cfg =  controller->bus_cfg;
	if (controller->scl_sda_cfg) {
		cfg = controller->scl_sda_cfg;
		dev->ss_hcnt = cfg->ss_hcnt;
		dev->fs_hcnt = cfg->fs_hcnt;
		dev->ss_lcnt = cfg->ss_lcnt;
		dev->fs_lcnt = cfg->fs_lcnt;
		dev->sda_hold_time = cfg->sda_hold;
	}

	pci_set_drvdata(pdev, dev);

	dev->tx_fifo_depth = controller->tx_fifo_depth;
	dev->rx_fifo_depth = controller->rx_fifo_depth;
	r = i2c_dw_init(dev);
	if (r)
		return r;

	adap = &dev->adapter;
	i2c_set_adapdata(adap, dev);
	adap->owner = THIS_MODULE;
	adap->class = 0;
	adap->algo = &i2c_dw_algo;
	adap->dev.parent = &pdev->dev;
	adap->nr = controller->bus_num;

	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");

	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
			adap->name, dev);
	if (r) {
		dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
		return r;
	}

	i2c_dw_disable_int(dev);
	i2c_dw_clear_int(dev);
	r = i2c_add_numbered_adapter(adap);
	if (r) {
		dev_err(&pdev->dev, "failure adding adapter\n");
		return r;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_put_autosuspend(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static void i2c_dw_pci_remove(struct pci_dev *pdev)
{
	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);

	i2c_dw_disable(dev);
	pm_runtime_forbid(&pdev->dev);
	pm_runtime_get_noresume(&pdev->dev);

	i2c_del_adapter(&dev->adapter);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("i2c_designware-pci");

static DEFINE_PCI_DEVICE_TABLE(i2_designware_pci_ids) = {
	/* Moorestown */
	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
	/* Medfield */
	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
	/* Baytrail */
	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
	{ 0,}
};
MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);

static struct pci_driver dw_i2c_driver = {
	.name		= DRIVER_NAME,
	.id_table	= i2_designware_pci_ids,
	.probe		= i2c_dw_pci_probe,
	.remove		= i2c_dw_pci_remove,
	.driver         = {
		.pm     = &i2c_dw_pm_ops,
	},
};

module_pci_driver(dw_i2c_driver);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
MODULE_LICENSE("GPL");
Commit	Line	Data
fe20ff5c DB	1	/*
	2	* Synopsys DesignWare I2C adapter driver (master only).
	3	*
	4	* Based on the TI DAVINCI I2C adapter driver.
	5	*
	6	* Copyright (C) 2006 Texas Instruments.
	7	* Copyright (C) 2007 MontaVista Software Inc.
	8	* Copyright (C) 2009 Provigent Ltd.
	9	* Copyright (C) 2011 Intel corporation.
	10	*
	11	* ----------------------------------------------------------------------------
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License, or
	16	* (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	26	* ----------------------------------------------------------------------------
	27	*
	28	*/
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
	32	#include <linux/delay.h>
	33	#include <linux/i2c.h>
	34	#include <linux/errno.h>
	35	#include <linux/sched.h>
	36	#include <linux/err.h>
	37	#include <linux/interrupt.h>
	38	#include <linux/io.h>
	39	#include <linux/slab.h>
	40	#include <linux/pci.h>
18dbdda8	41	#include <linux/pm_runtime.h>
fe20ff5c DB	42	#include "i2c-designware-core.h"
	43
	44	#define DRIVER_NAME "i2c-designware-pci"
	45
	46	enum dw_pci_ctl_id_t {
	47	moorestown_0,
	48	moorestown_1,
	49	moorestown_2,
	50
	51	medfield_0,
	52	medfield_1,
	53	medfield_2,
	54	medfield_3,
	55	medfield_4,
	56	medfield_5,
089c729a MW	57
089c729a MW	58	baytrail,
fe20ff5c DB	59	};
fe20ff5c DB	60
8efd1e9e CCE	61	struct dw_scl_sda_cfg {
	62	u32 ss_hcnt;
	63	u32 fs_hcnt;
	64	u32 ss_lcnt;
	65	u32 fs_lcnt;
	66	u32 sda_hold;
	67	};
	68
fe20ff5c DB	69	struct dw_pci_controller {
	70	u32 bus_num;
	71	u32 bus_cfg;
	72	u32 tx_fifo_depth;
	73	u32 rx_fifo_depth;
	74	u32 clk_khz;
ceccd298	75	u32 functionality;
8efd1e9e	76	struct dw_scl_sda_cfg *scl_sda_cfg;
fe20ff5c DB	77	};
	78
	79	#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER \| \
	80	DW_IC_CON_SLAVE_DISABLE \| \
	81	DW_IC_CON_RESTART_EN)
	82
ceccd298 CCE	83	#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C \| \
	84	I2C_FUNC_SMBUS_BYTE \| \
	85	I2C_FUNC_SMBUS_BYTE_DATA \| \
	86	I2C_FUNC_SMBUS_WORD_DATA \| \
	87	I2C_FUNC_SMBUS_I2C_BLOCK)
	88
8efd1e9e CCE	89	/* BayTrail HCNT/LCNT/SDA hold time */
	90	static struct dw_scl_sda_cfg byt_config = {
	91	.ss_hcnt = 0x200,
	92	.fs_hcnt = 0x55,
	93	.ss_lcnt = 0x200,
	94	.fs_lcnt = 0x99,
	95	.sda_hold = 0x6,
	96	};
	97
fe20ff5c DB	98	static struct dw_pci_controller dw_pci_controllers[] = {
	99	[moorestown_0] = {
	100	.bus_num = 0,
	101	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	102	.tx_fifo_depth = 32,
	103	.rx_fifo_depth = 32,
	104	.clk_khz = 25000,
	105	},
	106	[moorestown_1] = {
	107	.bus_num = 1,
	108	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	109	.tx_fifo_depth = 32,
	110	.rx_fifo_depth = 32,
	111	.clk_khz = 25000,
	112	},
	113	[moorestown_2] = {
	114	.bus_num = 2,
	115	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	116	.tx_fifo_depth = 32,
	117	.rx_fifo_depth = 32,
	118	.clk_khz = 25000,
	119	},
	120	[medfield_0] = {
	121	.bus_num = 0,
	122	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	123	.tx_fifo_depth = 32,
	124	.rx_fifo_depth = 32,
	125	.clk_khz = 25000,
	126	},
	127	[medfield_1] = {
	128	.bus_num = 1,
	129	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	130	.tx_fifo_depth = 32,
	131	.rx_fifo_depth = 32,
	132	.clk_khz = 25000,
	133	},
	134	[medfield_2] = {
	135	.bus_num = 2,
	136	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	137	.tx_fifo_depth = 32,
	138	.rx_fifo_depth = 32,
	139	.clk_khz = 25000,
	140	},
	141	[medfield_3] = {
	142	.bus_num = 3,
	143	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_STD,
	144	.tx_fifo_depth = 32,
	145	.rx_fifo_depth = 32,
	146	.clk_khz = 25000,
	147	},
	148	[medfield_4] = {
	149	.bus_num = 4,
	150	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	151	.tx_fifo_depth = 32,
	152	.rx_fifo_depth = 32,
	153	.clk_khz = 25000,
	154	},
	155	[medfield_5] = {
	156	.bus_num = 5,
	157	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	158	.tx_fifo_depth = 32,
	159	.rx_fifo_depth = 32,
	160	.clk_khz = 25000,
	161	},
089c729a MW	162	[baytrail] = {
	163	.bus_num = -1,
	164	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	165	.tx_fifo_depth = 32,
	166	.rx_fifo_depth = 32,
	167	.clk_khz = 100000,
ceccd298	168	.functionality = I2C_FUNC_10BIT_ADDR,
8efd1e9e	169	.scl_sda_cfg = &byt_config,
089c729a	170	},
fe20ff5c DB	171	};
	172	static struct i2c_algorithm i2c_dw_algo = {
	173	.master_xfer = i2c_dw_xfer,
	174	.functionality = i2c_dw_func,
	175	};
	176
be58eda7	177	#ifdef CONFIG_PM
52c28433	178	static int i2c_dw_pci_suspend(struct device *dev)
18dbdda8	179	{
52c28433	180	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
18dbdda8	181
be58eda7	182	i2c_dw_disable(pci_get_drvdata(pdev));
18dbdda8 DB	183	return 0;
	184	}
	185
52c28433	186	static int i2c_dw_pci_resume(struct device *dev)
18dbdda8	187	{
52c28433	188	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
18dbdda8	189
be58eda7	190	return i2c_dw_init(pci_get_drvdata(pdev));
18dbdda8	191	}
be58eda7	192	#endif
18dbdda8	193
be58eda7 MW	194	static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
be58eda7 MW	195	i2c_dw_pci_resume, NULL);
18dbdda8	196
fe20ff5c DB	197	static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
	198	{
	199	return dev->controller->clk_khz;
	200	}
	201
0b255e92	202	static int i2c_dw_pci_probe(struct pci_dev *pdev,
ca0c1ff5	203	const struct pci_device_id *id)
fe20ff5c DB	204	{
	205	struct dw_i2c_dev *dev;
	206	struct i2c_adapter *adap;
fe20ff5c DB	207	int r;
fe20ff5c DB	208	struct dw_pci_controller *controller;
8efd1e9e	209	struct dw_scl_sda_cfg *cfg;
fe20ff5c DB	210
fe20ff5c DB	211	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
ca0c1ff5	212	dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
fe20ff5c DB	213	id->driver_data);
	214	return -EINVAL;
	215	}
	216
	217	controller = &dw_pci_controllers[id->driver_data];
	218
76cf3fc8	219	r = pcim_enable_device(pdev);
fe20ff5c DB	220	if (r) {
	221	dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
	222	r);
76cf3fc8	223	return r;
fe20ff5c DB	224	}
fe20ff5c DB	225
76cf3fc8	226	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
fe20ff5c	227	if (r) {
fe20ff5c	228	dev_err(&pdev->dev, "I/O memory remapping failed\n");
76cf3fc8	229	return r;
fe20ff5c DB	230	}
fe20ff5c DB	231
76cf3fc8 AS	232	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
	233	if (!dev)
	234	return -ENOMEM;
fe20ff5c DB	235
	236	init_completion(&dev->cmd_complete);
	237	mutex_init(&dev->lock);
	238	dev->clk = NULL;
	239	dev->controller = controller;
	240	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
76cf3fc8 AS	241	dev->base = pcim_iomap_table(pdev)[0];
76cf3fc8 AS	242	dev->dev = &pdev->dev;
ceccd298 CCE	243	dev->functionality = controller->functionality \|
	244	DW_DEFAULT_FUNCTIONALITY;
	245
fe20ff5c	246	dev->master_cfg = controller->bus_cfg;
8efd1e9e CCE	247	if (controller->scl_sda_cfg) {
	248	cfg = controller->scl_sda_cfg;
	249	dev->ss_hcnt = cfg->ss_hcnt;
	250	dev->fs_hcnt = cfg->fs_hcnt;
	251	dev->ss_lcnt = cfg->ss_lcnt;
	252	dev->fs_lcnt = cfg->fs_lcnt;
	253	dev->sda_hold_time = cfg->sda_hold;
	254	}
fe20ff5c DB	255
	256	pci_set_drvdata(pdev, dev);
	257
	258	dev->tx_fifo_depth = controller->tx_fifo_depth;
	259	dev->rx_fifo_depth = controller->rx_fifo_depth;
	260	r = i2c_dw_init(dev);
	261	if (r)
76cf3fc8	262	return r;
fe20ff5c DB	263
	264	adap = &dev->adapter;
	265	i2c_set_adapdata(adap, dev);
	266	adap->owner = THIS_MODULE;
	267	adap->class = 0;
	268	adap->algo = &i2c_dw_algo;
	269	adap->dev.parent = &pdev->dev;
	270	adap->nr = controller->bus_num;
089c729a MW	271
089c729a MW	272	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
fe20ff5c	273
76cf3fc8 AS	274	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
76cf3fc8 AS	275	adap->name, dev);
fe20ff5c DB	276	if (r) {
fe20ff5c DB	277	dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
76cf3fc8	278	return r;
fe20ff5c DB	279	}
	280
	281	i2c_dw_disable_int(dev);
	282	i2c_dw_clear_int(dev);
	283	r = i2c_add_numbered_adapter(adap);
	284	if (r) {
	285	dev_err(&pdev->dev, "failure adding adapter\n");
76cf3fc8	286	return r;
fe20ff5c DB	287	}
fe20ff5c DB	288
43452335 MW	289	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
43452335 MW	290	pm_runtime_use_autosuspend(&pdev->dev);
be58eda7	291	pm_runtime_put_autosuspend(&pdev->dev);
18dbdda8 DB	292	pm_runtime_allow(&pdev->dev);
18dbdda8 DB	293
fe20ff5c	294	return 0;
fe20ff5c DB	295	}
fe20ff5c DB	296
0b255e92	297	static void i2c_dw_pci_remove(struct pci_dev *pdev)
fe20ff5c DB	298	{
	299	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
	300
18dbdda8 DB	301	i2c_dw_disable(dev);
	302	pm_runtime_forbid(&pdev->dev);
	303	pm_runtime_get_noresume(&pdev->dev);
	304
fe20ff5c	305	i2c_del_adapter(&dev->adapter);
fe20ff5c DB	306	}
	307
	308	/* work with hotplug and coldplug */
	309	MODULE_ALIAS("i2c_designware-pci");
	310
3527bd50	311	static DEFINE_PCI_DEVICE_TABLE(i2_designware_pci_ids) = {
fe20ff5c DB	312	/* Moorestown */
	313	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
	314	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
	315	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
	316	/* Medfield */
	317	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
	318	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
	319	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
	320	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
	321	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
	322	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
089c729a MW	323	/* Baytrail */
	324	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
	325	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
	326	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
	327	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
	328	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
	329	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
	330	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
fe20ff5c DB	331	{ 0,}
	332	};
	333	MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
	334
	335	static struct pci_driver dw_i2c_driver = {
	336	.name = DRIVER_NAME,
	337	.id_table = i2_designware_pci_ids,
	338	.probe = i2c_dw_pci_probe,
0b255e92	339	.remove = i2c_dw_pci_remove,
18dbdda8 DB	340	.driver = {
	341	.pm = &i2c_dw_pm_ops,
	342	},
fe20ff5c DB	343	};
fe20ff5c DB	344
56f21788	345	module_pci_driver(dw_i2c_driver);
fe20ff5c DB	346
	347	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	348	MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
	349	MODULE_LICENSE("GPL");