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Commit | Line | Data |
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fe20ff5c DB |
1 | /* |
2 | * Synopsys DesignWare I2C adapter driver (master only). | |
3 | * | |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
45bc35ef | 9 | * Copyright (C) 2011, 2015, 2016 Intel Corporation. |
fe20ff5c DB |
10 | * |
11 | * ---------------------------------------------------------------------------- | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
fe20ff5c DB |
22 | * ---------------------------------------------------------------------------- |
23 | * | |
24 | */ | |
25 | ||
45bc35ef | 26 | #include <linux/acpi.h> |
fe20ff5c | 27 | #include <linux/delay.h> |
fe20ff5c | 28 | #include <linux/err.h> |
45bc35ef AS |
29 | #include <linux/errno.h> |
30 | #include <linux/i2c.h> | |
fe20ff5c DB |
31 | #include <linux/interrupt.h> |
32 | #include <linux/io.h> | |
45bc35ef AS |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
fe20ff5c | 35 | #include <linux/pci.h> |
18dbdda8 | 36 | #include <linux/pm_runtime.h> |
45bc35ef AS |
37 | #include <linux/sched.h> |
38 | #include <linux/slab.h> | |
39 | ||
fe20ff5c DB |
40 | #include "i2c-designware-core.h" |
41 | ||
42 | #define DRIVER_NAME "i2c-designware-pci" | |
43 | ||
44 | enum dw_pci_ctl_id_t { | |
ed1bf034 | 45 | medfield, |
b20551c1 | 46 | merrifield, |
089c729a | 47 | baytrail, |
fd476fa2 | 48 | cherrytrail, |
157a801e | 49 | haswell, |
fe20ff5c DB |
50 | }; |
51 | ||
8efd1e9e CCE |
52 | struct dw_scl_sda_cfg { |
53 | u32 ss_hcnt; | |
54 | u32 fs_hcnt; | |
55 | u32 ss_lcnt; | |
56 | u32 fs_lcnt; | |
57 | u32 sda_hold; | |
58 | }; | |
59 | ||
fe20ff5c DB |
60 | struct dw_pci_controller { |
61 | u32 bus_num; | |
62 | u32 bus_cfg; | |
63 | u32 tx_fifo_depth; | |
64 | u32 rx_fifo_depth; | |
65 | u32 clk_khz; | |
ceccd298 | 66 | u32 functionality; |
fd476fa2 | 67 | u32 flags; |
8efd1e9e | 68 | struct dw_scl_sda_cfg *scl_sda_cfg; |
ed1bf034 | 69 | int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c); |
fe20ff5c DB |
70 | }; |
71 | ||
72 | #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \ | |
73 | DW_IC_CON_SLAVE_DISABLE | \ | |
74 | DW_IC_CON_RESTART_EN) | |
75 | ||
b20551c1 AS |
76 | /* Merrifield HCNT/LCNT/SDA hold time */ |
77 | static struct dw_scl_sda_cfg mrfld_config = { | |
78 | .ss_hcnt = 0x2f8, | |
79 | .fs_hcnt = 0x87, | |
80 | .ss_lcnt = 0x37b, | |
81 | .fs_lcnt = 0x10a, | |
82 | }; | |
83 | ||
8efd1e9e CCE |
84 | /* BayTrail HCNT/LCNT/SDA hold time */ |
85 | static struct dw_scl_sda_cfg byt_config = { | |
86 | .ss_hcnt = 0x200, | |
87 | .fs_hcnt = 0x55, | |
88 | .ss_lcnt = 0x200, | |
89 | .fs_lcnt = 0x99, | |
90 | .sda_hold = 0x6, | |
91 | }; | |
92 | ||
157a801e MW |
93 | /* Haswell HCNT/LCNT/SDA hold time */ |
94 | static struct dw_scl_sda_cfg hsw_config = { | |
95 | .ss_hcnt = 0x01b0, | |
96 | .fs_hcnt = 0x48, | |
97 | .ss_lcnt = 0x01fb, | |
98 | .fs_lcnt = 0xa0, | |
99 | .sda_hold = 0x9, | |
100 | }; | |
101 | ||
ed1bf034 AS |
102 | static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) |
103 | { | |
104 | switch (pdev->device) { | |
105 | case 0x0817: | |
106 | c->bus_cfg &= ~DW_IC_CON_SPEED_MASK; | |
107 | c->bus_cfg |= DW_IC_CON_SPEED_STD; | |
108 | case 0x0818: | |
109 | case 0x0819: | |
110 | c->bus_num = pdev->device - 0x817 + 3; | |
111 | return 0; | |
112 | case 0x082C: | |
113 | case 0x082D: | |
114 | case 0x082E: | |
115 | c->bus_num = pdev->device - 0x82C + 0; | |
116 | return 0; | |
117 | } | |
118 | return -ENODEV; | |
119 | } | |
120 | ||
b20551c1 AS |
121 | static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) |
122 | { | |
123 | /* | |
ec2790e9 AS |
124 | * On Intel Merrifield the user visible i2c busses are enumerated |
125 | * [1..7]. So, we add 1 to shift the default range. Besides that the | |
126 | * first PCI slot provides 4 functions, that's why we have to add 0 to | |
127 | * the first slot and 4 to the next one. | |
b20551c1 AS |
128 | */ |
129 | switch (PCI_SLOT(pdev->devfn)) { | |
130 | case 8: | |
131 | c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1; | |
132 | return 0; | |
133 | case 9: | |
134 | c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1; | |
135 | return 0; | |
136 | } | |
137 | return -ENODEV; | |
138 | } | |
139 | ||
a93ac578 | 140 | static struct dw_pci_controller dw_pci_controllers[] = { |
ed1bf034 AS |
141 | [medfield] = { |
142 | .bus_num = -1, | |
fe20ff5c DB |
143 | .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, |
144 | .tx_fifo_depth = 32, | |
145 | .rx_fifo_depth = 32, | |
531ccabb | 146 | .functionality = I2C_FUNC_10BIT_ADDR, |
fe20ff5c | 147 | .clk_khz = 25000, |
ed1bf034 | 148 | .setup = mfld_setup, |
fe20ff5c | 149 | }, |
b20551c1 AS |
150 | [merrifield] = { |
151 | .bus_num = -1, | |
152 | .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, | |
153 | .tx_fifo_depth = 64, | |
154 | .rx_fifo_depth = 64, | |
531ccabb | 155 | .functionality = I2C_FUNC_10BIT_ADDR, |
b20551c1 AS |
156 | .scl_sda_cfg = &mrfld_config, |
157 | .setup = mrfld_setup, | |
158 | }, | |
089c729a MW |
159 | [baytrail] = { |
160 | .bus_num = -1, | |
161 | .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, | |
162 | .tx_fifo_depth = 32, | |
163 | .rx_fifo_depth = 32, | |
ceccd298 | 164 | .functionality = I2C_FUNC_10BIT_ADDR, |
8efd1e9e | 165 | .scl_sda_cfg = &byt_config, |
089c729a | 166 | }, |
157a801e MW |
167 | [haswell] = { |
168 | .bus_num = -1, | |
169 | .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, | |
170 | .tx_fifo_depth = 32, | |
171 | .rx_fifo_depth = 32, | |
157a801e MW |
172 | .functionality = I2C_FUNC_10BIT_ADDR, |
173 | .scl_sda_cfg = &hsw_config, | |
174 | }, | |
fd476fa2 HG |
175 | [cherrytrail] = { |
176 | .bus_num = -1, | |
177 | .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, | |
178 | .tx_fifo_depth = 32, | |
179 | .rx_fifo_depth = 32, | |
180 | .functionality = I2C_FUNC_10BIT_ADDR, | |
181 | .flags = MODEL_CHERRYTRAIL, | |
182 | .scl_sda_cfg = &byt_config, | |
183 | }, | |
fe20ff5c | 184 | }; |
0409516a | 185 | |
be58eda7 | 186 | #ifdef CONFIG_PM |
52c28433 | 187 | static int i2c_dw_pci_suspend(struct device *dev) |
18dbdda8 | 188 | { |
238c44a7 | 189 | struct pci_dev *pdev = to_pci_dev(dev); |
18dbdda8 | 190 | |
be58eda7 | 191 | i2c_dw_disable(pci_get_drvdata(pdev)); |
18dbdda8 DB |
192 | return 0; |
193 | } | |
194 | ||
52c28433 | 195 | static int i2c_dw_pci_resume(struct device *dev) |
18dbdda8 | 196 | { |
238c44a7 | 197 | struct pci_dev *pdev = to_pci_dev(dev); |
18dbdda8 | 198 | |
be58eda7 | 199 | return i2c_dw_init(pci_get_drvdata(pdev)); |
18dbdda8 | 200 | } |
be58eda7 | 201 | #endif |
18dbdda8 | 202 | |
be58eda7 MW |
203 | static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend, |
204 | i2c_dw_pci_resume, NULL); | |
18dbdda8 | 205 | |
fe20ff5c DB |
206 | static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev) |
207 | { | |
208 | return dev->controller->clk_khz; | |
209 | } | |
210 | ||
0b255e92 | 211 | static int i2c_dw_pci_probe(struct pci_dev *pdev, |
ca0c1ff5 | 212 | const struct pci_device_id *id) |
fe20ff5c DB |
213 | { |
214 | struct dw_i2c_dev *dev; | |
215 | struct i2c_adapter *adap; | |
fe20ff5c | 216 | int r; |
45bc35ef | 217 | struct dw_pci_controller *controller; |
8efd1e9e | 218 | struct dw_scl_sda_cfg *cfg; |
fe20ff5c DB |
219 | |
220 | if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) { | |
ca0c1ff5 | 221 | dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__, |
fe20ff5c DB |
222 | id->driver_data); |
223 | return -EINVAL; | |
224 | } | |
225 | ||
226 | controller = &dw_pci_controllers[id->driver_data]; | |
227 | ||
76cf3fc8 | 228 | r = pcim_enable_device(pdev); |
fe20ff5c DB |
229 | if (r) { |
230 | dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n", | |
231 | r); | |
76cf3fc8 | 232 | return r; |
fe20ff5c DB |
233 | } |
234 | ||
76cf3fc8 | 235 | r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); |
fe20ff5c | 236 | if (r) { |
fe20ff5c | 237 | dev_err(&pdev->dev, "I/O memory remapping failed\n"); |
76cf3fc8 | 238 | return r; |
fe20ff5c DB |
239 | } |
240 | ||
76cf3fc8 AS |
241 | dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL); |
242 | if (!dev) | |
243 | return -ENOMEM; | |
fe20ff5c | 244 | |
fe20ff5c DB |
245 | dev->clk = NULL; |
246 | dev->controller = controller; | |
247 | dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; | |
76cf3fc8 AS |
248 | dev->base = pcim_iomap_table(pdev)[0]; |
249 | dev->dev = &pdev->dev; | |
d80d1341 | 250 | dev->irq = pdev->irq; |
fd476fa2 | 251 | dev->flags |= controller->flags; |
ed1bf034 AS |
252 | |
253 | if (controller->setup) { | |
254 | r = controller->setup(pdev, controller); | |
255 | if (r) | |
256 | return r; | |
257 | } | |
258 | ||
ceccd298 | 259 | dev->functionality = controller->functionality | |
f06122f0 | 260 | DW_IC_DEFAULT_FUNCTIONALITY; |
ceccd298 | 261 | |
a93ac578 | 262 | dev->master_cfg = controller->bus_cfg; |
8efd1e9e CCE |
263 | if (controller->scl_sda_cfg) { |
264 | cfg = controller->scl_sda_cfg; | |
265 | dev->ss_hcnt = cfg->ss_hcnt; | |
266 | dev->fs_hcnt = cfg->fs_hcnt; | |
267 | dev->ss_lcnt = cfg->ss_lcnt; | |
268 | dev->fs_lcnt = cfg->fs_lcnt; | |
269 | dev->sda_hold_time = cfg->sda_hold; | |
270 | } | |
fe20ff5c DB |
271 | |
272 | pci_set_drvdata(pdev, dev); | |
273 | ||
274 | dev->tx_fifo_depth = controller->tx_fifo_depth; | |
275 | dev->rx_fifo_depth = controller->rx_fifo_depth; | |
fe20ff5c DB |
276 | |
277 | adap = &dev->adapter; | |
fe20ff5c DB |
278 | adap->owner = THIS_MODULE; |
279 | adap->class = 0; | |
8eb5c87a | 280 | ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev)); |
fe20ff5c | 281 | adap->nr = controller->bus_num; |
089c729a | 282 | |
d80d1341 JN |
283 | r = i2c_dw_probe(dev); |
284 | if (r) | |
76cf3fc8 | 285 | return r; |
fe20ff5c | 286 | |
43452335 MW |
287 | pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); |
288 | pm_runtime_use_autosuspend(&pdev->dev); | |
be58eda7 | 289 | pm_runtime_put_autosuspend(&pdev->dev); |
18dbdda8 DB |
290 | pm_runtime_allow(&pdev->dev); |
291 | ||
fe20ff5c | 292 | return 0; |
fe20ff5c DB |
293 | } |
294 | ||
0b255e92 | 295 | static void i2c_dw_pci_remove(struct pci_dev *pdev) |
fe20ff5c DB |
296 | { |
297 | struct dw_i2c_dev *dev = pci_get_drvdata(pdev); | |
298 | ||
18dbdda8 DB |
299 | i2c_dw_disable(dev); |
300 | pm_runtime_forbid(&pdev->dev); | |
301 | pm_runtime_get_noresume(&pdev->dev); | |
302 | ||
fe20ff5c | 303 | i2c_del_adapter(&dev->adapter); |
fe20ff5c DB |
304 | } |
305 | ||
306 | /* work with hotplug and coldplug */ | |
307 | MODULE_ALIAS("i2c_designware-pci"); | |
308 | ||
392debf1 | 309 | static const struct pci_device_id i2_designware_pci_ids[] = { |
fe20ff5c | 310 | /* Medfield */ |
ed1bf034 AS |
311 | { PCI_VDEVICE(INTEL, 0x0817), medfield }, |
312 | { PCI_VDEVICE(INTEL, 0x0818), medfield }, | |
313 | { PCI_VDEVICE(INTEL, 0x0819), medfield }, | |
314 | { PCI_VDEVICE(INTEL, 0x082C), medfield }, | |
315 | { PCI_VDEVICE(INTEL, 0x082D), medfield }, | |
316 | { PCI_VDEVICE(INTEL, 0x082E), medfield }, | |
b20551c1 AS |
317 | /* Merrifield */ |
318 | { PCI_VDEVICE(INTEL, 0x1195), merrifield }, | |
319 | { PCI_VDEVICE(INTEL, 0x1196), merrifield }, | |
089c729a MW |
320 | /* Baytrail */ |
321 | { PCI_VDEVICE(INTEL, 0x0F41), baytrail }, | |
322 | { PCI_VDEVICE(INTEL, 0x0F42), baytrail }, | |
323 | { PCI_VDEVICE(INTEL, 0x0F43), baytrail }, | |
324 | { PCI_VDEVICE(INTEL, 0x0F44), baytrail }, | |
325 | { PCI_VDEVICE(INTEL, 0x0F45), baytrail }, | |
326 | { PCI_VDEVICE(INTEL, 0x0F46), baytrail }, | |
327 | { PCI_VDEVICE(INTEL, 0x0F47), baytrail }, | |
157a801e MW |
328 | /* Haswell */ |
329 | { PCI_VDEVICE(INTEL, 0x9c61), haswell }, | |
330 | { PCI_VDEVICE(INTEL, 0x9c62), haswell }, | |
0409516a | 331 | /* Braswell / Cherrytrail */ |
fd476fa2 HG |
332 | { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail }, |
333 | { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail }, | |
334 | { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail }, | |
335 | { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail }, | |
336 | { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail }, | |
337 | { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail }, | |
338 | { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail }, | |
fe20ff5c DB |
339 | { 0,} |
340 | }; | |
341 | MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids); | |
342 | ||
343 | static struct pci_driver dw_i2c_driver = { | |
344 | .name = DRIVER_NAME, | |
345 | .id_table = i2_designware_pci_ids, | |
346 | .probe = i2c_dw_pci_probe, | |
0b255e92 | 347 | .remove = i2c_dw_pci_remove, |
18dbdda8 DB |
348 | .driver = { |
349 | .pm = &i2c_dw_pm_ops, | |
350 | }, | |
fe20ff5c DB |
351 | }; |
352 | ||
56f21788 | 353 | module_pci_driver(dw_i2c_driver); |
fe20ff5c DB |
354 | |
355 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
356 | MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter"); | |
357 | MODULE_LICENSE("GPL"); |