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9f3e065c LO |
1 | /* |
2 | * Synopsys DesignWare I2C adapter driver (slave only). | |
3 | * | |
4 | * Based on the Synopsys DesignWare I2C adapter driver (master). | |
5 | * | |
6 | * Copyright (C) 2016 Synopsys Inc. | |
7 | * | |
8 | * ---------------------------------------------------------------------------- | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * ---------------------------------------------------------------------------- | |
20 | * | |
21 | */ | |
22 | #include <linux/delay.h> | |
23 | #include <linux/err.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/i2c.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pm_runtime.h> | |
30 | ||
31 | #include "i2c-designware-core.h" | |
32 | ||
33 | static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev) | |
34 | { | |
35 | /* Configure Tx/Rx FIFO threshold levels. */ | |
36 | dw_writel(dev, 0, DW_IC_TX_TL); | |
37 | dw_writel(dev, 0, DW_IC_RX_TL); | |
38 | ||
39 | /* Configure the I2C slave. */ | |
40 | dw_writel(dev, dev->slave_cfg, DW_IC_CON); | |
41 | dw_writel(dev, DW_IC_INTR_SLAVE_MASK, DW_IC_INTR_MASK); | |
42 | } | |
43 | ||
44 | /** | |
45 | * i2c_dw_init_slave() - Initialize the designware i2c slave hardware | |
46 | * @dev: device private data | |
47 | * | |
48 | * This function configures and enables the I2C in slave mode. | |
49 | * This function is called during I2C init function, and in case of timeout at | |
50 | * run time. | |
51 | */ | |
21bf440c | 52 | static int i2c_dw_init_slave(struct dw_i2c_dev *dev) |
9f3e065c LO |
53 | { |
54 | u32 sda_falling_time, scl_falling_time; | |
55 | u32 reg, comp_param1; | |
56 | u32 hcnt, lcnt; | |
57 | int ret; | |
58 | ||
59 | ret = i2c_dw_acquire_lock(dev); | |
60 | if (ret) | |
61 | return ret; | |
62 | ||
63 | reg = dw_readl(dev, DW_IC_COMP_TYPE); | |
64 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
65 | /* Configure register endianness access. */ | |
66 | dev->flags |= ACCESS_SWAP; | |
67 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
68 | /* Configure register access mode 16bit. */ | |
69 | dev->flags |= ACCESS_16BIT; | |
70 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
71 | dev_err(dev->dev, | |
72 | "Unknown Synopsys component type: 0x%08x\n", reg); | |
73 | i2c_dw_release_lock(dev); | |
74 | return -ENODEV; | |
75 | } | |
76 | ||
77 | comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); | |
78 | ||
79 | /* Disable the adapter. */ | |
80 | __i2c_dw_enable_and_wait(dev, false); | |
81 | ||
82 | /* Set standard and fast speed deviders for high/low periods. */ | |
83 | sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ | |
84 | scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ | |
85 | ||
86 | /* Set SCL timing parameters for standard-mode. */ | |
87 | if (dev->ss_hcnt && dev->ss_lcnt) { | |
88 | hcnt = dev->ss_hcnt; | |
89 | lcnt = dev->ss_lcnt; | |
90 | } else { | |
91 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), | |
92 | 4000, /* tHD;STA = tHIGH = 4.0 us */ | |
93 | sda_falling_time, | |
94 | 0, /* 0: DW default, 1: Ideal */ | |
95 | 0); /* No offset */ | |
96 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), | |
97 | 4700, /* tLOW = 4.7 us */ | |
98 | scl_falling_time, | |
99 | 0); /* No offset */ | |
100 | } | |
101 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); | |
102 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
103 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
104 | ||
105 | /* Set SCL timing parameters for fast-mode or fast-mode plus. */ | |
106 | if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) { | |
107 | hcnt = dev->fp_hcnt; | |
108 | lcnt = dev->fp_lcnt; | |
109 | } else if (dev->fs_hcnt && dev->fs_lcnt) { | |
110 | hcnt = dev->fs_hcnt; | |
111 | lcnt = dev->fs_lcnt; | |
112 | } else { | |
113 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), | |
114 | 600, /* tHD;STA = tHIGH = 0.6 us */ | |
115 | sda_falling_time, | |
116 | 0, /* 0: DW default, 1: Ideal */ | |
117 | 0); /* No offset */ | |
118 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), | |
119 | 1300, /* tLOW = 1.3 us */ | |
120 | scl_falling_time, | |
121 | 0); /* No offset */ | |
122 | } | |
123 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); | |
124 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
125 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
126 | ||
127 | if ((dev->slave_cfg & DW_IC_CON_SPEED_MASK) == | |
128 | DW_IC_CON_SPEED_HIGH) { | |
129 | if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) | |
130 | != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { | |
131 | dev_err(dev->dev, "High Speed not supported!\n"); | |
132 | dev->slave_cfg &= ~DW_IC_CON_SPEED_MASK; | |
133 | dev->slave_cfg |= DW_IC_CON_SPEED_FAST; | |
134 | } else if (dev->hs_hcnt && dev->hs_lcnt) { | |
135 | hcnt = dev->hs_hcnt; | |
136 | lcnt = dev->hs_lcnt; | |
137 | dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT); | |
138 | dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT); | |
139 | dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n", | |
140 | hcnt, lcnt); | |
141 | } | |
142 | } | |
143 | ||
144 | /* Configure SDA Hold Time if required. */ | |
145 | reg = dw_readl(dev, DW_IC_COMP_VERSION); | |
146 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { | |
147 | if (!dev->sda_hold_time) { | |
148 | /* Keep previous hold time setting if no one set it. */ | |
149 | dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD); | |
150 | } | |
151 | /* | |
152 | * Workaround for avoiding TX arbitration lost in case I2C | |
153 | * slave pulls SDA down "too quickly" after falling egde of | |
154 | * SCL by enabling non-zero SDA RX hold. Specification says it | |
155 | * extends incoming SDA low to high transition while SCL is | |
156 | * high but it apprears to help also above issue. | |
157 | */ | |
158 | if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) | |
159 | dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; | |
160 | dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); | |
161 | } else { | |
162 | dev_warn(dev->dev, | |
163 | "Hardware too old to adjust SDA hold time.\n"); | |
164 | } | |
165 | ||
166 | i2c_dw_configure_fifo_slave(dev); | |
167 | i2c_dw_release_lock(dev); | |
168 | ||
169 | return 0; | |
170 | } | |
9f3e065c LO |
171 | |
172 | static int i2c_dw_reg_slave(struct i2c_client *slave) | |
173 | { | |
174 | struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); | |
175 | ||
176 | if (dev->slave) | |
177 | return -EBUSY; | |
178 | if (slave->flags & I2C_CLIENT_TEN) | |
179 | return -EAFNOSUPPORT; | |
180 | /* | |
181 | * Set slave address in the IC_SAR register, | |
182 | * the address to which the DW_apb_i2c responds. | |
183 | */ | |
184 | __i2c_dw_enable(dev, false); | |
185 | dw_writel(dev, slave->addr, DW_IC_SAR); | |
186 | dev->slave = slave; | |
187 | ||
188 | __i2c_dw_enable(dev, true); | |
189 | ||
190 | dev->cmd_err = 0; | |
191 | dev->msg_write_idx = 0; | |
192 | dev->msg_read_idx = 0; | |
193 | dev->msg_err = 0; | |
194 | dev->status = STATUS_IDLE; | |
195 | dev->abort_source = 0; | |
196 | dev->rx_outstanding = 0; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | static int i2c_dw_unreg_slave(struct i2c_client *slave) | |
202 | { | |
203 | struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); | |
204 | ||
205 | dev->disable_int(dev); | |
206 | dev->disable(dev); | |
207 | dev->slave = NULL; | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev) | |
213 | { | |
214 | u32 stat; | |
215 | ||
216 | /* | |
217 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
218 | * Ths unmasked raw version of interrupt status bits are available | |
219 | * in the IC_RAW_INTR_STAT register. | |
220 | * | |
221 | * That is, | |
222 | * stat = dw_readl(IC_INTR_STAT); | |
223 | * equals to, | |
224 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); | |
225 | * | |
226 | * The raw version might be useful for debugging purposes. | |
227 | */ | |
228 | stat = dw_readl(dev, DW_IC_INTR_STAT); | |
229 | ||
230 | /* | |
231 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
232 | * you'll miss some interrupts, triggered during the period from | |
233 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). | |
234 | * | |
235 | * Instead, use the separately-prepared IC_CLR_* registers. | |
236 | */ | |
237 | if (stat & DW_IC_INTR_TX_ABRT) | |
238 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
239 | if (stat & DW_IC_INTR_RX_UNDER) | |
240 | dw_readl(dev, DW_IC_CLR_RX_UNDER); | |
241 | if (stat & DW_IC_INTR_RX_OVER) | |
242 | dw_readl(dev, DW_IC_CLR_RX_OVER); | |
243 | if (stat & DW_IC_INTR_TX_OVER) | |
244 | dw_readl(dev, DW_IC_CLR_TX_OVER); | |
245 | if (stat & DW_IC_INTR_RX_DONE) | |
246 | dw_readl(dev, DW_IC_CLR_RX_DONE); | |
247 | if (stat & DW_IC_INTR_ACTIVITY) | |
248 | dw_readl(dev, DW_IC_CLR_ACTIVITY); | |
249 | if (stat & DW_IC_INTR_STOP_DET) | |
250 | dw_readl(dev, DW_IC_CLR_STOP_DET); | |
251 | if (stat & DW_IC_INTR_START_DET) | |
252 | dw_readl(dev, DW_IC_CLR_START_DET); | |
253 | if (stat & DW_IC_INTR_GEN_CALL) | |
254 | dw_readl(dev, DW_IC_CLR_GEN_CALL); | |
255 | ||
256 | return stat; | |
257 | } | |
258 | ||
259 | /* | |
260 | * Interrupt service routine. This gets called whenever an I2C slave interrupt | |
261 | * occurs. | |
262 | */ | |
263 | ||
264 | static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev) | |
265 | { | |
266 | u32 raw_stat, stat, enabled; | |
267 | u8 val, slave_activity; | |
268 | ||
269 | stat = dw_readl(dev, DW_IC_INTR_STAT); | |
270 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
271 | raw_stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
272 | slave_activity = ((dw_readl(dev, DW_IC_STATUS) & | |
273 | DW_IC_STATUS_SLAVE_ACTIVITY) >> 6); | |
274 | ||
275 | if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY)) | |
276 | return 0; | |
277 | ||
278 | dev_dbg(dev->dev, | |
9809cb83 | 279 | "%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n", |
9f3e065c LO |
280 | enabled, slave_activity, raw_stat, stat); |
281 | ||
282 | if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET)) | |
283 | i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val); | |
284 | ||
285 | if (stat & DW_IC_INTR_RD_REQ) { | |
286 | if (slave_activity) { | |
287 | if (stat & DW_IC_INTR_RX_FULL) { | |
288 | val = dw_readl(dev, DW_IC_DATA_CMD); | |
289 | ||
290 | if (!i2c_slave_event(dev->slave, | |
291 | I2C_SLAVE_WRITE_RECEIVED, | |
292 | &val)) { | |
293 | dev_vdbg(dev->dev, "Byte %X acked!", | |
294 | val); | |
295 | } | |
296 | dw_readl(dev, DW_IC_CLR_RD_REQ); | |
297 | stat = i2c_dw_read_clear_intrbits_slave(dev); | |
298 | } else { | |
299 | dw_readl(dev, DW_IC_CLR_RD_REQ); | |
300 | dw_readl(dev, DW_IC_CLR_RX_UNDER); | |
301 | stat = i2c_dw_read_clear_intrbits_slave(dev); | |
302 | } | |
303 | if (!i2c_slave_event(dev->slave, | |
304 | I2C_SLAVE_READ_REQUESTED, | |
305 | &val)) | |
306 | dw_writel(dev, val, DW_IC_DATA_CMD); | |
307 | } | |
308 | } | |
309 | ||
310 | if (stat & DW_IC_INTR_RX_DONE) { | |
311 | if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED, | |
312 | &val)) | |
313 | dw_readl(dev, DW_IC_CLR_RX_DONE); | |
314 | ||
315 | i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); | |
316 | stat = i2c_dw_read_clear_intrbits_slave(dev); | |
317 | return 1; | |
318 | } | |
319 | ||
320 | if (stat & DW_IC_INTR_RX_FULL) { | |
321 | val = dw_readl(dev, DW_IC_DATA_CMD); | |
322 | if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED, | |
323 | &val)) | |
324 | dev_vdbg(dev->dev, "Byte %X acked!", val); | |
325 | } else { | |
326 | i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); | |
327 | stat = i2c_dw_read_clear_intrbits_slave(dev); | |
328 | } | |
329 | ||
330 | return 1; | |
331 | } | |
332 | ||
333 | static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id) | |
334 | { | |
335 | struct dw_i2c_dev *dev = dev_id; | |
336 | int ret; | |
337 | ||
338 | i2c_dw_read_clear_intrbits_slave(dev); | |
339 | ret = i2c_dw_irq_handler_slave(dev); | |
340 | if (ret > 0) | |
341 | complete(&dev->cmd_complete); | |
342 | ||
343 | return IRQ_RETVAL(ret); | |
344 | } | |
345 | ||
346 | static struct i2c_algorithm i2c_dw_algo = { | |
347 | .functionality = i2c_dw_func, | |
348 | .reg_slave = i2c_dw_reg_slave, | |
349 | .unreg_slave = i2c_dw_unreg_slave, | |
350 | }; | |
351 | ||
352 | int i2c_dw_probe_slave(struct dw_i2c_dev *dev) | |
353 | { | |
354 | struct i2c_adapter *adap = &dev->adapter; | |
355 | int ret; | |
356 | ||
357 | init_completion(&dev->cmd_complete); | |
358 | ||
359 | dev->init = i2c_dw_init_slave; | |
360 | dev->disable = i2c_dw_disable; | |
361 | dev->disable_int = i2c_dw_disable_int; | |
362 | ||
363 | ret = dev->init(dev); | |
364 | if (ret) | |
365 | return ret; | |
366 | ||
367 | snprintf(adap->name, sizeof(adap->name), | |
368 | "Synopsys DesignWare I2C Slave adapter"); | |
369 | adap->retries = 3; | |
370 | adap->algo = &i2c_dw_algo; | |
371 | adap->dev.parent = dev->dev; | |
372 | i2c_set_adapdata(adap, dev); | |
373 | ||
374 | ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave, | |
375 | IRQF_SHARED, dev_name(dev->dev), dev); | |
376 | if (ret) { | |
377 | dev_err(dev->dev, "failure requesting irq %i: %d\n", | |
378 | dev->irq, ret); | |
379 | return ret; | |
380 | } | |
381 | ||
382 | ret = i2c_add_numbered_adapter(adap); | |
383 | if (ret) | |
384 | dev_err(dev->dev, "failure adding adapter: %d\n", ret); | |
385 | pm_runtime_put_noidle(dev->dev); | |
386 | ||
387 | return ret; | |
388 | } | |
389 | EXPORT_SYMBOL_GPL(i2c_dw_probe_slave); | |
390 | ||
391 | MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>"); | |
392 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter"); | |
393 | MODULE_LICENSE("GPL v2"); |