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1ab52cf9 BS |
1 | /* |
2 | * Synopsys Designware I2C adapter driver (master only). | |
3 | * | |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/i2c.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/io.h> | |
39 | ||
40 | /* | |
41 | * Registers offset | |
42 | */ | |
43 | #define DW_IC_CON 0x0 | |
44 | #define DW_IC_TAR 0x4 | |
45 | #define DW_IC_DATA_CMD 0x10 | |
46 | #define DW_IC_SS_SCL_HCNT 0x14 | |
47 | #define DW_IC_SS_SCL_LCNT 0x18 | |
48 | #define DW_IC_FS_SCL_HCNT 0x1c | |
49 | #define DW_IC_FS_SCL_LCNT 0x20 | |
50 | #define DW_IC_INTR_STAT 0x2c | |
51 | #define DW_IC_INTR_MASK 0x30 | |
e28000a3 | 52 | #define DW_IC_RAW_INTR_STAT 0x34 |
1ab52cf9 | 53 | #define DW_IC_CLR_INTR 0x40 |
e28000a3 SK |
54 | #define DW_IC_CLR_RX_UNDER 0x44 |
55 | #define DW_IC_CLR_RX_OVER 0x48 | |
56 | #define DW_IC_CLR_TX_OVER 0x4c | |
57 | #define DW_IC_CLR_RD_REQ 0x50 | |
58 | #define DW_IC_CLR_TX_ABRT 0x54 | |
59 | #define DW_IC_CLR_RX_DONE 0x58 | |
60 | #define DW_IC_CLR_ACTIVITY 0x5c | |
61 | #define DW_IC_CLR_STOP_DET 0x60 | |
62 | #define DW_IC_CLR_START_DET 0x64 | |
63 | #define DW_IC_CLR_GEN_CALL 0x68 | |
1ab52cf9 BS |
64 | #define DW_IC_ENABLE 0x6c |
65 | #define DW_IC_STATUS 0x70 | |
66 | #define DW_IC_TXFLR 0x74 | |
67 | #define DW_IC_RXFLR 0x78 | |
68 | #define DW_IC_COMP_PARAM_1 0xf4 | |
69 | #define DW_IC_TX_ABRT_SOURCE 0x80 | |
70 | ||
71 | #define DW_IC_CON_MASTER 0x1 | |
72 | #define DW_IC_CON_SPEED_STD 0x2 | |
73 | #define DW_IC_CON_SPEED_FAST 0x4 | |
74 | #define DW_IC_CON_10BITADDR_MASTER 0x10 | |
75 | #define DW_IC_CON_RESTART_EN 0x20 | |
76 | #define DW_IC_CON_SLAVE_DISABLE 0x40 | |
77 | ||
e28000a3 SK |
78 | #define DW_IC_INTR_RX_UNDER 0x001 |
79 | #define DW_IC_INTR_RX_OVER 0x002 | |
80 | #define DW_IC_INTR_RX_FULL 0x004 | |
81 | #define DW_IC_INTR_TX_OVER 0x008 | |
82 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
83 | #define DW_IC_INTR_RD_REQ 0x020 | |
84 | #define DW_IC_INTR_TX_ABRT 0x040 | |
85 | #define DW_IC_INTR_RX_DONE 0x080 | |
86 | #define DW_IC_INTR_ACTIVITY 0x100 | |
1ab52cf9 | 87 | #define DW_IC_INTR_STOP_DET 0x200 |
e28000a3 SK |
88 | #define DW_IC_INTR_START_DET 0x400 |
89 | #define DW_IC_INTR_GEN_CALL 0x800 | |
1ab52cf9 BS |
90 | |
91 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
92 | ||
93 | #define DW_IC_ERR_TX_ABRT 0x1 | |
94 | ||
95 | /* | |
96 | * status codes | |
97 | */ | |
98 | #define STATUS_IDLE 0x0 | |
99 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
100 | #define STATUS_READ_IN_PROGRESS 0x2 | |
101 | ||
102 | #define TIMEOUT 20 /* ms */ | |
103 | ||
104 | /* | |
105 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
106 | * | |
107 | * only expected abort codes are listed here | |
108 | * refer to the datasheet for the full list | |
109 | */ | |
110 | #define ABRT_7B_ADDR_NOACK 0 | |
111 | #define ABRT_10ADDR1_NOACK 1 | |
112 | #define ABRT_10ADDR2_NOACK 2 | |
113 | #define ABRT_TXDATA_NOACK 3 | |
114 | #define ABRT_GCALL_NOACK 4 | |
115 | #define ABRT_GCALL_READ 5 | |
116 | #define ABRT_SBYTE_ACKDET 7 | |
117 | #define ABRT_SBYTE_NORSTRT 9 | |
118 | #define ABRT_10B_RD_NORSTRT 10 | |
119 | #define ARB_MASTER_DIS 11 | |
120 | #define ARB_LOST 12 | |
121 | ||
122 | static char *abort_sources[] = { | |
123 | [ABRT_7B_ADDR_NOACK] = | |
124 | "slave address not acknowledged (7bit mode)", | |
125 | [ABRT_10ADDR1_NOACK] = | |
126 | "first address byte not acknowledged (10bit mode)", | |
127 | [ABRT_10ADDR2_NOACK] = | |
128 | "second address byte not acknowledged (10bit mode)", | |
129 | [ABRT_TXDATA_NOACK] = | |
130 | "data not acknowledged", | |
131 | [ABRT_GCALL_NOACK] = | |
132 | "no acknowledgement for a general call", | |
133 | [ABRT_GCALL_READ] = | |
134 | "read after general call", | |
135 | [ABRT_SBYTE_ACKDET] = | |
136 | "start byte acknowledged", | |
137 | [ABRT_SBYTE_NORSTRT] = | |
138 | "trying to send start byte when restart is disabled", | |
139 | [ABRT_10B_RD_NORSTRT] = | |
140 | "trying to read when restart is disabled (10bit mode)", | |
141 | [ARB_MASTER_DIS] = | |
142 | "trying to use disabled adapter", | |
143 | [ARB_LOST] = | |
144 | "lost arbitration", | |
145 | }; | |
146 | ||
147 | /** | |
148 | * struct dw_i2c_dev - private i2c-designware data | |
149 | * @dev: driver model device node | |
150 | * @base: IO registers pointer | |
151 | * @cmd_complete: tx completion indicator | |
1ab52cf9 BS |
152 | * @lock: protect this struct and IO registers |
153 | * @clk: input reference clock | |
154 | * @cmd_err: run time hadware error code | |
155 | * @msgs: points to an array of messages currently being transfered | |
156 | * @msgs_num: the number of elements in msgs | |
157 | * @msg_write_idx: the element index of the current tx message in the msgs | |
158 | * array | |
159 | * @tx_buf_len: the length of the current tx buffer | |
160 | * @tx_buf: the current tx buffer | |
161 | * @msg_read_idx: the element index of the current rx message in the msgs | |
162 | * array | |
163 | * @rx_buf_len: the length of the current rx buffer | |
164 | * @rx_buf: the current rx buffer | |
165 | * @msg_err: error status of the current transfer | |
166 | * @status: i2c master status, one of STATUS_* | |
167 | * @abort_source: copy of the TX_ABRT_SOURCE register | |
168 | * @irq: interrupt number for the i2c master | |
169 | * @adapter: i2c subsystem adapter node | |
170 | * @tx_fifo_depth: depth of the hardware tx fifo | |
171 | * @rx_fifo_depth: depth of the hardware rx fifo | |
172 | */ | |
173 | struct dw_i2c_dev { | |
174 | struct device *dev; | |
175 | void __iomem *base; | |
176 | struct completion cmd_complete; | |
1ab52cf9 BS |
177 | struct mutex lock; |
178 | struct clk *clk; | |
179 | int cmd_err; | |
180 | struct i2c_msg *msgs; | |
181 | int msgs_num; | |
182 | int msg_write_idx; | |
ed5e1dd5 | 183 | u32 tx_buf_len; |
1ab52cf9 BS |
184 | u8 *tx_buf; |
185 | int msg_read_idx; | |
ed5e1dd5 | 186 | u32 rx_buf_len; |
1ab52cf9 BS |
187 | u8 *rx_buf; |
188 | int msg_err; | |
189 | unsigned int status; | |
ed5e1dd5 | 190 | u32 abort_source; |
1ab52cf9 BS |
191 | int irq; |
192 | struct i2c_adapter adapter; | |
193 | unsigned int tx_fifo_depth; | |
194 | unsigned int rx_fifo_depth; | |
195 | }; | |
196 | ||
d60c7e81 SK |
197 | static u32 |
198 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
199 | { | |
200 | /* | |
201 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
202 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
203 | * will result in violation of the tHD;STA spec. | |
204 | */ | |
205 | if (cond) | |
206 | /* | |
207 | * Conditional expression: | |
208 | * | |
209 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
210 | * | |
211 | * This is based on the DW manuals, and represents an ideal | |
212 | * configuration. The resulting I2C bus speed will be | |
213 | * faster than any of the others. | |
214 | * | |
215 | * If your hardware is free from tHD;STA issue, try this one. | |
216 | */ | |
217 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
218 | else | |
219 | /* | |
220 | * Conditional expression: | |
221 | * | |
222 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
223 | * | |
224 | * This is just experimental rule; the tHD;STA period turned | |
225 | * out to be proportinal to (_HCNT + 3). With this setting, | |
226 | * we could meet both tHIGH and tHD;STA timing specs. | |
227 | * | |
228 | * If unsure, you'd better to take this alternative. | |
229 | * | |
230 | * The reason why we need to take into account "tf" here, | |
231 | * is the same as described in i2c_dw_scl_lcnt(). | |
232 | */ | |
233 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
234 | } | |
235 | ||
236 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
237 | { | |
238 | /* | |
239 | * Conditional expression: | |
240 | * | |
241 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
242 | * | |
243 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
244 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
245 | * In order to meet the tLOW timing spec, we need to take into | |
246 | * account the fall time of SCL signal (tf). Default tf value | |
247 | * should be 0.3 us, for safety. | |
248 | */ | |
249 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
250 | } | |
251 | ||
1ab52cf9 BS |
252 | /** |
253 | * i2c_dw_init() - initialize the designware i2c master hardware | |
254 | * @dev: device private data | |
255 | * | |
256 | * This functions configures and enables the I2C master. | |
257 | * This function is called during I2C init function, and in case of timeout at | |
258 | * run time. | |
259 | */ | |
260 | static void i2c_dw_init(struct dw_i2c_dev *dev) | |
261 | { | |
262 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; | |
d60c7e81 | 263 | u32 ic_con, hcnt, lcnt; |
1ab52cf9 BS |
264 | |
265 | /* Disable the adapter */ | |
ed5e1dd5 | 266 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
267 | |
268 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
269 | |
270 | /* Standard-mode */ | |
271 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
272 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
273 | 3, /* tf = 0.3 us */ | |
274 | 0, /* 0: DW default, 1: Ideal */ | |
275 | 0); /* No offset */ | |
276 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
277 | 47, /* tLOW = 4.7 us */ | |
278 | 3, /* tf = 0.3 us */ | |
279 | 0); /* No offset */ | |
280 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); | |
281 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); | |
282 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
283 | ||
284 | /* Fast-mode */ | |
285 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
286 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
287 | 3, /* tf = 0.3 us */ | |
288 | 0, /* 0: DW default, 1: Ideal */ | |
289 | 0); /* No offset */ | |
290 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
291 | 13, /* tLOW = 1.3 us */ | |
292 | 3, /* tf = 0.3 us */ | |
293 | 0); /* No offset */ | |
294 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); | |
295 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); | |
296 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
1ab52cf9 BS |
297 | |
298 | /* configure the i2c master */ | |
299 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | | |
300 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; | |
ed5e1dd5 | 301 | writel(ic_con, dev->base + DW_IC_CON); |
1ab52cf9 BS |
302 | } |
303 | ||
304 | /* | |
305 | * Waiting for bus not busy | |
306 | */ | |
307 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
308 | { | |
309 | int timeout = TIMEOUT; | |
310 | ||
ed5e1dd5 | 311 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
312 | if (timeout <= 0) { |
313 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
314 | return -ETIMEDOUT; | |
315 | } | |
316 | timeout--; | |
317 | mdelay(1); | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | /* | |
324 | * Initiate low level master read/write transaction. | |
325 | * This function is called from i2c_dw_xfer when starting a transfer. | |
07745399 | 326 | * This function is also called from i2c_dw_isr to continue a transfer |
1ab52cf9 BS |
327 | * that is longer than the size of the TX FIFO. |
328 | */ | |
329 | static void | |
e77cf232 | 330 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 331 | { |
1ab52cf9 | 332 | struct i2c_msg *msgs = dev->msgs; |
ed5e1dd5 SK |
333 | u32 ic_con, intr_mask; |
334 | int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); | |
335 | int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); | |
336 | u32 addr = msgs[dev->msg_write_idx].addr; | |
337 | u32 buf_len = dev->tx_buf_len; | |
1ab52cf9 | 338 | |
c70c5cd3 SK |
339 | intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT; |
340 | ||
1ab52cf9 BS |
341 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
342 | /* Disable the adapter */ | |
ed5e1dd5 | 343 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
344 | |
345 | /* set the slave (target) address */ | |
ed5e1dd5 | 346 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); |
1ab52cf9 BS |
347 | |
348 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
ed5e1dd5 | 349 | ic_con = readl(dev->base + DW_IC_CON); |
1ab52cf9 BS |
350 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
351 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
352 | else | |
353 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
ed5e1dd5 | 354 | writel(ic_con, dev->base + DW_IC_CON); |
1ab52cf9 BS |
355 | |
356 | /* Enable the adapter */ | |
ed5e1dd5 | 357 | writel(1, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
358 | } |
359 | ||
6d2ea487 | 360 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
1ab52cf9 BS |
361 | /* if target address has changed, we need to |
362 | * reprogram the target address in the i2c | |
363 | * adapter when we are done with this transfer | |
364 | */ | |
365 | if (msgs[dev->msg_write_idx].addr != addr) | |
366 | return; | |
367 | ||
368 | if (msgs[dev->msg_write_idx].len == 0) { | |
369 | dev_err(dev->dev, | |
370 | "%s: invalid message length\n", __func__); | |
371 | dev->msg_err = -EINVAL; | |
372 | return; | |
373 | } | |
374 | ||
375 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
376 | /* new i2c_msg */ | |
377 | dev->tx_buf = msgs[dev->msg_write_idx].buf; | |
378 | buf_len = msgs[dev->msg_write_idx].len; | |
379 | } | |
380 | ||
381 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { | |
382 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | |
ed5e1dd5 | 383 | writel(0x100, dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
384 | rx_limit--; |
385 | } else | |
ed5e1dd5 | 386 | writel(*(dev->tx_buf++), |
1ab52cf9 BS |
387 | dev->base + DW_IC_DATA_CMD); |
388 | tx_limit--; buf_len--; | |
389 | } | |
c70c5cd3 SK |
390 | |
391 | dev->tx_buf_len = buf_len; | |
392 | ||
393 | if (buf_len > 0) { | |
394 | /* more bytes to be written */ | |
395 | intr_mask |= DW_IC_INTR_TX_EMPTY; | |
396 | dev->status |= STATUS_WRITE_IN_PROGRESS; | |
397 | break; | |
398 | } else | |
399 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; | |
1ab52cf9 BS |
400 | } |
401 | ||
ed5e1dd5 | 402 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
1ab52cf9 BS |
403 | } |
404 | ||
405 | static void | |
78839bd0 | 406 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 407 | { |
1ab52cf9 | 408 | struct i2c_msg *msgs = dev->msgs; |
ed5e1dd5 SK |
409 | u32 addr = msgs[dev->msg_read_idx].addr; |
410 | int rx_valid = readl(dev->base + DW_IC_RXFLR); | |
1ab52cf9 | 411 | |
6d2ea487 | 412 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 413 | u32 len; |
1ab52cf9 BS |
414 | u8 *buf; |
415 | ||
416 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
417 | continue; | |
418 | ||
419 | /* different i2c client, reprogram the i2c adapter */ | |
420 | if (msgs[dev->msg_read_idx].addr != addr) | |
421 | return; | |
422 | ||
423 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { | |
424 | len = msgs[dev->msg_read_idx].len; | |
425 | buf = msgs[dev->msg_read_idx].buf; | |
426 | } else { | |
427 | len = dev->rx_buf_len; | |
428 | buf = dev->rx_buf; | |
429 | } | |
430 | ||
431 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) | |
ed5e1dd5 | 432 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
433 | |
434 | if (len > 0) { | |
435 | dev->status |= STATUS_READ_IN_PROGRESS; | |
436 | dev->rx_buf_len = len; | |
437 | dev->rx_buf = buf; | |
438 | return; | |
439 | } else | |
440 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
441 | } | |
442 | } | |
443 | ||
444 | /* | |
445 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
446 | */ | |
447 | static int | |
448 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
449 | { | |
450 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
451 | int ret; | |
452 | ||
453 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
454 | ||
455 | mutex_lock(&dev->lock); | |
456 | ||
457 | INIT_COMPLETION(dev->cmd_complete); | |
458 | dev->msgs = msgs; | |
459 | dev->msgs_num = num; | |
460 | dev->cmd_err = 0; | |
461 | dev->msg_write_idx = 0; | |
462 | dev->msg_read_idx = 0; | |
463 | dev->msg_err = 0; | |
464 | dev->status = STATUS_IDLE; | |
465 | ||
466 | ret = i2c_dw_wait_bus_not_busy(dev); | |
467 | if (ret < 0) | |
468 | goto done; | |
469 | ||
470 | /* start the transfers */ | |
e77cf232 | 471 | i2c_dw_xfer_msg(dev); |
1ab52cf9 BS |
472 | |
473 | /* wait for tx to complete */ | |
474 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
475 | if (ret == 0) { | |
476 | dev_err(dev->dev, "controller timed out\n"); | |
477 | i2c_dw_init(dev); | |
478 | ret = -ETIMEDOUT; | |
479 | goto done; | |
480 | } else if (ret < 0) | |
481 | goto done; | |
482 | ||
483 | if (dev->msg_err) { | |
484 | ret = dev->msg_err; | |
485 | goto done; | |
486 | } | |
487 | ||
488 | /* no error */ | |
489 | if (likely(!dev->cmd_err)) { | |
07745399 | 490 | /* Disable the adapter */ |
ed5e1dd5 | 491 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
492 | ret = num; |
493 | goto done; | |
494 | } | |
495 | ||
496 | /* We have an error */ | |
497 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
498 | unsigned long abort_source = dev->abort_source; | |
499 | int i; | |
500 | ||
501 | for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) { | |
502 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); | |
503 | } | |
504 | } | |
505 | ret = -EIO; | |
506 | ||
507 | done: | |
508 | mutex_unlock(&dev->lock); | |
509 | ||
510 | return ret; | |
511 | } | |
512 | ||
513 | static u32 i2c_dw_func(struct i2c_adapter *adap) | |
514 | { | |
515 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; | |
516 | } | |
517 | ||
e28000a3 SK |
518 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
519 | { | |
520 | u32 stat; | |
521 | ||
522 | /* | |
523 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
524 | * Ths unmasked raw version of interrupt status bits are available | |
525 | * in the IC_RAW_INTR_STAT register. | |
526 | * | |
527 | * That is, | |
528 | * stat = readl(IC_INTR_STAT); | |
529 | * equals to, | |
530 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); | |
531 | * | |
532 | * The raw version might be useful for debugging purposes. | |
533 | */ | |
534 | stat = readl(dev->base + DW_IC_INTR_STAT); | |
535 | ||
536 | /* | |
537 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
538 | * you'll miss some interrupts, triggered during the period from | |
539 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). | |
540 | * | |
541 | * Instead, use the separately-prepared IC_CLR_* registers. | |
542 | */ | |
543 | if (stat & DW_IC_INTR_RX_UNDER) | |
544 | readl(dev->base + DW_IC_CLR_RX_UNDER); | |
545 | if (stat & DW_IC_INTR_RX_OVER) | |
546 | readl(dev->base + DW_IC_CLR_RX_OVER); | |
547 | if (stat & DW_IC_INTR_TX_OVER) | |
548 | readl(dev->base + DW_IC_CLR_TX_OVER); | |
549 | if (stat & DW_IC_INTR_RD_REQ) | |
550 | readl(dev->base + DW_IC_CLR_RD_REQ); | |
551 | if (stat & DW_IC_INTR_TX_ABRT) { | |
552 | /* | |
553 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
554 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
555 | */ | |
556 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); | |
557 | readl(dev->base + DW_IC_CLR_TX_ABRT); | |
558 | } | |
559 | if (stat & DW_IC_INTR_RX_DONE) | |
560 | readl(dev->base + DW_IC_CLR_RX_DONE); | |
561 | if (stat & DW_IC_INTR_ACTIVITY) | |
562 | readl(dev->base + DW_IC_CLR_ACTIVITY); | |
563 | if (stat & DW_IC_INTR_STOP_DET) | |
564 | readl(dev->base + DW_IC_CLR_STOP_DET); | |
565 | if (stat & DW_IC_INTR_START_DET) | |
566 | readl(dev->base + DW_IC_CLR_START_DET); | |
567 | if (stat & DW_IC_INTR_GEN_CALL) | |
568 | readl(dev->base + DW_IC_CLR_GEN_CALL); | |
569 | ||
570 | return stat; | |
571 | } | |
572 | ||
1ab52cf9 BS |
573 | /* |
574 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
575 | * occurs. | |
576 | */ | |
577 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |
578 | { | |
579 | struct dw_i2c_dev *dev = dev_id; | |
ed5e1dd5 | 580 | u32 stat; |
1ab52cf9 | 581 | |
e28000a3 | 582 | stat = i2c_dw_read_clear_intrbits(dev); |
1ab52cf9 | 583 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
e28000a3 | 584 | |
1ab52cf9 | 585 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
586 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
587 | dev->status = STATUS_IDLE; | |
07745399 SK |
588 | } |
589 | ||
590 | if (stat & DW_IC_INTR_TX_EMPTY) { | |
591 | i2c_dw_read(dev); | |
592 | i2c_dw_xfer_msg(dev); | |
593 | } | |
594 | ||
595 | /* | |
596 | * No need to modify or disable the interrupt mask here. | |
597 | * i2c_dw_xfer_msg() will take care of it according to | |
598 | * the current transmit status. | |
599 | */ | |
1ab52cf9 | 600 | |
1ab52cf9 BS |
601 | if (stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) |
602 | complete(&dev->cmd_complete); | |
603 | ||
604 | return IRQ_HANDLED; | |
605 | } | |
606 | ||
607 | static struct i2c_algorithm i2c_dw_algo = { | |
608 | .master_xfer = i2c_dw_xfer, | |
609 | .functionality = i2c_dw_func, | |
610 | }; | |
611 | ||
612 | static int __devinit dw_i2c_probe(struct platform_device *pdev) | |
613 | { | |
614 | struct dw_i2c_dev *dev; | |
615 | struct i2c_adapter *adap; | |
91b52cae SK |
616 | struct resource *mem, *ioarea; |
617 | int irq, r; | |
1ab52cf9 BS |
618 | |
619 | /* NOTE: driver uses the static register mapping */ | |
620 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
621 | if (!mem) { | |
622 | dev_err(&pdev->dev, "no mem resource?\n"); | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
91b52cae SK |
626 | irq = platform_get_irq(pdev, 0); |
627 | if (irq < 0) { | |
1ab52cf9 | 628 | dev_err(&pdev->dev, "no irq resource?\n"); |
91b52cae | 629 | return irq; /* -ENXIO */ |
1ab52cf9 BS |
630 | } |
631 | ||
632 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
633 | pdev->name); | |
634 | if (!ioarea) { | |
635 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
636 | return -EBUSY; | |
637 | } | |
638 | ||
639 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); | |
640 | if (!dev) { | |
641 | r = -ENOMEM; | |
642 | goto err_release_region; | |
643 | } | |
644 | ||
645 | init_completion(&dev->cmd_complete); | |
1ab52cf9 BS |
646 | mutex_init(&dev->lock); |
647 | dev->dev = get_device(&pdev->dev); | |
91b52cae | 648 | dev->irq = irq; |
1ab52cf9 BS |
649 | platform_set_drvdata(pdev, dev); |
650 | ||
651 | dev->clk = clk_get(&pdev->dev, NULL); | |
652 | if (IS_ERR(dev->clk)) { | |
653 | r = -ENODEV; | |
654 | goto err_free_mem; | |
655 | } | |
656 | clk_enable(dev->clk); | |
657 | ||
658 | dev->base = ioremap(mem->start, resource_size(mem)); | |
659 | if (dev->base == NULL) { | |
660 | dev_err(&pdev->dev, "failure mapping io resources\n"); | |
661 | r = -EBUSY; | |
662 | goto err_unuse_clocks; | |
663 | } | |
664 | { | |
665 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); | |
666 | ||
667 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; | |
668 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; | |
669 | } | |
670 | i2c_dw_init(dev); | |
671 | ||
ed5e1dd5 | 672 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ |
1ab52cf9 BS |
673 | r = request_irq(dev->irq, i2c_dw_isr, 0, pdev->name, dev); |
674 | if (r) { | |
675 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | |
676 | goto err_iounmap; | |
677 | } | |
678 | ||
679 | adap = &dev->adapter; | |
680 | i2c_set_adapdata(adap, dev); | |
681 | adap->owner = THIS_MODULE; | |
682 | adap->class = I2C_CLASS_HWMON; | |
683 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", | |
684 | sizeof(adap->name)); | |
685 | adap->algo = &i2c_dw_algo; | |
686 | adap->dev.parent = &pdev->dev; | |
687 | ||
688 | adap->nr = pdev->id; | |
689 | r = i2c_add_numbered_adapter(adap); | |
690 | if (r) { | |
691 | dev_err(&pdev->dev, "failure adding adapter\n"); | |
692 | goto err_free_irq; | |
693 | } | |
694 | ||
695 | return 0; | |
696 | ||
697 | err_free_irq: | |
698 | free_irq(dev->irq, dev); | |
699 | err_iounmap: | |
700 | iounmap(dev->base); | |
701 | err_unuse_clocks: | |
702 | clk_disable(dev->clk); | |
703 | clk_put(dev->clk); | |
704 | dev->clk = NULL; | |
705 | err_free_mem: | |
706 | platform_set_drvdata(pdev, NULL); | |
707 | put_device(&pdev->dev); | |
708 | kfree(dev); | |
709 | err_release_region: | |
710 | release_mem_region(mem->start, resource_size(mem)); | |
711 | ||
712 | return r; | |
713 | } | |
714 | ||
715 | static int __devexit dw_i2c_remove(struct platform_device *pdev) | |
716 | { | |
717 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); | |
718 | struct resource *mem; | |
719 | ||
720 | platform_set_drvdata(pdev, NULL); | |
721 | i2c_del_adapter(&dev->adapter); | |
722 | put_device(&pdev->dev); | |
723 | ||
724 | clk_disable(dev->clk); | |
725 | clk_put(dev->clk); | |
726 | dev->clk = NULL; | |
727 | ||
ed5e1dd5 | 728 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
729 | free_irq(dev->irq, dev); |
730 | kfree(dev); | |
731 | ||
732 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
733 | release_mem_region(mem->start, resource_size(mem)); | |
734 | return 0; | |
735 | } | |
736 | ||
737 | /* work with hotplug and coldplug */ | |
738 | MODULE_ALIAS("platform:i2c_designware"); | |
739 | ||
740 | static struct platform_driver dw_i2c_driver = { | |
741 | .remove = __devexit_p(dw_i2c_remove), | |
742 | .driver = { | |
743 | .name = "i2c_designware", | |
744 | .owner = THIS_MODULE, | |
745 | }, | |
746 | }; | |
747 | ||
748 | static int __init dw_i2c_init_driver(void) | |
749 | { | |
750 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); | |
751 | } | |
752 | module_init(dw_i2c_init_driver); | |
753 | ||
754 | static void __exit dw_i2c_exit_driver(void) | |
755 | { | |
756 | platform_driver_unregister(&dw_i2c_driver); | |
757 | } | |
758 | module_exit(dw_i2c_exit_driver); | |
759 | ||
760 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
761 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); | |
762 | MODULE_LICENSE("GPL"); |