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1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/i2c.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/io.h> | |
5a0e3ad6 | 39 | #include <linux/slab.h> |
1ab52cf9 BS |
40 | |
41 | /* | |
42 | * Registers offset | |
43 | */ | |
44 | #define DW_IC_CON 0x0 | |
45 | #define DW_IC_TAR 0x4 | |
46 | #define DW_IC_DATA_CMD 0x10 | |
47 | #define DW_IC_SS_SCL_HCNT 0x14 | |
48 | #define DW_IC_SS_SCL_LCNT 0x18 | |
49 | #define DW_IC_FS_SCL_HCNT 0x1c | |
50 | #define DW_IC_FS_SCL_LCNT 0x20 | |
51 | #define DW_IC_INTR_STAT 0x2c | |
52 | #define DW_IC_INTR_MASK 0x30 | |
e28000a3 | 53 | #define DW_IC_RAW_INTR_STAT 0x34 |
4cb6d1d6 SK |
54 | #define DW_IC_RX_TL 0x38 |
55 | #define DW_IC_TX_TL 0x3c | |
1ab52cf9 | 56 | #define DW_IC_CLR_INTR 0x40 |
e28000a3 SK |
57 | #define DW_IC_CLR_RX_UNDER 0x44 |
58 | #define DW_IC_CLR_RX_OVER 0x48 | |
59 | #define DW_IC_CLR_TX_OVER 0x4c | |
60 | #define DW_IC_CLR_RD_REQ 0x50 | |
61 | #define DW_IC_CLR_TX_ABRT 0x54 | |
62 | #define DW_IC_CLR_RX_DONE 0x58 | |
63 | #define DW_IC_CLR_ACTIVITY 0x5c | |
64 | #define DW_IC_CLR_STOP_DET 0x60 | |
65 | #define DW_IC_CLR_START_DET 0x64 | |
66 | #define DW_IC_CLR_GEN_CALL 0x68 | |
1ab52cf9 BS |
67 | #define DW_IC_ENABLE 0x6c |
68 | #define DW_IC_STATUS 0x70 | |
69 | #define DW_IC_TXFLR 0x74 | |
70 | #define DW_IC_RXFLR 0x78 | |
71 | #define DW_IC_COMP_PARAM_1 0xf4 | |
72 | #define DW_IC_TX_ABRT_SOURCE 0x80 | |
73 | ||
74 | #define DW_IC_CON_MASTER 0x1 | |
75 | #define DW_IC_CON_SPEED_STD 0x2 | |
76 | #define DW_IC_CON_SPEED_FAST 0x4 | |
77 | #define DW_IC_CON_10BITADDR_MASTER 0x10 | |
78 | #define DW_IC_CON_RESTART_EN 0x20 | |
79 | #define DW_IC_CON_SLAVE_DISABLE 0x40 | |
80 | ||
e28000a3 SK |
81 | #define DW_IC_INTR_RX_UNDER 0x001 |
82 | #define DW_IC_INTR_RX_OVER 0x002 | |
83 | #define DW_IC_INTR_RX_FULL 0x004 | |
84 | #define DW_IC_INTR_TX_OVER 0x008 | |
85 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
86 | #define DW_IC_INTR_RD_REQ 0x020 | |
87 | #define DW_IC_INTR_TX_ABRT 0x040 | |
88 | #define DW_IC_INTR_RX_DONE 0x080 | |
89 | #define DW_IC_INTR_ACTIVITY 0x100 | |
1ab52cf9 | 90 | #define DW_IC_INTR_STOP_DET 0x200 |
e28000a3 SK |
91 | #define DW_IC_INTR_START_DET 0x400 |
92 | #define DW_IC_INTR_GEN_CALL 0x800 | |
1ab52cf9 | 93 | |
201d6a70 SK |
94 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
95 | DW_IC_INTR_TX_EMPTY | \ | |
96 | DW_IC_INTR_TX_ABRT | \ | |
97 | DW_IC_INTR_STOP_DET) | |
98 | ||
1ab52cf9 BS |
99 | #define DW_IC_STATUS_ACTIVITY 0x1 |
100 | ||
101 | #define DW_IC_ERR_TX_ABRT 0x1 | |
102 | ||
103 | /* | |
104 | * status codes | |
105 | */ | |
106 | #define STATUS_IDLE 0x0 | |
107 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
108 | #define STATUS_READ_IN_PROGRESS 0x2 | |
109 | ||
110 | #define TIMEOUT 20 /* ms */ | |
111 | ||
112 | /* | |
113 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
114 | * | |
115 | * only expected abort codes are listed here | |
116 | * refer to the datasheet for the full list | |
117 | */ | |
118 | #define ABRT_7B_ADDR_NOACK 0 | |
119 | #define ABRT_10ADDR1_NOACK 1 | |
120 | #define ABRT_10ADDR2_NOACK 2 | |
121 | #define ABRT_TXDATA_NOACK 3 | |
122 | #define ABRT_GCALL_NOACK 4 | |
123 | #define ABRT_GCALL_READ 5 | |
124 | #define ABRT_SBYTE_ACKDET 7 | |
125 | #define ABRT_SBYTE_NORSTRT 9 | |
126 | #define ABRT_10B_RD_NORSTRT 10 | |
ce6eb574 | 127 | #define ABRT_MASTER_DIS 11 |
1ab52cf9 BS |
128 | #define ARB_LOST 12 |
129 | ||
ce6eb574 SK |
130 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
131 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
132 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
133 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
134 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
135 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
136 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
137 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
138 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
139 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
140 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
141 | ||
142 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
143 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
144 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
145 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
146 | DW_IC_TX_ABRT_GCALL_NOACK) | |
147 | ||
1ab52cf9 | 148 | static char *abort_sources[] = { |
a0e06ea6 | 149 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 150 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 151 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 152 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 153 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 154 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 155 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 156 | "data not acknowledged", |
a0e06ea6 | 157 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 158 | "no acknowledgement for a general call", |
a0e06ea6 | 159 | [ABRT_GCALL_READ] = |
1ab52cf9 | 160 | "read after general call", |
a0e06ea6 | 161 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 162 | "start byte acknowledged", |
a0e06ea6 | 163 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 164 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 165 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 166 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 167 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 168 | "trying to use disabled adapter", |
a0e06ea6 | 169 | [ARB_LOST] = |
1ab52cf9 BS |
170 | "lost arbitration", |
171 | }; | |
172 | ||
173 | /** | |
174 | * struct dw_i2c_dev - private i2c-designware data | |
175 | * @dev: driver model device node | |
176 | * @base: IO registers pointer | |
177 | * @cmd_complete: tx completion indicator | |
1ab52cf9 BS |
178 | * @lock: protect this struct and IO registers |
179 | * @clk: input reference clock | |
180 | * @cmd_err: run time hadware error code | |
25985edc | 181 | * @msgs: points to an array of messages currently being transferred |
1ab52cf9 BS |
182 | * @msgs_num: the number of elements in msgs |
183 | * @msg_write_idx: the element index of the current tx message in the msgs | |
184 | * array | |
185 | * @tx_buf_len: the length of the current tx buffer | |
186 | * @tx_buf: the current tx buffer | |
187 | * @msg_read_idx: the element index of the current rx message in the msgs | |
188 | * array | |
189 | * @rx_buf_len: the length of the current rx buffer | |
190 | * @rx_buf: the current rx buffer | |
191 | * @msg_err: error status of the current transfer | |
192 | * @status: i2c master status, one of STATUS_* | |
193 | * @abort_source: copy of the TX_ABRT_SOURCE register | |
194 | * @irq: interrupt number for the i2c master | |
195 | * @adapter: i2c subsystem adapter node | |
196 | * @tx_fifo_depth: depth of the hardware tx fifo | |
197 | * @rx_fifo_depth: depth of the hardware rx fifo | |
198 | */ | |
199 | struct dw_i2c_dev { | |
200 | struct device *dev; | |
201 | void __iomem *base; | |
202 | struct completion cmd_complete; | |
1ab52cf9 BS |
203 | struct mutex lock; |
204 | struct clk *clk; | |
205 | int cmd_err; | |
206 | struct i2c_msg *msgs; | |
207 | int msgs_num; | |
208 | int msg_write_idx; | |
ed5e1dd5 | 209 | u32 tx_buf_len; |
1ab52cf9 BS |
210 | u8 *tx_buf; |
211 | int msg_read_idx; | |
ed5e1dd5 | 212 | u32 rx_buf_len; |
1ab52cf9 BS |
213 | u8 *rx_buf; |
214 | int msg_err; | |
215 | unsigned int status; | |
ed5e1dd5 | 216 | u32 abort_source; |
1ab52cf9 BS |
217 | int irq; |
218 | struct i2c_adapter adapter; | |
219 | unsigned int tx_fifo_depth; | |
220 | unsigned int rx_fifo_depth; | |
221 | }; | |
222 | ||
d60c7e81 SK |
223 | static u32 |
224 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
225 | { | |
226 | /* | |
227 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
228 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
229 | * will result in violation of the tHD;STA spec. | |
230 | */ | |
231 | if (cond) | |
232 | /* | |
233 | * Conditional expression: | |
234 | * | |
235 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
236 | * | |
237 | * This is based on the DW manuals, and represents an ideal | |
238 | * configuration. The resulting I2C bus speed will be | |
239 | * faster than any of the others. | |
240 | * | |
241 | * If your hardware is free from tHD;STA issue, try this one. | |
242 | */ | |
243 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
244 | else | |
245 | /* | |
246 | * Conditional expression: | |
247 | * | |
248 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
249 | * | |
250 | * This is just experimental rule; the tHD;STA period turned | |
251 | * out to be proportinal to (_HCNT + 3). With this setting, | |
252 | * we could meet both tHIGH and tHD;STA timing specs. | |
253 | * | |
254 | * If unsure, you'd better to take this alternative. | |
255 | * | |
256 | * The reason why we need to take into account "tf" here, | |
257 | * is the same as described in i2c_dw_scl_lcnt(). | |
258 | */ | |
259 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
260 | } | |
261 | ||
262 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
263 | { | |
264 | /* | |
265 | * Conditional expression: | |
266 | * | |
267 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
268 | * | |
269 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
270 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
271 | * In order to meet the tLOW timing spec, we need to take into | |
272 | * account the fall time of SCL signal (tf). Default tf value | |
273 | * should be 0.3 us, for safety. | |
274 | */ | |
275 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
276 | } | |
277 | ||
1ab52cf9 BS |
278 | /** |
279 | * i2c_dw_init() - initialize the designware i2c master hardware | |
280 | * @dev: device private data | |
281 | * | |
282 | * This functions configures and enables the I2C master. | |
283 | * This function is called during I2C init function, and in case of timeout at | |
284 | * run time. | |
285 | */ | |
286 | static void i2c_dw_init(struct dw_i2c_dev *dev) | |
287 | { | |
288 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; | |
d60c7e81 | 289 | u32 ic_con, hcnt, lcnt; |
1ab52cf9 BS |
290 | |
291 | /* Disable the adapter */ | |
ed5e1dd5 | 292 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
293 | |
294 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
295 | |
296 | /* Standard-mode */ | |
297 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
298 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
299 | 3, /* tf = 0.3 us */ | |
300 | 0, /* 0: DW default, 1: Ideal */ | |
301 | 0); /* No offset */ | |
302 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
303 | 47, /* tLOW = 4.7 us */ | |
304 | 3, /* tf = 0.3 us */ | |
305 | 0); /* No offset */ | |
306 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); | |
307 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); | |
308 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
309 | ||
310 | /* Fast-mode */ | |
311 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
312 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
313 | 3, /* tf = 0.3 us */ | |
314 | 0, /* 0: DW default, 1: Ideal */ | |
315 | 0); /* No offset */ | |
316 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
317 | 13, /* tLOW = 1.3 us */ | |
318 | 3, /* tf = 0.3 us */ | |
319 | 0); /* No offset */ | |
320 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); | |
321 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); | |
322 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
1ab52cf9 | 323 | |
4cb6d1d6 SK |
324 | /* Configure Tx/Rx FIFO threshold levels */ |
325 | writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL); | |
326 | writel(0, dev->base + DW_IC_RX_TL); | |
327 | ||
1ab52cf9 BS |
328 | /* configure the i2c master */ |
329 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | | |
330 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; | |
ed5e1dd5 | 331 | writel(ic_con, dev->base + DW_IC_CON); |
1ab52cf9 BS |
332 | } |
333 | ||
334 | /* | |
335 | * Waiting for bus not busy | |
336 | */ | |
337 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
338 | { | |
339 | int timeout = TIMEOUT; | |
340 | ||
ed5e1dd5 | 341 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
342 | if (timeout <= 0) { |
343 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
344 | return -ETIMEDOUT; | |
345 | } | |
346 | timeout--; | |
347 | mdelay(1); | |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
81e798b7 SK |
353 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
354 | { | |
355 | struct i2c_msg *msgs = dev->msgs; | |
356 | u32 ic_con; | |
357 | ||
358 | /* Disable the adapter */ | |
359 | writel(0, dev->base + DW_IC_ENABLE); | |
360 | ||
361 | /* set the slave (target) address */ | |
362 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); | |
363 | ||
364 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
365 | ic_con = readl(dev->base + DW_IC_CON); | |
366 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) | |
367 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
368 | else | |
369 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
370 | writel(ic_con, dev->base + DW_IC_CON); | |
371 | ||
372 | /* Enable the adapter */ | |
373 | writel(1, dev->base + DW_IC_ENABLE); | |
201d6a70 SK |
374 | |
375 | /* Enable interrupts */ | |
376 | writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK); | |
81e798b7 SK |
377 | } |
378 | ||
1ab52cf9 | 379 | /* |
201d6a70 SK |
380 | * Initiate (and continue) low level master read/write transaction. |
381 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
382 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
383 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 BS |
384 | */ |
385 | static void | |
e77cf232 | 386 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 387 | { |
1ab52cf9 | 388 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 389 | u32 intr_mask; |
ae72222d | 390 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
391 | u32 addr = msgs[dev->msg_write_idx].addr; |
392 | u32 buf_len = dev->tx_buf_len; | |
26ea15b1 | 393 | u8 *buf = dev->tx_buf;; |
1ab52cf9 | 394 | |
201d6a70 | 395 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 396 | |
6d2ea487 | 397 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
398 | /* |
399 | * if target address has changed, we need to | |
1ab52cf9 BS |
400 | * reprogram the target address in the i2c |
401 | * adapter when we are done with this transfer | |
402 | */ | |
8f588e40 SK |
403 | if (msgs[dev->msg_write_idx].addr != addr) { |
404 | dev_err(dev->dev, | |
405 | "%s: invalid target address\n", __func__); | |
406 | dev->msg_err = -EINVAL; | |
407 | break; | |
408 | } | |
1ab52cf9 BS |
409 | |
410 | if (msgs[dev->msg_write_idx].len == 0) { | |
411 | dev_err(dev->dev, | |
412 | "%s: invalid message length\n", __func__); | |
413 | dev->msg_err = -EINVAL; | |
8f588e40 | 414 | break; |
1ab52cf9 BS |
415 | } |
416 | ||
417 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
418 | /* new i2c_msg */ | |
26ea15b1 | 419 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 BS |
420 | buf_len = msgs[dev->msg_write_idx].len; |
421 | } | |
422 | ||
ae72222d SK |
423 | tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); |
424 | rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); | |
425 | ||
1ab52cf9 BS |
426 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
427 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | |
ed5e1dd5 | 428 | writel(0x100, dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
429 | rx_limit--; |
430 | } else | |
26ea15b1 | 431 | writel(*buf++, dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
432 | tx_limit--; buf_len--; |
433 | } | |
c70c5cd3 | 434 | |
26ea15b1 | 435 | dev->tx_buf = buf; |
c70c5cd3 SK |
436 | dev->tx_buf_len = buf_len; |
437 | ||
438 | if (buf_len > 0) { | |
439 | /* more bytes to be written */ | |
c70c5cd3 SK |
440 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
441 | break; | |
69151e53 | 442 | } else |
c70c5cd3 | 443 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
444 | } |
445 | ||
69151e53 SK |
446 | /* |
447 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
448 | * interrupt any more. | |
449 | */ | |
450 | if (dev->msg_write_idx == dev->msgs_num) | |
451 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
452 | ||
8f588e40 SK |
453 | if (dev->msg_err) |
454 | intr_mask = 0; | |
455 | ||
ed5e1dd5 | 456 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
1ab52cf9 BS |
457 | } |
458 | ||
459 | static void | |
78839bd0 | 460 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 461 | { |
1ab52cf9 | 462 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 463 | int rx_valid; |
1ab52cf9 | 464 | |
6d2ea487 | 465 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 466 | u32 len; |
1ab52cf9 BS |
467 | u8 *buf; |
468 | ||
469 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
470 | continue; | |
471 | ||
1ab52cf9 BS |
472 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
473 | len = msgs[dev->msg_read_idx].len; | |
474 | buf = msgs[dev->msg_read_idx].buf; | |
475 | } else { | |
476 | len = dev->rx_buf_len; | |
477 | buf = dev->rx_buf; | |
478 | } | |
479 | ||
ae72222d SK |
480 | rx_valid = readl(dev->base + DW_IC_RXFLR); |
481 | ||
1ab52cf9 | 482 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
ed5e1dd5 | 483 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
484 | |
485 | if (len > 0) { | |
486 | dev->status |= STATUS_READ_IN_PROGRESS; | |
487 | dev->rx_buf_len = len; | |
488 | dev->rx_buf = buf; | |
489 | return; | |
490 | } else | |
491 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
492 | } | |
493 | } | |
494 | ||
ce6eb574 SK |
495 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
496 | { | |
497 | unsigned long abort_source = dev->abort_source; | |
498 | int i; | |
499 | ||
6d1ea0f6 | 500 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 501 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
502 | dev_dbg(dev->dev, |
503 | "%s: %s\n", __func__, abort_sources[i]); | |
504 | return -EREMOTEIO; | |
505 | } | |
506 | ||
984b3f57 | 507 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
508 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
509 | ||
510 | if (abort_source & DW_IC_TX_ARB_LOST) | |
511 | return -EAGAIN; | |
ce6eb574 SK |
512 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
513 | return -EINVAL; /* wrong msgs[] data */ | |
514 | else | |
515 | return -EIO; | |
516 | } | |
517 | ||
1ab52cf9 BS |
518 | /* |
519 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
520 | */ | |
521 | static int | |
522 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
523 | { | |
524 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
525 | int ret; | |
526 | ||
527 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
528 | ||
529 | mutex_lock(&dev->lock); | |
530 | ||
531 | INIT_COMPLETION(dev->cmd_complete); | |
532 | dev->msgs = msgs; | |
533 | dev->msgs_num = num; | |
534 | dev->cmd_err = 0; | |
535 | dev->msg_write_idx = 0; | |
536 | dev->msg_read_idx = 0; | |
537 | dev->msg_err = 0; | |
538 | dev->status = STATUS_IDLE; | |
ce6eb574 | 539 | dev->abort_source = 0; |
1ab52cf9 BS |
540 | |
541 | ret = i2c_dw_wait_bus_not_busy(dev); | |
542 | if (ret < 0) | |
543 | goto done; | |
544 | ||
545 | /* start the transfers */ | |
81e798b7 | 546 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
547 | |
548 | /* wait for tx to complete */ | |
549 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
550 | if (ret == 0) { | |
551 | dev_err(dev->dev, "controller timed out\n"); | |
552 | i2c_dw_init(dev); | |
553 | ret = -ETIMEDOUT; | |
554 | goto done; | |
555 | } else if (ret < 0) | |
556 | goto done; | |
557 | ||
558 | if (dev->msg_err) { | |
559 | ret = dev->msg_err; | |
560 | goto done; | |
561 | } | |
562 | ||
563 | /* no error */ | |
564 | if (likely(!dev->cmd_err)) { | |
07745399 | 565 | /* Disable the adapter */ |
ed5e1dd5 | 566 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
567 | ret = num; |
568 | goto done; | |
569 | } | |
570 | ||
571 | /* We have an error */ | |
572 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
573 | ret = i2c_dw_handle_tx_abort(dev); |
574 | goto done; | |
1ab52cf9 BS |
575 | } |
576 | ret = -EIO; | |
577 | ||
578 | done: | |
579 | mutex_unlock(&dev->lock); | |
580 | ||
581 | return ret; | |
582 | } | |
583 | ||
584 | static u32 i2c_dw_func(struct i2c_adapter *adap) | |
585 | { | |
52d7e430 SK |
586 | return I2C_FUNC_I2C | |
587 | I2C_FUNC_10BIT_ADDR | | |
588 | I2C_FUNC_SMBUS_BYTE | | |
589 | I2C_FUNC_SMBUS_BYTE_DATA | | |
590 | I2C_FUNC_SMBUS_WORD_DATA | | |
591 | I2C_FUNC_SMBUS_I2C_BLOCK; | |
1ab52cf9 BS |
592 | } |
593 | ||
e28000a3 SK |
594 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
595 | { | |
596 | u32 stat; | |
597 | ||
598 | /* | |
599 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
600 | * Ths unmasked raw version of interrupt status bits are available | |
601 | * in the IC_RAW_INTR_STAT register. | |
602 | * | |
603 | * That is, | |
604 | * stat = readl(IC_INTR_STAT); | |
605 | * equals to, | |
606 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); | |
607 | * | |
608 | * The raw version might be useful for debugging purposes. | |
609 | */ | |
610 | stat = readl(dev->base + DW_IC_INTR_STAT); | |
611 | ||
612 | /* | |
613 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
614 | * you'll miss some interrupts, triggered during the period from | |
615 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). | |
616 | * | |
617 | * Instead, use the separately-prepared IC_CLR_* registers. | |
618 | */ | |
619 | if (stat & DW_IC_INTR_RX_UNDER) | |
620 | readl(dev->base + DW_IC_CLR_RX_UNDER); | |
621 | if (stat & DW_IC_INTR_RX_OVER) | |
622 | readl(dev->base + DW_IC_CLR_RX_OVER); | |
623 | if (stat & DW_IC_INTR_TX_OVER) | |
624 | readl(dev->base + DW_IC_CLR_TX_OVER); | |
625 | if (stat & DW_IC_INTR_RD_REQ) | |
626 | readl(dev->base + DW_IC_CLR_RD_REQ); | |
627 | if (stat & DW_IC_INTR_TX_ABRT) { | |
628 | /* | |
629 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
630 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
631 | */ | |
632 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); | |
633 | readl(dev->base + DW_IC_CLR_TX_ABRT); | |
634 | } | |
635 | if (stat & DW_IC_INTR_RX_DONE) | |
636 | readl(dev->base + DW_IC_CLR_RX_DONE); | |
637 | if (stat & DW_IC_INTR_ACTIVITY) | |
638 | readl(dev->base + DW_IC_CLR_ACTIVITY); | |
639 | if (stat & DW_IC_INTR_STOP_DET) | |
640 | readl(dev->base + DW_IC_CLR_STOP_DET); | |
641 | if (stat & DW_IC_INTR_START_DET) | |
642 | readl(dev->base + DW_IC_CLR_START_DET); | |
643 | if (stat & DW_IC_INTR_GEN_CALL) | |
644 | readl(dev->base + DW_IC_CLR_GEN_CALL); | |
645 | ||
646 | return stat; | |
647 | } | |
648 | ||
1ab52cf9 BS |
649 | /* |
650 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
651 | * occurs. | |
652 | */ | |
653 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |
654 | { | |
655 | struct dw_i2c_dev *dev = dev_id; | |
ed5e1dd5 | 656 | u32 stat; |
1ab52cf9 | 657 | |
e28000a3 | 658 | stat = i2c_dw_read_clear_intrbits(dev); |
1ab52cf9 | 659 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
e28000a3 | 660 | |
1ab52cf9 | 661 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
662 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
663 | dev->status = STATUS_IDLE; | |
597fe310 SK |
664 | |
665 | /* | |
666 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
667 | * buffers are flushed. Make sure to skip them. | |
668 | */ | |
669 | writel(0, dev->base + DW_IC_INTR_MASK); | |
670 | goto tx_aborted; | |
07745399 SK |
671 | } |
672 | ||
21a89d41 | 673 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 674 | i2c_dw_read(dev); |
21a89d41 SK |
675 | |
676 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 677 | i2c_dw_xfer_msg(dev); |
07745399 SK |
678 | |
679 | /* | |
680 | * No need to modify or disable the interrupt mask here. | |
681 | * i2c_dw_xfer_msg() will take care of it according to | |
682 | * the current transmit status. | |
683 | */ | |
1ab52cf9 | 684 | |
597fe310 | 685 | tx_aborted: |
8f588e40 | 686 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
687 | complete(&dev->cmd_complete); |
688 | ||
689 | return IRQ_HANDLED; | |
690 | } | |
691 | ||
692 | static struct i2c_algorithm i2c_dw_algo = { | |
693 | .master_xfer = i2c_dw_xfer, | |
694 | .functionality = i2c_dw_func, | |
695 | }; | |
696 | ||
697 | static int __devinit dw_i2c_probe(struct platform_device *pdev) | |
698 | { | |
699 | struct dw_i2c_dev *dev; | |
700 | struct i2c_adapter *adap; | |
91b52cae SK |
701 | struct resource *mem, *ioarea; |
702 | int irq, r; | |
1ab52cf9 BS |
703 | |
704 | /* NOTE: driver uses the static register mapping */ | |
705 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
706 | if (!mem) { | |
707 | dev_err(&pdev->dev, "no mem resource?\n"); | |
708 | return -EINVAL; | |
709 | } | |
710 | ||
91b52cae SK |
711 | irq = platform_get_irq(pdev, 0); |
712 | if (irq < 0) { | |
1ab52cf9 | 713 | dev_err(&pdev->dev, "no irq resource?\n"); |
91b52cae | 714 | return irq; /* -ENXIO */ |
1ab52cf9 BS |
715 | } |
716 | ||
717 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
718 | pdev->name); | |
719 | if (!ioarea) { | |
720 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
721 | return -EBUSY; | |
722 | } | |
723 | ||
724 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); | |
725 | if (!dev) { | |
726 | r = -ENOMEM; | |
727 | goto err_release_region; | |
728 | } | |
729 | ||
730 | init_completion(&dev->cmd_complete); | |
1ab52cf9 BS |
731 | mutex_init(&dev->lock); |
732 | dev->dev = get_device(&pdev->dev); | |
91b52cae | 733 | dev->irq = irq; |
1ab52cf9 BS |
734 | platform_set_drvdata(pdev, dev); |
735 | ||
736 | dev->clk = clk_get(&pdev->dev, NULL); | |
737 | if (IS_ERR(dev->clk)) { | |
738 | r = -ENODEV; | |
739 | goto err_free_mem; | |
740 | } | |
741 | clk_enable(dev->clk); | |
742 | ||
743 | dev->base = ioremap(mem->start, resource_size(mem)); | |
744 | if (dev->base == NULL) { | |
745 | dev_err(&pdev->dev, "failure mapping io resources\n"); | |
746 | r = -EBUSY; | |
747 | goto err_unuse_clocks; | |
748 | } | |
749 | { | |
750 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); | |
751 | ||
752 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; | |
753 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; | |
754 | } | |
755 | i2c_dw_init(dev); | |
756 | ||
ed5e1dd5 | 757 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ |
201d6a70 | 758 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); |
1ab52cf9 BS |
759 | if (r) { |
760 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | |
761 | goto err_iounmap; | |
762 | } | |
763 | ||
764 | adap = &dev->adapter; | |
765 | i2c_set_adapdata(adap, dev); | |
766 | adap->owner = THIS_MODULE; | |
767 | adap->class = I2C_CLASS_HWMON; | |
768 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", | |
769 | sizeof(adap->name)); | |
770 | adap->algo = &i2c_dw_algo; | |
771 | adap->dev.parent = &pdev->dev; | |
772 | ||
773 | adap->nr = pdev->id; | |
774 | r = i2c_add_numbered_adapter(adap); | |
775 | if (r) { | |
776 | dev_err(&pdev->dev, "failure adding adapter\n"); | |
777 | goto err_free_irq; | |
778 | } | |
779 | ||
780 | return 0; | |
781 | ||
782 | err_free_irq: | |
783 | free_irq(dev->irq, dev); | |
784 | err_iounmap: | |
785 | iounmap(dev->base); | |
786 | err_unuse_clocks: | |
787 | clk_disable(dev->clk); | |
788 | clk_put(dev->clk); | |
789 | dev->clk = NULL; | |
790 | err_free_mem: | |
791 | platform_set_drvdata(pdev, NULL); | |
792 | put_device(&pdev->dev); | |
793 | kfree(dev); | |
794 | err_release_region: | |
795 | release_mem_region(mem->start, resource_size(mem)); | |
796 | ||
797 | return r; | |
798 | } | |
799 | ||
800 | static int __devexit dw_i2c_remove(struct platform_device *pdev) | |
801 | { | |
802 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); | |
803 | struct resource *mem; | |
804 | ||
805 | platform_set_drvdata(pdev, NULL); | |
806 | i2c_del_adapter(&dev->adapter); | |
807 | put_device(&pdev->dev); | |
808 | ||
809 | clk_disable(dev->clk); | |
810 | clk_put(dev->clk); | |
811 | dev->clk = NULL; | |
812 | ||
ed5e1dd5 | 813 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
814 | free_irq(dev->irq, dev); |
815 | kfree(dev); | |
816 | ||
817 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
818 | release_mem_region(mem->start, resource_size(mem)); | |
819 | return 0; | |
820 | } | |
821 | ||
822 | /* work with hotplug and coldplug */ | |
823 | MODULE_ALIAS("platform:i2c_designware"); | |
824 | ||
825 | static struct platform_driver dw_i2c_driver = { | |
826 | .remove = __devexit_p(dw_i2c_remove), | |
827 | .driver = { | |
828 | .name = "i2c_designware", | |
829 | .owner = THIS_MODULE, | |
830 | }, | |
831 | }; | |
832 | ||
833 | static int __init dw_i2c_init_driver(void) | |
834 | { | |
835 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); | |
836 | } | |
837 | module_init(dw_i2c_init_driver); | |
838 | ||
839 | static void __exit dw_i2c_exit_driver(void) | |
840 | { | |
841 | platform_driver_unregister(&dw_i2c_driver); | |
842 | } | |
843 | module_exit(dw_i2c_exit_driver); | |
844 | ||
845 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
846 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); | |
847 | MODULE_LICENSE("GPL"); |