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1ab52cf9 BS |
1 | /* |
2 | * Synopsys Designware I2C adapter driver (master only). | |
3 | * | |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/i2c.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/io.h> | |
39 | ||
40 | /* | |
41 | * Registers offset | |
42 | */ | |
43 | #define DW_IC_CON 0x0 | |
44 | #define DW_IC_TAR 0x4 | |
45 | #define DW_IC_DATA_CMD 0x10 | |
46 | #define DW_IC_SS_SCL_HCNT 0x14 | |
47 | #define DW_IC_SS_SCL_LCNT 0x18 | |
48 | #define DW_IC_FS_SCL_HCNT 0x1c | |
49 | #define DW_IC_FS_SCL_LCNT 0x20 | |
50 | #define DW_IC_INTR_STAT 0x2c | |
51 | #define DW_IC_INTR_MASK 0x30 | |
e28000a3 | 52 | #define DW_IC_RAW_INTR_STAT 0x34 |
1ab52cf9 | 53 | #define DW_IC_CLR_INTR 0x40 |
e28000a3 SK |
54 | #define DW_IC_CLR_RX_UNDER 0x44 |
55 | #define DW_IC_CLR_RX_OVER 0x48 | |
56 | #define DW_IC_CLR_TX_OVER 0x4c | |
57 | #define DW_IC_CLR_RD_REQ 0x50 | |
58 | #define DW_IC_CLR_TX_ABRT 0x54 | |
59 | #define DW_IC_CLR_RX_DONE 0x58 | |
60 | #define DW_IC_CLR_ACTIVITY 0x5c | |
61 | #define DW_IC_CLR_STOP_DET 0x60 | |
62 | #define DW_IC_CLR_START_DET 0x64 | |
63 | #define DW_IC_CLR_GEN_CALL 0x68 | |
1ab52cf9 BS |
64 | #define DW_IC_ENABLE 0x6c |
65 | #define DW_IC_STATUS 0x70 | |
66 | #define DW_IC_TXFLR 0x74 | |
67 | #define DW_IC_RXFLR 0x78 | |
68 | #define DW_IC_COMP_PARAM_1 0xf4 | |
69 | #define DW_IC_TX_ABRT_SOURCE 0x80 | |
70 | ||
71 | #define DW_IC_CON_MASTER 0x1 | |
72 | #define DW_IC_CON_SPEED_STD 0x2 | |
73 | #define DW_IC_CON_SPEED_FAST 0x4 | |
74 | #define DW_IC_CON_10BITADDR_MASTER 0x10 | |
75 | #define DW_IC_CON_RESTART_EN 0x20 | |
76 | #define DW_IC_CON_SLAVE_DISABLE 0x40 | |
77 | ||
e28000a3 SK |
78 | #define DW_IC_INTR_RX_UNDER 0x001 |
79 | #define DW_IC_INTR_RX_OVER 0x002 | |
80 | #define DW_IC_INTR_RX_FULL 0x004 | |
81 | #define DW_IC_INTR_TX_OVER 0x008 | |
82 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
83 | #define DW_IC_INTR_RD_REQ 0x020 | |
84 | #define DW_IC_INTR_TX_ABRT 0x040 | |
85 | #define DW_IC_INTR_RX_DONE 0x080 | |
86 | #define DW_IC_INTR_ACTIVITY 0x100 | |
1ab52cf9 | 87 | #define DW_IC_INTR_STOP_DET 0x200 |
e28000a3 SK |
88 | #define DW_IC_INTR_START_DET 0x400 |
89 | #define DW_IC_INTR_GEN_CALL 0x800 | |
1ab52cf9 BS |
90 | |
91 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
92 | ||
93 | #define DW_IC_ERR_TX_ABRT 0x1 | |
94 | ||
95 | /* | |
96 | * status codes | |
97 | */ | |
98 | #define STATUS_IDLE 0x0 | |
99 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
100 | #define STATUS_READ_IN_PROGRESS 0x2 | |
101 | ||
102 | #define TIMEOUT 20 /* ms */ | |
103 | ||
104 | /* | |
105 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
106 | * | |
107 | * only expected abort codes are listed here | |
108 | * refer to the datasheet for the full list | |
109 | */ | |
110 | #define ABRT_7B_ADDR_NOACK 0 | |
111 | #define ABRT_10ADDR1_NOACK 1 | |
112 | #define ABRT_10ADDR2_NOACK 2 | |
113 | #define ABRT_TXDATA_NOACK 3 | |
114 | #define ABRT_GCALL_NOACK 4 | |
115 | #define ABRT_GCALL_READ 5 | |
116 | #define ABRT_SBYTE_ACKDET 7 | |
117 | #define ABRT_SBYTE_NORSTRT 9 | |
118 | #define ABRT_10B_RD_NORSTRT 10 | |
119 | #define ARB_MASTER_DIS 11 | |
120 | #define ARB_LOST 12 | |
121 | ||
122 | static char *abort_sources[] = { | |
123 | [ABRT_7B_ADDR_NOACK] = | |
124 | "slave address not acknowledged (7bit mode)", | |
125 | [ABRT_10ADDR1_NOACK] = | |
126 | "first address byte not acknowledged (10bit mode)", | |
127 | [ABRT_10ADDR2_NOACK] = | |
128 | "second address byte not acknowledged (10bit mode)", | |
129 | [ABRT_TXDATA_NOACK] = | |
130 | "data not acknowledged", | |
131 | [ABRT_GCALL_NOACK] = | |
132 | "no acknowledgement for a general call", | |
133 | [ABRT_GCALL_READ] = | |
134 | "read after general call", | |
135 | [ABRT_SBYTE_ACKDET] = | |
136 | "start byte acknowledged", | |
137 | [ABRT_SBYTE_NORSTRT] = | |
138 | "trying to send start byte when restart is disabled", | |
139 | [ABRT_10B_RD_NORSTRT] = | |
140 | "trying to read when restart is disabled (10bit mode)", | |
141 | [ARB_MASTER_DIS] = | |
142 | "trying to use disabled adapter", | |
143 | [ARB_LOST] = | |
144 | "lost arbitration", | |
145 | }; | |
146 | ||
147 | /** | |
148 | * struct dw_i2c_dev - private i2c-designware data | |
149 | * @dev: driver model device node | |
150 | * @base: IO registers pointer | |
151 | * @cmd_complete: tx completion indicator | |
152 | * @pump_msg: continue in progress transfers | |
153 | * @lock: protect this struct and IO registers | |
154 | * @clk: input reference clock | |
155 | * @cmd_err: run time hadware error code | |
156 | * @msgs: points to an array of messages currently being transfered | |
157 | * @msgs_num: the number of elements in msgs | |
158 | * @msg_write_idx: the element index of the current tx message in the msgs | |
159 | * array | |
160 | * @tx_buf_len: the length of the current tx buffer | |
161 | * @tx_buf: the current tx buffer | |
162 | * @msg_read_idx: the element index of the current rx message in the msgs | |
163 | * array | |
164 | * @rx_buf_len: the length of the current rx buffer | |
165 | * @rx_buf: the current rx buffer | |
166 | * @msg_err: error status of the current transfer | |
167 | * @status: i2c master status, one of STATUS_* | |
168 | * @abort_source: copy of the TX_ABRT_SOURCE register | |
169 | * @irq: interrupt number for the i2c master | |
170 | * @adapter: i2c subsystem adapter node | |
171 | * @tx_fifo_depth: depth of the hardware tx fifo | |
172 | * @rx_fifo_depth: depth of the hardware rx fifo | |
173 | */ | |
174 | struct dw_i2c_dev { | |
175 | struct device *dev; | |
176 | void __iomem *base; | |
177 | struct completion cmd_complete; | |
178 | struct tasklet_struct pump_msg; | |
179 | struct mutex lock; | |
180 | struct clk *clk; | |
181 | int cmd_err; | |
182 | struct i2c_msg *msgs; | |
183 | int msgs_num; | |
184 | int msg_write_idx; | |
ed5e1dd5 | 185 | u32 tx_buf_len; |
1ab52cf9 BS |
186 | u8 *tx_buf; |
187 | int msg_read_idx; | |
ed5e1dd5 | 188 | u32 rx_buf_len; |
1ab52cf9 BS |
189 | u8 *rx_buf; |
190 | int msg_err; | |
191 | unsigned int status; | |
ed5e1dd5 | 192 | u32 abort_source; |
1ab52cf9 BS |
193 | int irq; |
194 | struct i2c_adapter adapter; | |
195 | unsigned int tx_fifo_depth; | |
196 | unsigned int rx_fifo_depth; | |
197 | }; | |
198 | ||
d60c7e81 SK |
199 | static u32 |
200 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
201 | { | |
202 | /* | |
203 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
204 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
205 | * will result in violation of the tHD;STA spec. | |
206 | */ | |
207 | if (cond) | |
208 | /* | |
209 | * Conditional expression: | |
210 | * | |
211 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
212 | * | |
213 | * This is based on the DW manuals, and represents an ideal | |
214 | * configuration. The resulting I2C bus speed will be | |
215 | * faster than any of the others. | |
216 | * | |
217 | * If your hardware is free from tHD;STA issue, try this one. | |
218 | */ | |
219 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
220 | else | |
221 | /* | |
222 | * Conditional expression: | |
223 | * | |
224 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
225 | * | |
226 | * This is just experimental rule; the tHD;STA period turned | |
227 | * out to be proportinal to (_HCNT + 3). With this setting, | |
228 | * we could meet both tHIGH and tHD;STA timing specs. | |
229 | * | |
230 | * If unsure, you'd better to take this alternative. | |
231 | * | |
232 | * The reason why we need to take into account "tf" here, | |
233 | * is the same as described in i2c_dw_scl_lcnt(). | |
234 | */ | |
235 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
236 | } | |
237 | ||
238 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
239 | { | |
240 | /* | |
241 | * Conditional expression: | |
242 | * | |
243 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
244 | * | |
245 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
246 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
247 | * In order to meet the tLOW timing spec, we need to take into | |
248 | * account the fall time of SCL signal (tf). Default tf value | |
249 | * should be 0.3 us, for safety. | |
250 | */ | |
251 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
252 | } | |
253 | ||
1ab52cf9 BS |
254 | /** |
255 | * i2c_dw_init() - initialize the designware i2c master hardware | |
256 | * @dev: device private data | |
257 | * | |
258 | * This functions configures and enables the I2C master. | |
259 | * This function is called during I2C init function, and in case of timeout at | |
260 | * run time. | |
261 | */ | |
262 | static void i2c_dw_init(struct dw_i2c_dev *dev) | |
263 | { | |
264 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; | |
d60c7e81 | 265 | u32 ic_con, hcnt, lcnt; |
1ab52cf9 BS |
266 | |
267 | /* Disable the adapter */ | |
ed5e1dd5 | 268 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
269 | |
270 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
271 | |
272 | /* Standard-mode */ | |
273 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
274 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
275 | 3, /* tf = 0.3 us */ | |
276 | 0, /* 0: DW default, 1: Ideal */ | |
277 | 0); /* No offset */ | |
278 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
279 | 47, /* tLOW = 4.7 us */ | |
280 | 3, /* tf = 0.3 us */ | |
281 | 0); /* No offset */ | |
282 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); | |
283 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); | |
284 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
285 | ||
286 | /* Fast-mode */ | |
287 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
288 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
289 | 3, /* tf = 0.3 us */ | |
290 | 0, /* 0: DW default, 1: Ideal */ | |
291 | 0); /* No offset */ | |
292 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
293 | 13, /* tLOW = 1.3 us */ | |
294 | 3, /* tf = 0.3 us */ | |
295 | 0); /* No offset */ | |
296 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); | |
297 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); | |
298 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | |
1ab52cf9 BS |
299 | |
300 | /* configure the i2c master */ | |
301 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | | |
302 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; | |
ed5e1dd5 | 303 | writel(ic_con, dev->base + DW_IC_CON); |
1ab52cf9 BS |
304 | } |
305 | ||
306 | /* | |
307 | * Waiting for bus not busy | |
308 | */ | |
309 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
310 | { | |
311 | int timeout = TIMEOUT; | |
312 | ||
ed5e1dd5 | 313 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
314 | if (timeout <= 0) { |
315 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
316 | return -ETIMEDOUT; | |
317 | } | |
318 | timeout--; | |
319 | mdelay(1); | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /* | |
326 | * Initiate low level master read/write transaction. | |
327 | * This function is called from i2c_dw_xfer when starting a transfer. | |
328 | * This function is also called from dw_i2c_pump_msg to continue a transfer | |
329 | * that is longer than the size of the TX FIFO. | |
330 | */ | |
331 | static void | |
e77cf232 | 332 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 333 | { |
1ab52cf9 | 334 | struct i2c_msg *msgs = dev->msgs; |
ed5e1dd5 SK |
335 | u32 ic_con, intr_mask; |
336 | int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); | |
337 | int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); | |
338 | u32 addr = msgs[dev->msg_write_idx].addr; | |
339 | u32 buf_len = dev->tx_buf_len; | |
1ab52cf9 BS |
340 | |
341 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
342 | /* Disable the adapter */ | |
ed5e1dd5 | 343 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
344 | |
345 | /* set the slave (target) address */ | |
ed5e1dd5 | 346 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); |
1ab52cf9 BS |
347 | |
348 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
ed5e1dd5 | 349 | ic_con = readl(dev->base + DW_IC_CON); |
1ab52cf9 BS |
350 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
351 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
352 | else | |
353 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
ed5e1dd5 | 354 | writel(ic_con, dev->base + DW_IC_CON); |
1ab52cf9 BS |
355 | |
356 | /* Enable the adapter */ | |
ed5e1dd5 | 357 | writel(1, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
358 | } |
359 | ||
6d2ea487 | 360 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
1ab52cf9 BS |
361 | /* if target address has changed, we need to |
362 | * reprogram the target address in the i2c | |
363 | * adapter when we are done with this transfer | |
364 | */ | |
365 | if (msgs[dev->msg_write_idx].addr != addr) | |
366 | return; | |
367 | ||
368 | if (msgs[dev->msg_write_idx].len == 0) { | |
369 | dev_err(dev->dev, | |
370 | "%s: invalid message length\n", __func__); | |
371 | dev->msg_err = -EINVAL; | |
372 | return; | |
373 | } | |
374 | ||
375 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
376 | /* new i2c_msg */ | |
377 | dev->tx_buf = msgs[dev->msg_write_idx].buf; | |
378 | buf_len = msgs[dev->msg_write_idx].len; | |
379 | } | |
380 | ||
381 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { | |
382 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | |
ed5e1dd5 | 383 | writel(0x100, dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
384 | rx_limit--; |
385 | } else | |
ed5e1dd5 | 386 | writel(*(dev->tx_buf++), |
1ab52cf9 BS |
387 | dev->base + DW_IC_DATA_CMD); |
388 | tx_limit--; buf_len--; | |
389 | } | |
390 | } | |
391 | ||
392 | intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT; | |
393 | if (buf_len > 0) { /* more bytes to be written */ | |
394 | intr_mask |= DW_IC_INTR_TX_EMPTY; | |
395 | dev->status |= STATUS_WRITE_IN_PROGRESS; | |
396 | } else | |
397 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; | |
ed5e1dd5 | 398 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
1ab52cf9 BS |
399 | |
400 | dev->tx_buf_len = buf_len; | |
401 | } | |
402 | ||
403 | static void | |
78839bd0 | 404 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 405 | { |
1ab52cf9 | 406 | struct i2c_msg *msgs = dev->msgs; |
ed5e1dd5 SK |
407 | u32 addr = msgs[dev->msg_read_idx].addr; |
408 | int rx_valid = readl(dev->base + DW_IC_RXFLR); | |
1ab52cf9 | 409 | |
6d2ea487 | 410 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 411 | u32 len; |
1ab52cf9 BS |
412 | u8 *buf; |
413 | ||
414 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
415 | continue; | |
416 | ||
417 | /* different i2c client, reprogram the i2c adapter */ | |
418 | if (msgs[dev->msg_read_idx].addr != addr) | |
419 | return; | |
420 | ||
421 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { | |
422 | len = msgs[dev->msg_read_idx].len; | |
423 | buf = msgs[dev->msg_read_idx].buf; | |
424 | } else { | |
425 | len = dev->rx_buf_len; | |
426 | buf = dev->rx_buf; | |
427 | } | |
428 | ||
429 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) | |
ed5e1dd5 | 430 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); |
1ab52cf9 BS |
431 | |
432 | if (len > 0) { | |
433 | dev->status |= STATUS_READ_IN_PROGRESS; | |
434 | dev->rx_buf_len = len; | |
435 | dev->rx_buf = buf; | |
436 | return; | |
437 | } else | |
438 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
439 | } | |
440 | } | |
441 | ||
442 | /* | |
443 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
444 | */ | |
445 | static int | |
446 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
447 | { | |
448 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
449 | int ret; | |
450 | ||
451 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
452 | ||
453 | mutex_lock(&dev->lock); | |
454 | ||
455 | INIT_COMPLETION(dev->cmd_complete); | |
456 | dev->msgs = msgs; | |
457 | dev->msgs_num = num; | |
458 | dev->cmd_err = 0; | |
459 | dev->msg_write_idx = 0; | |
460 | dev->msg_read_idx = 0; | |
461 | dev->msg_err = 0; | |
462 | dev->status = STATUS_IDLE; | |
463 | ||
464 | ret = i2c_dw_wait_bus_not_busy(dev); | |
465 | if (ret < 0) | |
466 | goto done; | |
467 | ||
468 | /* start the transfers */ | |
e77cf232 | 469 | i2c_dw_xfer_msg(dev); |
1ab52cf9 BS |
470 | |
471 | /* wait for tx to complete */ | |
472 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
473 | if (ret == 0) { | |
474 | dev_err(dev->dev, "controller timed out\n"); | |
475 | i2c_dw_init(dev); | |
476 | ret = -ETIMEDOUT; | |
477 | goto done; | |
478 | } else if (ret < 0) | |
479 | goto done; | |
480 | ||
481 | if (dev->msg_err) { | |
482 | ret = dev->msg_err; | |
483 | goto done; | |
484 | } | |
485 | ||
486 | /* no error */ | |
487 | if (likely(!dev->cmd_err)) { | |
488 | /* read rx fifo, and disable the adapter */ | |
489 | do { | |
78839bd0 | 490 | i2c_dw_read(dev); |
1ab52cf9 | 491 | } while (dev->status & STATUS_READ_IN_PROGRESS); |
ed5e1dd5 | 492 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
493 | ret = num; |
494 | goto done; | |
495 | } | |
496 | ||
497 | /* We have an error */ | |
498 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
499 | unsigned long abort_source = dev->abort_source; | |
500 | int i; | |
501 | ||
502 | for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) { | |
503 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); | |
504 | } | |
505 | } | |
506 | ret = -EIO; | |
507 | ||
508 | done: | |
509 | mutex_unlock(&dev->lock); | |
510 | ||
511 | return ret; | |
512 | } | |
513 | ||
514 | static u32 i2c_dw_func(struct i2c_adapter *adap) | |
515 | { | |
516 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; | |
517 | } | |
518 | ||
519 | static void dw_i2c_pump_msg(unsigned long data) | |
520 | { | |
521 | struct dw_i2c_dev *dev = (struct dw_i2c_dev *) data; | |
ed5e1dd5 | 522 | u32 intr_mask; |
1ab52cf9 | 523 | |
78839bd0 | 524 | i2c_dw_read(dev); |
e77cf232 | 525 | i2c_dw_xfer_msg(dev); |
1ab52cf9 BS |
526 | |
527 | intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT; | |
528 | if (dev->status & STATUS_WRITE_IN_PROGRESS) | |
529 | intr_mask |= DW_IC_INTR_TX_EMPTY; | |
ed5e1dd5 | 530 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
1ab52cf9 BS |
531 | } |
532 | ||
e28000a3 SK |
533 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
534 | { | |
535 | u32 stat; | |
536 | ||
537 | /* | |
538 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
539 | * Ths unmasked raw version of interrupt status bits are available | |
540 | * in the IC_RAW_INTR_STAT register. | |
541 | * | |
542 | * That is, | |
543 | * stat = readl(IC_INTR_STAT); | |
544 | * equals to, | |
545 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); | |
546 | * | |
547 | * The raw version might be useful for debugging purposes. | |
548 | */ | |
549 | stat = readl(dev->base + DW_IC_INTR_STAT); | |
550 | ||
551 | /* | |
552 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
553 | * you'll miss some interrupts, triggered during the period from | |
554 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). | |
555 | * | |
556 | * Instead, use the separately-prepared IC_CLR_* registers. | |
557 | */ | |
558 | if (stat & DW_IC_INTR_RX_UNDER) | |
559 | readl(dev->base + DW_IC_CLR_RX_UNDER); | |
560 | if (stat & DW_IC_INTR_RX_OVER) | |
561 | readl(dev->base + DW_IC_CLR_RX_OVER); | |
562 | if (stat & DW_IC_INTR_TX_OVER) | |
563 | readl(dev->base + DW_IC_CLR_TX_OVER); | |
564 | if (stat & DW_IC_INTR_RD_REQ) | |
565 | readl(dev->base + DW_IC_CLR_RD_REQ); | |
566 | if (stat & DW_IC_INTR_TX_ABRT) { | |
567 | /* | |
568 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
569 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
570 | */ | |
571 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); | |
572 | readl(dev->base + DW_IC_CLR_TX_ABRT); | |
573 | } | |
574 | if (stat & DW_IC_INTR_RX_DONE) | |
575 | readl(dev->base + DW_IC_CLR_RX_DONE); | |
576 | if (stat & DW_IC_INTR_ACTIVITY) | |
577 | readl(dev->base + DW_IC_CLR_ACTIVITY); | |
578 | if (stat & DW_IC_INTR_STOP_DET) | |
579 | readl(dev->base + DW_IC_CLR_STOP_DET); | |
580 | if (stat & DW_IC_INTR_START_DET) | |
581 | readl(dev->base + DW_IC_CLR_START_DET); | |
582 | if (stat & DW_IC_INTR_GEN_CALL) | |
583 | readl(dev->base + DW_IC_CLR_GEN_CALL); | |
584 | ||
585 | return stat; | |
586 | } | |
587 | ||
1ab52cf9 BS |
588 | /* |
589 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
590 | * occurs. | |
591 | */ | |
592 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |
593 | { | |
594 | struct dw_i2c_dev *dev = dev_id; | |
ed5e1dd5 | 595 | u32 stat; |
1ab52cf9 | 596 | |
e28000a3 | 597 | stat = i2c_dw_read_clear_intrbits(dev); |
1ab52cf9 | 598 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
e28000a3 | 599 | |
1ab52cf9 | 600 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
601 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
602 | dev->status = STATUS_IDLE; | |
603 | } else if (stat & DW_IC_INTR_TX_EMPTY) | |
604 | tasklet_schedule(&dev->pump_msg); | |
605 | ||
ed5e1dd5 | 606 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable interrupts */ |
1ab52cf9 BS |
607 | if (stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) |
608 | complete(&dev->cmd_complete); | |
609 | ||
610 | return IRQ_HANDLED; | |
611 | } | |
612 | ||
613 | static struct i2c_algorithm i2c_dw_algo = { | |
614 | .master_xfer = i2c_dw_xfer, | |
615 | .functionality = i2c_dw_func, | |
616 | }; | |
617 | ||
618 | static int __devinit dw_i2c_probe(struct platform_device *pdev) | |
619 | { | |
620 | struct dw_i2c_dev *dev; | |
621 | struct i2c_adapter *adap; | |
91b52cae SK |
622 | struct resource *mem, *ioarea; |
623 | int irq, r; | |
1ab52cf9 BS |
624 | |
625 | /* NOTE: driver uses the static register mapping */ | |
626 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
627 | if (!mem) { | |
628 | dev_err(&pdev->dev, "no mem resource?\n"); | |
629 | return -EINVAL; | |
630 | } | |
631 | ||
91b52cae SK |
632 | irq = platform_get_irq(pdev, 0); |
633 | if (irq < 0) { | |
1ab52cf9 | 634 | dev_err(&pdev->dev, "no irq resource?\n"); |
91b52cae | 635 | return irq; /* -ENXIO */ |
1ab52cf9 BS |
636 | } |
637 | ||
638 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
639 | pdev->name); | |
640 | if (!ioarea) { | |
641 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
642 | return -EBUSY; | |
643 | } | |
644 | ||
645 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); | |
646 | if (!dev) { | |
647 | r = -ENOMEM; | |
648 | goto err_release_region; | |
649 | } | |
650 | ||
651 | init_completion(&dev->cmd_complete); | |
652 | tasklet_init(&dev->pump_msg, dw_i2c_pump_msg, (unsigned long) dev); | |
653 | mutex_init(&dev->lock); | |
654 | dev->dev = get_device(&pdev->dev); | |
91b52cae | 655 | dev->irq = irq; |
1ab52cf9 BS |
656 | platform_set_drvdata(pdev, dev); |
657 | ||
658 | dev->clk = clk_get(&pdev->dev, NULL); | |
659 | if (IS_ERR(dev->clk)) { | |
660 | r = -ENODEV; | |
661 | goto err_free_mem; | |
662 | } | |
663 | clk_enable(dev->clk); | |
664 | ||
665 | dev->base = ioremap(mem->start, resource_size(mem)); | |
666 | if (dev->base == NULL) { | |
667 | dev_err(&pdev->dev, "failure mapping io resources\n"); | |
668 | r = -EBUSY; | |
669 | goto err_unuse_clocks; | |
670 | } | |
671 | { | |
672 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); | |
673 | ||
674 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; | |
675 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; | |
676 | } | |
677 | i2c_dw_init(dev); | |
678 | ||
ed5e1dd5 | 679 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ |
1ab52cf9 BS |
680 | r = request_irq(dev->irq, i2c_dw_isr, 0, pdev->name, dev); |
681 | if (r) { | |
682 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | |
683 | goto err_iounmap; | |
684 | } | |
685 | ||
686 | adap = &dev->adapter; | |
687 | i2c_set_adapdata(adap, dev); | |
688 | adap->owner = THIS_MODULE; | |
689 | adap->class = I2C_CLASS_HWMON; | |
690 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", | |
691 | sizeof(adap->name)); | |
692 | adap->algo = &i2c_dw_algo; | |
693 | adap->dev.parent = &pdev->dev; | |
694 | ||
695 | adap->nr = pdev->id; | |
696 | r = i2c_add_numbered_adapter(adap); | |
697 | if (r) { | |
698 | dev_err(&pdev->dev, "failure adding adapter\n"); | |
699 | goto err_free_irq; | |
700 | } | |
701 | ||
702 | return 0; | |
703 | ||
704 | err_free_irq: | |
705 | free_irq(dev->irq, dev); | |
706 | err_iounmap: | |
707 | iounmap(dev->base); | |
708 | err_unuse_clocks: | |
709 | clk_disable(dev->clk); | |
710 | clk_put(dev->clk); | |
711 | dev->clk = NULL; | |
712 | err_free_mem: | |
713 | platform_set_drvdata(pdev, NULL); | |
714 | put_device(&pdev->dev); | |
715 | kfree(dev); | |
716 | err_release_region: | |
717 | release_mem_region(mem->start, resource_size(mem)); | |
718 | ||
719 | return r; | |
720 | } | |
721 | ||
722 | static int __devexit dw_i2c_remove(struct platform_device *pdev) | |
723 | { | |
724 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); | |
725 | struct resource *mem; | |
726 | ||
727 | platform_set_drvdata(pdev, NULL); | |
728 | i2c_del_adapter(&dev->adapter); | |
729 | put_device(&pdev->dev); | |
730 | ||
731 | clk_disable(dev->clk); | |
732 | clk_put(dev->clk); | |
733 | dev->clk = NULL; | |
734 | ||
ed5e1dd5 | 735 | writel(0, dev->base + DW_IC_ENABLE); |
1ab52cf9 BS |
736 | free_irq(dev->irq, dev); |
737 | kfree(dev); | |
738 | ||
739 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
740 | release_mem_region(mem->start, resource_size(mem)); | |
741 | return 0; | |
742 | } | |
743 | ||
744 | /* work with hotplug and coldplug */ | |
745 | MODULE_ALIAS("platform:i2c_designware"); | |
746 | ||
747 | static struct platform_driver dw_i2c_driver = { | |
748 | .remove = __devexit_p(dw_i2c_remove), | |
749 | .driver = { | |
750 | .name = "i2c_designware", | |
751 | .owner = THIS_MODULE, | |
752 | }, | |
753 | }; | |
754 | ||
755 | static int __init dw_i2c_init_driver(void) | |
756 | { | |
757 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); | |
758 | } | |
759 | module_init(dw_i2c_init_driver); | |
760 | ||
761 | static void __exit dw_i2c_exit_driver(void) | |
762 | { | |
763 | platform_driver_unregister(&dw_i2c_driver); | |
764 | } | |
765 | module_exit(dw_i2c_exit_driver); | |
766 | ||
767 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
768 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); | |
769 | MODULE_LICENSE("GPL"); |