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8a73cd4c NKC |
1 | /** |
2 | * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | ||
14 | #include <linux/i2c.h> | |
8a73cd4c NKC |
15 | #include <linux/time.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
28 | /* | |
29 | * HSI2C controller from Samsung supports 2 modes of operation | |
30 | * 1. Auto mode: Where in master automatically controls the whole transaction | |
31 | * 2. Manual mode: Software controls the transaction by issuing commands | |
32 | * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. | |
33 | * | |
34 | * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register | |
35 | * | |
36 | * Special bits are available for both modes of operation to set commands | |
37 | * and for checking transfer status | |
38 | */ | |
39 | ||
40 | /* Register Map */ | |
41 | #define HSI2C_CTL 0x00 | |
42 | #define HSI2C_FIFO_CTL 0x04 | |
43 | #define HSI2C_TRAILIG_CTL 0x08 | |
44 | #define HSI2C_CLK_CTL 0x0C | |
45 | #define HSI2C_CLK_SLOT 0x10 | |
46 | #define HSI2C_INT_ENABLE 0x20 | |
47 | #define HSI2C_INT_STATUS 0x24 | |
48 | #define HSI2C_ERR_STATUS 0x2C | |
49 | #define HSI2C_FIFO_STATUS 0x30 | |
50 | #define HSI2C_TX_DATA 0x34 | |
51 | #define HSI2C_RX_DATA 0x38 | |
52 | #define HSI2C_CONF 0x40 | |
53 | #define HSI2C_AUTO_CONF 0x44 | |
54 | #define HSI2C_TIMEOUT 0x48 | |
55 | #define HSI2C_MANUAL_CMD 0x4C | |
56 | #define HSI2C_TRANS_STATUS 0x50 | |
57 | #define HSI2C_TIMING_HS1 0x54 | |
58 | #define HSI2C_TIMING_HS2 0x58 | |
59 | #define HSI2C_TIMING_HS3 0x5C | |
60 | #define HSI2C_TIMING_FS1 0x60 | |
61 | #define HSI2C_TIMING_FS2 0x64 | |
62 | #define HSI2C_TIMING_FS3 0x68 | |
63 | #define HSI2C_TIMING_SLA 0x6C | |
64 | #define HSI2C_ADDR 0x70 | |
65 | ||
66 | /* I2C_CTL Register bits */ | |
67 | #define HSI2C_FUNC_MODE_I2C (1u << 0) | |
68 | #define HSI2C_MASTER (1u << 3) | |
69 | #define HSI2C_RXCHON (1u << 6) | |
70 | #define HSI2C_TXCHON (1u << 7) | |
71 | #define HSI2C_SW_RST (1u << 31) | |
72 | ||
73 | /* I2C_FIFO_CTL Register bits */ | |
74 | #define HSI2C_RXFIFO_EN (1u << 0) | |
75 | #define HSI2C_TXFIFO_EN (1u << 1) | |
76 | #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) | |
77 | #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) | |
78 | ||
79 | /* As per user manual FIFO max depth is 64bytes */ | |
80 | #define HSI2C_FIFO_MAX 0x40 | |
81 | /* default trigger levels for Tx and Rx FIFOs */ | |
82 | #define HSI2C_DEF_TXFIFO_LVL (HSI2C_FIFO_MAX - 0x30) | |
83 | #define HSI2C_DEF_RXFIFO_LVL (HSI2C_FIFO_MAX - 0x10) | |
84 | ||
85 | /* I2C_TRAILING_CTL Register bits */ | |
86 | #define HSI2C_TRAILING_COUNT (0xf) | |
87 | ||
88 | /* I2C_INT_EN Register bits */ | |
89 | #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) | |
90 | #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) | |
91 | #define HSI2C_INT_TRAILING_EN (1u << 6) | |
92 | #define HSI2C_INT_I2C_EN (1u << 9) | |
93 | ||
94 | /* I2C_INT_STAT Register bits */ | |
95 | #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) | |
96 | #define HSI2C_INT_RX_ALMOSTFULL (1u << 1) | |
97 | #define HSI2C_INT_TX_UNDERRUN (1u << 2) | |
98 | #define HSI2C_INT_TX_OVERRUN (1u << 3) | |
99 | #define HSI2C_INT_RX_UNDERRUN (1u << 4) | |
100 | #define HSI2C_INT_RX_OVERRUN (1u << 5) | |
101 | #define HSI2C_INT_TRAILING (1u << 6) | |
102 | #define HSI2C_INT_I2C (1u << 9) | |
103 | ||
104 | /* I2C_FIFO_STAT Register bits */ | |
105 | #define HSI2C_RX_FIFO_EMPTY (1u << 24) | |
106 | #define HSI2C_RX_FIFO_FULL (1u << 23) | |
107 | #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) | |
108 | #define HSI2C_TX_FIFO_EMPTY (1u << 8) | |
109 | #define HSI2C_TX_FIFO_FULL (1u << 7) | |
110 | #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) | |
111 | ||
112 | /* I2C_CONF Register bits */ | |
113 | #define HSI2C_AUTO_MODE (1u << 31) | |
114 | #define HSI2C_10BIT_ADDR_MODE (1u << 30) | |
115 | #define HSI2C_HS_MODE (1u << 29) | |
116 | ||
117 | /* I2C_AUTO_CONF Register bits */ | |
118 | #define HSI2C_READ_WRITE (1u << 16) | |
119 | #define HSI2C_STOP_AFTER_TRANS (1u << 17) | |
120 | #define HSI2C_MASTER_RUN (1u << 31) | |
121 | ||
122 | /* I2C_TIMEOUT Register bits */ | |
123 | #define HSI2C_TIMEOUT_EN (1u << 31) | |
124 | #define HSI2C_TIMEOUT_MASK 0xff | |
125 | ||
126 | /* I2C_TRANS_STATUS register bits */ | |
127 | #define HSI2C_MASTER_BUSY (1u << 17) | |
128 | #define HSI2C_SLAVE_BUSY (1u << 16) | |
129 | #define HSI2C_TIMEOUT_AUTO (1u << 4) | |
130 | #define HSI2C_NO_DEV (1u << 3) | |
131 | #define HSI2C_NO_DEV_ACK (1u << 2) | |
132 | #define HSI2C_TRANS_ABORT (1u << 1) | |
133 | #define HSI2C_TRANS_DONE (1u << 0) | |
134 | ||
135 | /* I2C_ADDR register bits */ | |
136 | #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) | |
137 | #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) | |
138 | #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) | |
139 | #define MASTER_ID(x) ((x & 0x7) + 0x08) | |
140 | ||
141 | /* | |
142 | * Controller operating frequency, timing values for operation | |
143 | * are calculated against this frequency | |
144 | */ | |
145 | #define HSI2C_HS_TX_CLOCK 1000000 | |
146 | #define HSI2C_FS_TX_CLOCK 100000 | |
147 | #define HSI2C_HIGH_SPD 1 | |
148 | #define HSI2C_FAST_SPD 0 | |
149 | ||
150 | #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
151 | ||
152 | struct exynos5_i2c { | |
153 | struct i2c_adapter adap; | |
154 | unsigned int suspended:1; | |
155 | ||
156 | struct i2c_msg *msg; | |
157 | struct completion msg_complete; | |
158 | unsigned int msg_ptr; | |
159 | ||
160 | unsigned int irq; | |
161 | ||
162 | void __iomem *regs; | |
163 | struct clk *clk; | |
164 | struct device *dev; | |
165 | int state; | |
166 | ||
167 | spinlock_t lock; /* IRQ synchronization */ | |
168 | ||
169 | /* | |
170 | * Since the TRANS_DONE bit is cleared on read, and we may read it | |
171 | * either during an IRQ or after a transaction, keep track of its | |
172 | * state here. | |
173 | */ | |
174 | int trans_done; | |
175 | ||
176 | /* Controller operating frequency */ | |
177 | unsigned int fs_clock; | |
178 | unsigned int hs_clock; | |
179 | ||
180 | /* | |
181 | * HSI2C Controller can operate in | |
182 | * 1. High speed upto 3.4Mbps | |
183 | * 2. Fast speed upto 1Mbps | |
184 | */ | |
185 | int speed_mode; | |
186 | }; | |
187 | ||
188 | static const struct of_device_id exynos5_i2c_match[] = { | |
189 | { .compatible = "samsung,exynos5-hsi2c" }, | |
190 | {}, | |
191 | }; | |
192 | MODULE_DEVICE_TABLE(of, exynos5_i2c_match); | |
193 | ||
194 | static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) | |
195 | { | |
196 | writel(readl(i2c->regs + HSI2C_INT_STATUS), | |
197 | i2c->regs + HSI2C_INT_STATUS); | |
198 | } | |
199 | ||
200 | /* | |
201 | * exynos5_i2c_set_timing: updates the registers with appropriate | |
202 | * timing values calculated | |
203 | * | |
204 | * Returns 0 on success, -EINVAL if the cycle length cannot | |
205 | * be calculated. | |
206 | */ | |
207 | static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) | |
208 | { | |
209 | u32 i2c_timing_s1; | |
210 | u32 i2c_timing_s2; | |
211 | u32 i2c_timing_s3; | |
212 | u32 i2c_timing_sla; | |
213 | unsigned int t_start_su, t_start_hd; | |
214 | unsigned int t_stop_su; | |
215 | unsigned int t_data_su, t_data_hd; | |
216 | unsigned int t_scl_l, t_scl_h; | |
217 | unsigned int t_sr_release; | |
218 | unsigned int t_ftl_cycle; | |
219 | unsigned int clkin = clk_get_rate(i2c->clk); | |
220 | unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle; | |
221 | unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ? | |
222 | i2c->hs_clock : i2c->fs_clock; | |
223 | ||
224 | /* | |
225 | * FPCLK / FI2C = | |
226 | * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE | |
227 | * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) | |
228 | * utemp1 = (TSCLK_L + TSCLK_H + 2) | |
229 | */ | |
230 | t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; | |
231 | utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; | |
232 | ||
233 | /* CLK_DIV max is 256 */ | |
234 | for (div = 0; div < 256; div++) { | |
235 | utemp1 = utemp0 / (div + 1); | |
236 | ||
237 | /* | |
238 | * SCL_L and SCL_H each has max value of 255 | |
239 | * Hence, For the clk_cycle to the have right value | |
240 | * utemp1 has to be less then 512 and more than 4. | |
241 | */ | |
242 | if ((utemp1 < 512) && (utemp1 > 4)) { | |
243 | clk_cycle = utemp1 - 2; | |
244 | break; | |
245 | } else if (div == 255) { | |
246 | dev_warn(i2c->dev, "Failed to calculate divisor"); | |
247 | return -EINVAL; | |
248 | } | |
249 | } | |
250 | ||
251 | t_scl_l = clk_cycle / 2; | |
252 | t_scl_h = clk_cycle / 2; | |
253 | t_start_su = t_scl_l; | |
254 | t_start_hd = t_scl_l; | |
255 | t_stop_su = t_scl_l; | |
256 | t_data_su = t_scl_l / 2; | |
257 | t_data_hd = t_scl_l / 2; | |
258 | t_sr_release = clk_cycle; | |
259 | ||
260 | i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; | |
261 | i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; | |
262 | i2c_timing_s3 = div << 16 | t_sr_release << 0; | |
263 | i2c_timing_sla = t_data_hd << 0; | |
264 | ||
265 | dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", | |
266 | t_start_su, t_start_hd, t_stop_su); | |
267 | dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", | |
268 | t_data_su, t_scl_l, t_scl_h); | |
269 | dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", | |
270 | div, t_sr_release); | |
271 | dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); | |
272 | ||
273 | if (mode == HSI2C_HIGH_SPD) { | |
274 | writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); | |
275 | writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); | |
276 | writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); | |
277 | } else { | |
278 | writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); | |
279 | writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); | |
280 | writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); | |
281 | } | |
282 | writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) | |
288 | { | |
289 | /* | |
290 | * Configure the Fast speed timing values | |
291 | * Even the High Speed mode initially starts with Fast mode | |
292 | */ | |
293 | if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) { | |
294 | dev_err(i2c->dev, "HSI2C FS Clock set up failed\n"); | |
295 | return -EINVAL; | |
296 | } | |
297 | ||
298 | /* configure the High speed timing values */ | |
299 | if (i2c->speed_mode == HSI2C_HIGH_SPD) { | |
300 | if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) { | |
301 | dev_err(i2c->dev, "HSI2C HS Clock set up failed\n"); | |
302 | return -EINVAL; | |
303 | } | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | /* | |
310 | * exynos5_i2c_init: configures the controller for I2C functionality | |
311 | * Programs I2C controller for Master mode operation | |
312 | */ | |
313 | static void exynos5_i2c_init(struct exynos5_i2c *i2c) | |
314 | { | |
315 | u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); | |
316 | u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); | |
317 | ||
318 | /* Clear to disable Timeout */ | |
319 | i2c_timeout &= ~HSI2C_TIMEOUT_EN; | |
320 | writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); | |
321 | ||
322 | writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), | |
323 | i2c->regs + HSI2C_CTL); | |
324 | writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); | |
325 | ||
326 | if (i2c->speed_mode == HSI2C_HIGH_SPD) { | |
327 | writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), | |
328 | i2c->regs + HSI2C_ADDR); | |
329 | i2c_conf |= HSI2C_HS_MODE; | |
330 | } | |
331 | ||
332 | writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); | |
333 | } | |
334 | ||
335 | static void exynos5_i2c_reset(struct exynos5_i2c *i2c) | |
336 | { | |
337 | u32 i2c_ctl; | |
338 | ||
339 | /* Set and clear the bit for reset */ | |
340 | i2c_ctl = readl(i2c->regs + HSI2C_CTL); | |
341 | i2c_ctl |= HSI2C_SW_RST; | |
342 | writel(i2c_ctl, i2c->regs + HSI2C_CTL); | |
343 | ||
344 | i2c_ctl = readl(i2c->regs + HSI2C_CTL); | |
345 | i2c_ctl &= ~HSI2C_SW_RST; | |
346 | writel(i2c_ctl, i2c->regs + HSI2C_CTL); | |
347 | ||
348 | /* We don't expect calculations to fail during the run */ | |
349 | exynos5_hsi2c_clock_setup(i2c); | |
350 | /* Initialize the configure registers */ | |
351 | exynos5_i2c_init(i2c); | |
352 | } | |
353 | ||
354 | /* | |
355 | * exynos5_i2c_irq: top level IRQ servicing routine | |
356 | * | |
357 | * INT_STATUS registers gives the interrupt details. Further, | |
358 | * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed | |
359 | * state of the bus. | |
360 | */ | |
361 | static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) | |
362 | { | |
363 | struct exynos5_i2c *i2c = dev_id; | |
364 | u32 fifo_level, int_status, fifo_status, trans_status; | |
365 | unsigned char byte; | |
366 | int len = 0; | |
367 | ||
368 | i2c->state = -EINVAL; | |
369 | ||
370 | spin_lock(&i2c->lock); | |
371 | ||
372 | int_status = readl(i2c->regs + HSI2C_INT_STATUS); | |
373 | writel(int_status, i2c->regs + HSI2C_INT_STATUS); | |
374 | fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); | |
375 | ||
376 | /* handle interrupt related to the transfer status */ | |
377 | if (int_status & HSI2C_INT_I2C) { | |
378 | trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); | |
379 | if (trans_status & HSI2C_NO_DEV_ACK) { | |
380 | dev_dbg(i2c->dev, "No ACK from device\n"); | |
381 | i2c->state = -ENXIO; | |
382 | goto stop; | |
383 | } else if (trans_status & HSI2C_NO_DEV) { | |
384 | dev_dbg(i2c->dev, "No device\n"); | |
385 | i2c->state = -ENXIO; | |
386 | goto stop; | |
387 | } else if (trans_status & HSI2C_TRANS_ABORT) { | |
388 | dev_dbg(i2c->dev, "Deal with arbitration lose\n"); | |
389 | i2c->state = -EAGAIN; | |
390 | goto stop; | |
391 | } else if (trans_status & HSI2C_TIMEOUT_AUTO) { | |
392 | dev_dbg(i2c->dev, "Accessing device timed out\n"); | |
393 | i2c->state = -EAGAIN; | |
394 | goto stop; | |
395 | } else if (trans_status & HSI2C_TRANS_DONE) { | |
396 | i2c->trans_done = 1; | |
397 | i2c->state = 0; | |
398 | } | |
399 | } | |
400 | ||
401 | if ((i2c->msg->flags & I2C_M_RD) && (int_status & | |
402 | (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { | |
403 | fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); | |
404 | fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); | |
405 | len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); | |
406 | ||
407 | while (len > 0) { | |
408 | byte = (unsigned char) | |
409 | readl(i2c->regs + HSI2C_RX_DATA); | |
410 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
411 | len--; | |
412 | } | |
413 | i2c->state = 0; | |
414 | } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { | |
415 | fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); | |
416 | fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); | |
417 | ||
418 | len = HSI2C_FIFO_MAX - fifo_level; | |
419 | if (len > (i2c->msg->len - i2c->msg_ptr)) | |
420 | len = i2c->msg->len - i2c->msg_ptr; | |
421 | ||
422 | while (len > 0) { | |
423 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
424 | writel(byte, i2c->regs + HSI2C_TX_DATA); | |
425 | len--; | |
426 | } | |
427 | i2c->state = 0; | |
428 | } | |
429 | ||
430 | stop: | |
431 | if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || | |
432 | (i2c->state < 0)) { | |
433 | writel(0, i2c->regs + HSI2C_INT_ENABLE); | |
434 | exynos5_i2c_clr_pend_irq(i2c); | |
435 | complete(&i2c->msg_complete); | |
436 | } | |
437 | ||
438 | spin_unlock(&i2c->lock); | |
439 | ||
440 | return IRQ_HANDLED; | |
441 | } | |
442 | ||
443 | /* | |
444 | * exynos5_i2c_wait_bus_idle | |
445 | * | |
446 | * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being | |
447 | * cleared. | |
448 | * | |
449 | * Returns -EBUSY if the bus cannot be bought to idle | |
450 | */ | |
451 | static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) | |
452 | { | |
453 | unsigned long stop_time; | |
454 | u32 trans_status; | |
455 | ||
456 | /* wait for 100 milli seconds for the bus to be idle */ | |
457 | stop_time = jiffies + msecs_to_jiffies(100) + 1; | |
458 | do { | |
459 | trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); | |
460 | if (!(trans_status & HSI2C_MASTER_BUSY)) | |
461 | return 0; | |
462 | ||
463 | usleep_range(50, 200); | |
464 | } while (time_before(jiffies, stop_time)); | |
465 | ||
466 | return -EBUSY; | |
467 | } | |
468 | ||
469 | /* | |
470 | * exynos5_i2c_message_start: Configures the bus and starts the xfer | |
471 | * i2c: struct exynos5_i2c pointer for the current bus | |
472 | * stop: Enables stop after transfer if set. Set for last transfer of | |
473 | * in the list of messages. | |
474 | * | |
475 | * Configures the bus for read/write function | |
476 | * Sets chip address to talk to, message length to be sent. | |
477 | * Enables appropriate interrupts and sends start xfer command. | |
478 | */ | |
479 | static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) | |
480 | { | |
481 | u32 i2c_ctl; | |
482 | u32 int_en = HSI2C_INT_I2C_EN; | |
483 | u32 i2c_auto_conf = 0; | |
484 | u32 fifo_ctl; | |
485 | unsigned long flags; | |
486 | ||
487 | i2c_ctl = readl(i2c->regs + HSI2C_CTL); | |
488 | i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); | |
489 | fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; | |
490 | ||
491 | if (i2c->msg->flags & I2C_M_RD) { | |
492 | i2c_ctl |= HSI2C_RXCHON; | |
493 | ||
494 | i2c_auto_conf = HSI2C_READ_WRITE; | |
495 | ||
496 | fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(HSI2C_DEF_TXFIFO_LVL); | |
497 | int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | | |
498 | HSI2C_INT_TRAILING_EN); | |
499 | } else { | |
500 | i2c_ctl |= HSI2C_TXCHON; | |
501 | ||
502 | fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(HSI2C_DEF_RXFIFO_LVL); | |
503 | int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; | |
504 | } | |
505 | ||
506 | writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); | |
507 | ||
508 | writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); | |
509 | writel(i2c_ctl, i2c->regs + HSI2C_CTL); | |
510 | ||
511 | ||
512 | /* | |
513 | * Enable interrupts before starting the transfer so that we don't | |
514 | * miss any INT_I2C interrupts. | |
515 | */ | |
516 | spin_lock_irqsave(&i2c->lock, flags); | |
517 | writel(int_en, i2c->regs + HSI2C_INT_ENABLE); | |
518 | ||
519 | if (stop == 1) | |
520 | i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; | |
521 | i2c_auto_conf |= i2c->msg->len; | |
522 | i2c_auto_conf |= HSI2C_MASTER_RUN; | |
523 | writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); | |
524 | spin_unlock_irqrestore(&i2c->lock, flags); | |
525 | } | |
526 | ||
527 | static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, | |
528 | struct i2c_msg *msgs, int stop) | |
529 | { | |
530 | unsigned long timeout; | |
531 | int ret; | |
532 | ||
533 | i2c->msg = msgs; | |
534 | i2c->msg_ptr = 0; | |
535 | i2c->trans_done = 0; | |
536 | ||
13509c3a | 537 | reinit_completion(&i2c->msg_complete); |
8a73cd4c NKC |
538 | |
539 | exynos5_i2c_message_start(i2c, stop); | |
540 | ||
541 | timeout = wait_for_completion_timeout(&i2c->msg_complete, | |
542 | EXYNOS5_I2C_TIMEOUT); | |
543 | if (timeout == 0) | |
544 | ret = -ETIMEDOUT; | |
545 | else | |
546 | ret = i2c->state; | |
547 | ||
548 | /* | |
549 | * If this is the last message to be transfered (stop == 1) | |
550 | * Then check if the bus can be brought back to idle. | |
551 | */ | |
552 | if (ret == 0 && stop) | |
553 | ret = exynos5_i2c_wait_bus_idle(i2c); | |
554 | ||
555 | if (ret < 0) { | |
556 | exynos5_i2c_reset(i2c); | |
557 | if (ret == -ETIMEDOUT) | |
558 | dev_warn(i2c->dev, "%s timeout\n", | |
559 | (msgs->flags & I2C_M_RD) ? "rx" : "tx"); | |
560 | } | |
561 | ||
562 | /* Return the state as in interrupt routine */ | |
563 | return ret; | |
564 | } | |
565 | ||
566 | static int exynos5_i2c_xfer(struct i2c_adapter *adap, | |
567 | struct i2c_msg *msgs, int num) | |
568 | { | |
569 | struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data; | |
570 | int i = 0, ret = 0, stop = 0; | |
571 | ||
572 | if (i2c->suspended) { | |
77d84ff8 | 573 | dev_err(i2c->dev, "HS-I2C is not initialized.\n"); |
8a73cd4c NKC |
574 | return -EIO; |
575 | } | |
576 | ||
577 | clk_prepare_enable(i2c->clk); | |
578 | ||
579 | for (i = 0; i < num; i++, msgs++) { | |
580 | stop = (i == num - 1); | |
581 | ||
582 | ret = exynos5_i2c_xfer_msg(i2c, msgs, stop); | |
583 | ||
584 | if (ret < 0) | |
585 | goto out; | |
586 | } | |
587 | ||
588 | if (i == num) { | |
589 | ret = num; | |
590 | } else { | |
591 | /* Only one message, cannot access the device */ | |
592 | if (i == 1) | |
593 | ret = -EREMOTEIO; | |
594 | else | |
595 | ret = i; | |
596 | ||
597 | dev_warn(i2c->dev, "xfer message failed\n"); | |
598 | } | |
599 | ||
600 | out: | |
601 | clk_disable_unprepare(i2c->clk); | |
602 | return ret; | |
603 | } | |
604 | ||
605 | static u32 exynos5_i2c_func(struct i2c_adapter *adap) | |
606 | { | |
607 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
608 | } | |
609 | ||
610 | static const struct i2c_algorithm exynos5_i2c_algorithm = { | |
611 | .master_xfer = exynos5_i2c_xfer, | |
612 | .functionality = exynos5_i2c_func, | |
613 | }; | |
614 | ||
615 | static int exynos5_i2c_probe(struct platform_device *pdev) | |
616 | { | |
617 | struct device_node *np = pdev->dev.of_node; | |
618 | struct exynos5_i2c *i2c; | |
619 | struct resource *mem; | |
620 | unsigned int op_clock; | |
621 | int ret; | |
622 | ||
623 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); | |
624 | if (!i2c) { | |
625 | dev_err(&pdev->dev, "no memory for state\n"); | |
626 | return -ENOMEM; | |
627 | } | |
628 | ||
629 | if (of_property_read_u32(np, "clock-frequency", &op_clock)) { | |
630 | i2c->speed_mode = HSI2C_FAST_SPD; | |
631 | i2c->fs_clock = HSI2C_FS_TX_CLOCK; | |
632 | } else { | |
633 | if (op_clock >= HSI2C_HS_TX_CLOCK) { | |
634 | i2c->speed_mode = HSI2C_HIGH_SPD; | |
635 | i2c->fs_clock = HSI2C_FS_TX_CLOCK; | |
636 | i2c->hs_clock = op_clock; | |
637 | } else { | |
638 | i2c->speed_mode = HSI2C_FAST_SPD; | |
639 | i2c->fs_clock = op_clock; | |
640 | } | |
641 | } | |
642 | ||
643 | strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); | |
644 | i2c->adap.owner = THIS_MODULE; | |
645 | i2c->adap.algo = &exynos5_i2c_algorithm; | |
646 | i2c->adap.retries = 3; | |
647 | ||
648 | i2c->dev = &pdev->dev; | |
649 | i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); | |
650 | if (IS_ERR(i2c->clk)) { | |
651 | dev_err(&pdev->dev, "cannot get clock\n"); | |
652 | return -ENOENT; | |
653 | } | |
654 | ||
655 | clk_prepare_enable(i2c->clk); | |
656 | ||
657 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
658 | i2c->regs = devm_ioremap_resource(&pdev->dev, mem); | |
659 | if (IS_ERR(i2c->regs)) { | |
660 | ret = PTR_ERR(i2c->regs); | |
661 | goto err_clk; | |
662 | } | |
663 | ||
664 | i2c->adap.dev.of_node = np; | |
665 | i2c->adap.algo_data = i2c; | |
666 | i2c->adap.dev.parent = &pdev->dev; | |
667 | ||
668 | /* Clear pending interrupts from u-boot or misc causes */ | |
669 | exynos5_i2c_clr_pend_irq(i2c); | |
670 | ||
671 | spin_lock_init(&i2c->lock); | |
672 | init_completion(&i2c->msg_complete); | |
673 | ||
674 | i2c->irq = ret = platform_get_irq(pdev, 0); | |
675 | if (ret <= 0) { | |
676 | dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); | |
677 | ret = -EINVAL; | |
678 | goto err_clk; | |
679 | } | |
680 | ||
681 | ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, | |
682 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
683 | dev_name(&pdev->dev), i2c); | |
684 | ||
685 | if (ret != 0) { | |
686 | dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); | |
687 | goto err_clk; | |
688 | } | |
689 | ||
690 | ret = exynos5_hsi2c_clock_setup(i2c); | |
691 | if (ret) | |
692 | goto err_clk; | |
693 | ||
694 | exynos5_i2c_init(i2c); | |
695 | ||
696 | ret = i2c_add_adapter(&i2c->adap); | |
697 | if (ret < 0) { | |
698 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); | |
699 | goto err_clk; | |
700 | } | |
701 | ||
702 | platform_set_drvdata(pdev, i2c); | |
703 | ||
8a73cd4c NKC |
704 | err_clk: |
705 | clk_disable_unprepare(i2c->clk); | |
706 | return ret; | |
707 | } | |
708 | ||
709 | static int exynos5_i2c_remove(struct platform_device *pdev) | |
710 | { | |
711 | struct exynos5_i2c *i2c = platform_get_drvdata(pdev); | |
712 | ||
713 | i2c_del_adapter(&i2c->adap); | |
8a73cd4c NKC |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
3917b84d | 718 | #ifdef CONFIG_PM_SLEEP |
8a73cd4c NKC |
719 | static int exynos5_i2c_suspend_noirq(struct device *dev) |
720 | { | |
721 | struct platform_device *pdev = to_platform_device(dev); | |
722 | struct exynos5_i2c *i2c = platform_get_drvdata(pdev); | |
723 | ||
724 | i2c->suspended = 1; | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | static int exynos5_i2c_resume_noirq(struct device *dev) | |
730 | { | |
731 | struct platform_device *pdev = to_platform_device(dev); | |
732 | struct exynos5_i2c *i2c = platform_get_drvdata(pdev); | |
733 | int ret = 0; | |
734 | ||
735 | clk_prepare_enable(i2c->clk); | |
736 | ||
737 | ret = exynos5_hsi2c_clock_setup(i2c); | |
738 | if (ret) { | |
739 | clk_disable_unprepare(i2c->clk); | |
740 | return ret; | |
741 | } | |
742 | ||
743 | exynos5_i2c_init(i2c); | |
744 | clk_disable_unprepare(i2c->clk); | |
745 | i2c->suspended = 0; | |
746 | ||
747 | return 0; | |
748 | } | |
3917b84d | 749 | #endif |
8a73cd4c NKC |
750 | |
751 | static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_suspend_noirq, | |
752 | exynos5_i2c_resume_noirq); | |
753 | ||
754 | static struct platform_driver exynos5_i2c_driver = { | |
755 | .probe = exynos5_i2c_probe, | |
756 | .remove = exynos5_i2c_remove, | |
757 | .driver = { | |
758 | .owner = THIS_MODULE, | |
759 | .name = "exynos5-hsi2c", | |
760 | .pm = &exynos5_i2c_dev_pm_ops, | |
761 | .of_match_table = exynos5_i2c_match, | |
762 | }, | |
763 | }; | |
764 | ||
765 | module_platform_driver(exynos5_i2c_driver); | |
766 | ||
767 | MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); | |
768 | MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>"); | |
769 | MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>"); | |
770 | MODULE_LICENSE("GPL v2"); |