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[mirror_ubuntu-focal-kernel.git] / drivers / i2c / busses / i2c-exynos5.c
CommitLineData
8a73cd4c
NKC		 1/**
2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include <linux/i2c.h>
8a73cd4c
NKC		 15#include <linux/time.h>
16#include <linux/interrupt.h>
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/slab.h>
23#include <linux/io.h>
24#include <linux/of_address.h>
b371f866 25#include <linux/of_device.h>
8a73cd4c
NKC		 26#include <linux/of_irq.h>
27#include <linux/spinlock.h>
28
29/*
30 * HSI2C controller from Samsung supports 2 modes of operation
31 * 1. Auto mode: Where in master automatically controls the whole transaction
32 * 2. Manual mode: Software controls the transaction by issuing commands
33 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
34 *
35 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
36 *
37 * Special bits are available for both modes of operation to set commands
38 * and for checking transfer status
39 */
40
41/* Register Map */
42#define HSI2C_CTL 0x00
43#define HSI2C_FIFO_CTL 0x04
44#define HSI2C_TRAILIG_CTL 0x08
45#define HSI2C_CLK_CTL 0x0C
46#define HSI2C_CLK_SLOT 0x10
47#define HSI2C_INT_ENABLE 0x20
48#define HSI2C_INT_STATUS 0x24
49#define HSI2C_ERR_STATUS 0x2C
50#define HSI2C_FIFO_STATUS 0x30
51#define HSI2C_TX_DATA 0x34
52#define HSI2C_RX_DATA 0x38
53#define HSI2C_CONF 0x40
54#define HSI2C_AUTO_CONF 0x44
55#define HSI2C_TIMEOUT 0x48
56#define HSI2C_MANUAL_CMD 0x4C
57#define HSI2C_TRANS_STATUS 0x50
58#define HSI2C_TIMING_HS1 0x54
59#define HSI2C_TIMING_HS2 0x58
60#define HSI2C_TIMING_HS3 0x5C
61#define HSI2C_TIMING_FS1 0x60
62#define HSI2C_TIMING_FS2 0x64
63#define HSI2C_TIMING_FS3 0x68
64#define HSI2C_TIMING_SLA 0x6C
65#define HSI2C_ADDR 0x70
66
67/* I2C_CTL Register bits */
68#define HSI2C_FUNC_MODE_I2C (1u << 0)
69#define HSI2C_MASTER (1u << 3)
70#define HSI2C_RXCHON (1u << 6)
71#define HSI2C_TXCHON (1u << 7)
72#define HSI2C_SW_RST (1u << 31)
73
74/* I2C_FIFO_CTL Register bits */
75#define HSI2C_RXFIFO_EN (1u << 0)
76#define HSI2C_TXFIFO_EN (1u << 1)
77#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
78#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
79
8a73cd4c
NKC		 80/* I2C_TRAILING_CTL Register bits */
81#define HSI2C_TRAILING_COUNT (0xf)
82
83/* I2C_INT_EN Register bits */
84#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
85#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
86#define HSI2C_INT_TRAILING_EN (1u << 6)
8a73cd4c
NKC		 87
88/* I2C_INT_STAT Register bits */
89#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
90#define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
91#define HSI2C_INT_TX_UNDERRUN (1u << 2)
92#define HSI2C_INT_TX_OVERRUN (1u << 3)
93#define HSI2C_INT_RX_UNDERRUN (1u << 4)
94#define HSI2C_INT_RX_OVERRUN (1u << 5)
95#define HSI2C_INT_TRAILING (1u << 6)
96#define HSI2C_INT_I2C (1u << 9)
97
2374a539
NKC		 98#define HSI2C_INT_TRANS_DONE (1u << 7)
99#define HSI2C_INT_TRANS_ABORT (1u << 8)
100#define HSI2C_INT_NO_DEV_ACK (1u << 9)
101#define HSI2C_INT_NO_DEV (1u << 10)
102#define HSI2C_INT_TIMEOUT (1u << 11)
103#define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
104 HSI2C_INT_TRANS_ABORT | \
105 HSI2C_INT_NO_DEV_ACK | \
106 HSI2C_INT_NO_DEV | \
107 HSI2C_INT_TIMEOUT)
108
8a73cd4c
NKC		 109/* I2C_FIFO_STAT Register bits */
110#define HSI2C_RX_FIFO_EMPTY (1u << 24)
111#define HSI2C_RX_FIFO_FULL (1u << 23)
112#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
113#define HSI2C_TX_FIFO_EMPTY (1u << 8)
114#define HSI2C_TX_FIFO_FULL (1u << 7)
115#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
116
117/* I2C_CONF Register bits */
118#define HSI2C_AUTO_MODE (1u << 31)
119#define HSI2C_10BIT_ADDR_MODE (1u << 30)
120#define HSI2C_HS_MODE (1u << 29)
121
122/* I2C_AUTO_CONF Register bits */
123#define HSI2C_READ_WRITE (1u << 16)
124#define HSI2C_STOP_AFTER_TRANS (1u << 17)
125#define HSI2C_MASTER_RUN (1u << 31)
126
127/* I2C_TIMEOUT Register bits */
128#define HSI2C_TIMEOUT_EN (1u << 31)
129#define HSI2C_TIMEOUT_MASK 0xff
130
131/* I2C_TRANS_STATUS register bits */
132#define HSI2C_MASTER_BUSY (1u << 17)
133#define HSI2C_SLAVE_BUSY (1u << 16)
7999eecb
AH		 134
135/* I2C_TRANS_STATUS register bits for Exynos5 variant */
8a73cd4c
NKC		 136#define HSI2C_TIMEOUT_AUTO (1u << 4)
137#define HSI2C_NO_DEV (1u << 3)
138#define HSI2C_NO_DEV_ACK (1u << 2)
139#define HSI2C_TRANS_ABORT (1u << 1)
140#define HSI2C_TRANS_DONE (1u << 0)
141
7999eecb
AH		 142/* I2C_TRANS_STATUS register bits for Exynos7 variant */
143#define HSI2C_MASTER_ST_MASK 0xf
144#define HSI2C_MASTER_ST_IDLE 0x0
145#define HSI2C_MASTER_ST_START 0x1
146#define HSI2C_MASTER_ST_RESTART 0x2
147#define HSI2C_MASTER_ST_STOP 0x3
148#define HSI2C_MASTER_ST_MASTER_ID 0x4
149#define HSI2C_MASTER_ST_ADDR0 0x5
150#define HSI2C_MASTER_ST_ADDR1 0x6
151#define HSI2C_MASTER_ST_ADDR2 0x7
152#define HSI2C_MASTER_ST_ADDR_SR 0x8
153#define HSI2C_MASTER_ST_READ 0x9
154#define HSI2C_MASTER_ST_WRITE 0xa
155#define HSI2C_MASTER_ST_NO_ACK 0xb
156#define HSI2C_MASTER_ST_LOSE 0xc
157#define HSI2C_MASTER_ST_WAIT 0xd
158#define HSI2C_MASTER_ST_WAIT_CMD 0xe
159
8a73cd4c
NKC		 160/* I2C_ADDR register bits */
161#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
162#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
163#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
164#define MASTER_ID(x) ((x & 0x7) + 0x08)
165
166/*
167 * Controller operating frequency, timing values for operation
168 * are calculated against this frequency
169 */
170#define HSI2C_HS_TX_CLOCK 1000000
171#define HSI2C_FS_TX_CLOCK 100000
8a73cd4c
NKC		 172
173#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
174
2374a539
NKC		 175#define HSI2C_EXYNOS7 BIT(0)
176
8a73cd4c
NKC		 177struct exynos5_i2c {
178 struct i2c_adapter adap;
179 unsigned int suspended:1;
180
181 struct i2c_msg *msg;
182 struct completion msg_complete;
183 unsigned int msg_ptr;
184
185 unsigned int irq;
186
187 void __iomem *regs;
188 struct clk *clk;
189 struct device *dev;
190 int state;
191
192 spinlock_t lock; /* IRQ synchronization */
193
194 /*
195 * Since the TRANS_DONE bit is cleared on read, and we may read it
196 * either during an IRQ or after a transaction, keep track of its
197 * state here.
198 */
199 int trans_done;
200
201 /* Controller operating frequency */
b9d5b31a 202 unsigned int op_clock;
218e1496
NKC		 203
204 /* Version of HS-I2C Hardware */
b371f866 205 const struct exynos_hsi2c_variant *variant;
218e1496
NKC		 206};
207
208/**
209 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
210 * @fifo_depth: the fifo depth supported by the HSI2C module
211 *
212 * Specifies platform specific configuration of HSI2C module.
213 * Note: A structure for driver specific platform data is used for future
214 * expansion of its usage.
215 */
216struct exynos_hsi2c_variant {
217 unsigned int fifo_depth;
2374a539 218 unsigned int hw;
218e1496
NKC		 219};
220
221static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
222 .fifo_depth = 64,
223};
224
225static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
226 .fifo_depth = 16,
8a73cd4c
NKC		 227};
228
2374a539
NKC		 229static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
230 .fifo_depth = 16,
231 .hw = HSI2C_EXYNOS7,
232};
233
8a73cd4c 234static const struct of_device_id exynos5_i2c_match[] = {
218e1496
NKC		 235 {
236 .compatible = "samsung,exynos5-hsi2c",
237 .data = &exynos5250_hsi2c_data
238 }, {
239 .compatible = "samsung,exynos5250-hsi2c",
240 .data = &exynos5250_hsi2c_data
241 }, {
242 .compatible = "samsung,exynos5260-hsi2c",
243 .data = &exynos5260_hsi2c_data
2374a539
NKC		 244 }, {
245 .compatible = "samsung,exynos7-hsi2c",
246 .data = &exynos7_hsi2c_data
218e1496 247 }, {},
8a73cd4c
NKC		 248};
249MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
250
251static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
252{
253 writel(readl(i2c->regs + HSI2C_INT_STATUS),
254 i2c->regs + HSI2C_INT_STATUS);
255}
256
257/*
258 * exynos5_i2c_set_timing: updates the registers with appropriate
259 * timing values calculated
260 *
261 * Returns 0 on success, -EINVAL if the cycle length cannot
262 * be calculated.
263 */
b9d5b31a 264static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
8a73cd4c
NKC		 265{
266 u32 i2c_timing_s1;
267 u32 i2c_timing_s2;
268 u32 i2c_timing_s3;
269 u32 i2c_timing_sla;
270 unsigned int t_start_su, t_start_hd;
271 unsigned int t_stop_su;
272 unsigned int t_data_su, t_data_hd;
273 unsigned int t_scl_l, t_scl_h;
274 unsigned int t_sr_release;
275 unsigned int t_ftl_cycle;
276 unsigned int clkin = clk_get_rate(i2c->clk);
b9d5b31a
AH		 277 unsigned int op_clk = hs_timings ? i2c->op_clock :
278 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
279 i2c->op_clock;
b917d4fd 280 int div, clk_cycle, temp;
8a73cd4c
NKC		 281
282 /*
2374a539 283 * In case of HSI2C controller in Exynos5 series
8a73cd4c
NKC		 284 * FPCLK / FI2C =
285 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
2374a539
NKC		 286 *
287 * In case of HSI2C controllers in Exynos7 series
288 * FPCLK / FI2C =
289 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
290 *
b917d4fd
AH		 291 * clk_cycle := TSCLK_L + TSCLK_H
292 * temp := (CLK_DIV + 1) * (clk_cycle + 2)
293 *
294 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
295 *
8a73cd4c
NKC		 296 */
297 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
b917d4fd
AH		 298 temp = clkin / op_clk - 8 - t_ftl_cycle;
299 if (i2c->variant->hw != HSI2C_EXYNOS7)
300 temp -= t_ftl_cycle;
301 div = temp / 512;
302 clk_cycle = temp / (div + 1) - 2;
303 if (temp < 4 || div >= 256 || clk_cycle < 2) {
70c8c4e9
AH		 304 dev_err(i2c->dev, "%s clock set-up failed\n",
305 hs_timings ? "HS" : "FS");
b917d4fd 306 return -EINVAL;
8a73cd4c
NKC		 307 }
308
309 t_scl_l = clk_cycle / 2;
310 t_scl_h = clk_cycle / 2;
311 t_start_su = t_scl_l;
312 t_start_hd = t_scl_l;
313 t_stop_su = t_scl_l;
314 t_data_su = t_scl_l / 2;
315 t_data_hd = t_scl_l / 2;
316 t_sr_release = clk_cycle;
317
318 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
319 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
320 i2c_timing_s3 = div << 16 | t_sr_release << 0;
321 i2c_timing_sla = t_data_hd << 0;
322
323 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
324 t_start_su, t_start_hd, t_stop_su);
325 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
326 t_data_su, t_scl_l, t_scl_h);
327 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
328 div, t_sr_release);
329 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
330
b9d5b31a 331 if (hs_timings) {
8a73cd4c
NKC		 332 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
333 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
334 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
335 } else {
336 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
337 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
338 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
339 }
340 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
341
342 return 0;
343}
344
345static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
346{
70c8c4e9
AH		 347 /* always set Fast Speed timings */
348 int ret = exynos5_i2c_set_timing(i2c, false);
8a73cd4c 349
70c8c4e9
AH		 350 if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK)
351 return ret;
8a73cd4c 352
70c8c4e9 353 return exynos5_i2c_set_timing(i2c, true);
8a73cd4c
NKC		 354}
355
356/*
357 * exynos5_i2c_init: configures the controller for I2C functionality
358 * Programs I2C controller for Master mode operation
359 */
360static void exynos5_i2c_init(struct exynos5_i2c *i2c)
361{
362 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
363 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
364
365 /* Clear to disable Timeout */
366 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
367 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
368
369 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
370 i2c->regs + HSI2C_CTL);
371 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
372
b9d5b31a 373 if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
8a73cd4c
NKC		 374 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
375 i2c->regs + HSI2C_ADDR);
376 i2c_conf |= HSI2C_HS_MODE;
377 }
378
379 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
380}
381
382static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
383{
384 u32 i2c_ctl;
385
386 /* Set and clear the bit for reset */
387 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
388 i2c_ctl |= HSI2C_SW_RST;
389 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
390
391 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
392 i2c_ctl &= ~HSI2C_SW_RST;
393 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
394
395 /* We don't expect calculations to fail during the run */
396 exynos5_hsi2c_clock_setup(i2c);
397 /* Initialize the configure registers */
398 exynos5_i2c_init(i2c);
399}
400
401/*
402 * exynos5_i2c_irq: top level IRQ servicing routine
403 *
404 * INT_STATUS registers gives the interrupt details. Further,
405 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
406 * state of the bus.
407 */
408static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
409{
410 struct exynos5_i2c *i2c = dev_id;
411 u32 fifo_level, int_status, fifo_status, trans_status;
412 unsigned char byte;
413 int len = 0;
414
415 i2c->state = -EINVAL;
416
417 spin_lock(&i2c->lock);
418
419 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
420 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
8a73cd4c
NKC		 421
422 /* handle interrupt related to the transfer status */
2374a539
NKC		 423 if (i2c->variant->hw == HSI2C_EXYNOS7) {
424 if (int_status & HSI2C_INT_TRANS_DONE) {
425 i2c->trans_done = 1;
426 i2c->state = 0;
427 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
428 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
429 i2c->state = -EAGAIN;
430 goto stop;
431 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
432 dev_dbg(i2c->dev, "No ACK from device\n");
433 i2c->state = -ENXIO;
434 goto stop;
435 } else if (int_status & HSI2C_INT_NO_DEV) {
436 dev_dbg(i2c->dev, "No device\n");
437 i2c->state = -ENXIO;
438 goto stop;
439 } else if (int_status & HSI2C_INT_TIMEOUT) {
440 dev_dbg(i2c->dev, "Accessing device timed out\n");
194fa7ff 441 i2c->state = -ETIMEDOUT;
2374a539
NKC		 442 goto stop;
443 }
7999eecb 444
9ad22474 445 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
7999eecb
AH		 446 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) {
447 i2c->state = -EAGAIN;
448 goto stop;
449 }
2374a539 450 } else if (int_status & HSI2C_INT_I2C) {
9ad22474 451 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
8a73cd4c
NKC		 452 if (trans_status & HSI2C_NO_DEV_ACK) {
453 dev_dbg(i2c->dev, "No ACK from device\n");
454 i2c->state = -ENXIO;
455 goto stop;
456 } else if (trans_status & HSI2C_NO_DEV) {
457 dev_dbg(i2c->dev, "No device\n");
458 i2c->state = -ENXIO;
459 goto stop;
460 } else if (trans_status & HSI2C_TRANS_ABORT) {
461 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
462 i2c->state = -EAGAIN;
463 goto stop;
464 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
465 dev_dbg(i2c->dev, "Accessing device timed out\n");
194fa7ff 466 i2c->state = -ETIMEDOUT;
8a73cd4c
NKC		 467 goto stop;
468 } else if (trans_status & HSI2C_TRANS_DONE) {
469 i2c->trans_done = 1;
470 i2c->state = 0;
471 }
472 }
473
474 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
475 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
476 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
477 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
478 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
479
480 while (len > 0) {
481 byte = (unsigned char)
482 readl(i2c->regs + HSI2C_RX_DATA);
483 i2c->msg->buf[i2c->msg_ptr++] = byte;
484 len--;
485 }
486 i2c->state = 0;
487 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
488 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
489 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
490
218e1496 491 len = i2c->variant->fifo_depth - fifo_level;
fd1c9c85
AH		 492 if (len > (i2c->msg->len - i2c->msg_ptr)) {
493 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
494
495 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
496 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
8a73cd4c 497 len = i2c->msg->len - i2c->msg_ptr;
fd1c9c85 498 }
8a73cd4c
NKC		 499
500 while (len > 0) {
501 byte = i2c->msg->buf[i2c->msg_ptr++];
502 writel(byte, i2c->regs + HSI2C_TX_DATA);
503 len--;
504 }
505 i2c->state = 0;
506 }
507
508 stop:
509 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
510 (i2c->state < 0)) {
511 writel(0, i2c->regs + HSI2C_INT_ENABLE);
512 exynos5_i2c_clr_pend_irq(i2c);
513 complete(&i2c->msg_complete);
514 }
515
516 spin_unlock(&i2c->lock);
517
518 return IRQ_HANDLED;
519}
520
521/*
522 * exynos5_i2c_wait_bus_idle
523 *
524 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
525 * cleared.
526 *
527 * Returns -EBUSY if the bus cannot be bought to idle
528 */
529static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
530{
531 unsigned long stop_time;
532 u32 trans_status;
533
534 /* wait for 100 milli seconds for the bus to be idle */
535 stop_time = jiffies + msecs_to_jiffies(100) + 1;
536 do {
537 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
538 if (!(trans_status & HSI2C_MASTER_BUSY))
539 return 0;
540
541 usleep_range(50, 200);
542 } while (time_before(jiffies, stop_time));
543
544 return -EBUSY;
545}
546
547/*
548 * exynos5_i2c_message_start: Configures the bus and starts the xfer
549 * i2c: struct exynos5_i2c pointer for the current bus
550 * stop: Enables stop after transfer if set. Set for last transfer of
551 * in the list of messages.
552 *
553 * Configures the bus for read/write function
554 * Sets chip address to talk to, message length to be sent.
555 * Enables appropriate interrupts and sends start xfer command.
556 */
557static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
558{
559 u32 i2c_ctl;
2374a539 560 u32 int_en = 0;
8a73cd4c
NKC		 561 u32 i2c_auto_conf = 0;
562 u32 fifo_ctl;
563 unsigned long flags;
218e1496 564 unsigned short trig_lvl;
8a73cd4c 565
2374a539
NKC		 566 if (i2c->variant->hw == HSI2C_EXYNOS7)
567 int_en |= HSI2C_INT_I2C_TRANS;
568 else
569 int_en |= HSI2C_INT_I2C;
570
8a73cd4c
NKC		 571 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
572 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
573 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
574
575 if (i2c->msg->flags & I2C_M_RD) {
576 i2c_ctl |= HSI2C_RXCHON;
577
290025d9 578 i2c_auto_conf |= HSI2C_READ_WRITE;
8a73cd4c 579
218e1496
NKC		 580 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
581 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
582 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
583
8a73cd4c
NKC		 584 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
585 HSI2C_INT_TRAILING_EN);
586 } else {
587 i2c_ctl |= HSI2C_TXCHON;
588
218e1496
NKC		 589 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
590 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
591 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
592
8a73cd4c
NKC		 593 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
594 }
595
596 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
597
598 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
599 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
600
8a73cd4c
NKC		 601 /*
602 * Enable interrupts before starting the transfer so that we don't
603 * miss any INT_I2C interrupts.
604 */
605 spin_lock_irqsave(&i2c->lock, flags);
606 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
607
608 if (stop == 1)
609 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
610 i2c_auto_conf |= i2c->msg->len;
611 i2c_auto_conf |= HSI2C_MASTER_RUN;
612 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
613 spin_unlock_irqrestore(&i2c->lock, flags);
614}
615
616static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
617 struct i2c_msg *msgs, int stop)
618{
619 unsigned long timeout;
620 int ret;
621
622 i2c->msg = msgs;
623 i2c->msg_ptr = 0;
624 i2c->trans_done = 0;
625
13509c3a 626 reinit_completion(&i2c->msg_complete);
8a73cd4c
NKC		 627
628 exynos5_i2c_message_start(i2c, stop);
629
630 timeout = wait_for_completion_timeout(&i2c->msg_complete,
631 EXYNOS5_I2C_TIMEOUT);
632 if (timeout == 0)
633 ret = -ETIMEDOUT;
634 else
635 ret = i2c->state;
636
637 /*
638 * If this is the last message to be transfered (stop == 1)
639 * Then check if the bus can be brought back to idle.
640 */
641 if (ret == 0 && stop)
642 ret = exynos5_i2c_wait_bus_idle(i2c);
643
644 if (ret < 0) {
645 exynos5_i2c_reset(i2c);
646 if (ret == -ETIMEDOUT)
647 dev_warn(i2c->dev, "%s timeout\n",
648 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
649 }
650
651 /* Return the state as in interrupt routine */
652 return ret;
653}
654
655static int exynos5_i2c_xfer(struct i2c_adapter *adap,
656 struct i2c_msg *msgs, int num)
657{
0ff83d2c 658 struct exynos5_i2c *i2c = adap->algo_data;
8a73cd4c
NKC		 659 int i = 0, ret = 0, stop = 0;
660
661 if (i2c->suspended) {
77d84ff8 662 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
8a73cd4c
NKC		 663 return -EIO;
664 }
665
10ff4c52
JMC		 666 ret = clk_enable(i2c->clk);
667 if (ret)
668 return ret;
8a73cd4c
NKC		 669
670 for (i = 0; i < num; i++, msgs++) {
671 stop = (i == num - 1);
672
673 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
674
675 if (ret < 0)
676 goto out;
677 }
678
679 if (i == num) {
680 ret = num;
681 } else {
682 /* Only one message, cannot access the device */
683 if (i == 1)
684 ret = -EREMOTEIO;
685 else
686 ret = i;
687
688 dev_warn(i2c->dev, "xfer message failed\n");
689 }
690
691 out:
10ff4c52 692 clk_disable(i2c->clk);
8a73cd4c
NKC		 693 return ret;
694}
695
696static u32 exynos5_i2c_func(struct i2c_adapter *adap)
697{
698 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
699}
700
701static const struct i2c_algorithm exynos5_i2c_algorithm = {
702 .master_xfer = exynos5_i2c_xfer,
703 .functionality = exynos5_i2c_func,
704};
705
706static int exynos5_i2c_probe(struct platform_device *pdev)
707{
708 struct device_node *np = pdev->dev.of_node;
709 struct exynos5_i2c *i2c;
710 struct resource *mem;
8a73cd4c
NKC		 711 int ret;
712
713 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
46797a2a 714 if (!i2c)
8a73cd4c 715 return -ENOMEM;
8a73cd4c 716
b9d5b31a
AH		 717 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
718 i2c->op_clock = HSI2C_FS_TX_CLOCK;
8a73cd4c
NKC		 719
720 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
721 i2c->adap.owner = THIS_MODULE;
722 i2c->adap.algo = &exynos5_i2c_algorithm;
723 i2c->adap.retries = 3;
724
725 i2c->dev = &pdev->dev;
726 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
727 if (IS_ERR(i2c->clk)) {
728 dev_err(&pdev->dev, "cannot get clock\n");
729 return -ENOENT;
730 }
731
10ff4c52
JMC		 732 ret = clk_prepare_enable(i2c->clk);
733 if (ret)
734 return ret;
8a73cd4c
NKC		 735
736 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
737 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
738 if (IS_ERR(i2c->regs)) {
739 ret = PTR_ERR(i2c->regs);
740 goto err_clk;
741 }
742
743 i2c->adap.dev.of_node = np;
744 i2c->adap.algo_data = i2c;
745 i2c->adap.dev.parent = &pdev->dev;
746
747 /* Clear pending interrupts from u-boot or misc causes */
748 exynos5_i2c_clr_pend_irq(i2c);
749
750 spin_lock_init(&i2c->lock);
751 init_completion(&i2c->msg_complete);
752
753 i2c->irq = ret = platform_get_irq(pdev, 0);
754 if (ret <= 0) {
755 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
756 ret = -EINVAL;
757 goto err_clk;
758 }
759
760 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
761 IRQF_NO_SUSPEND | IRQF_ONESHOT,
762 dev_name(&pdev->dev), i2c);
763
764 if (ret != 0) {
765 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
766 goto err_clk;
767 }
768
b371f866 769 i2c->variant = of_device_get_match_data(&pdev->dev);
2374a539 770
8a73cd4c
NKC		 771 ret = exynos5_hsi2c_clock_setup(i2c);
772 if (ret)
773 goto err_clk;
774
218e1496 775 exynos5_i2c_reset(i2c);
8a73cd4c
NKC		 776
777 ret = i2c_add_adapter(&i2c->adap);
ea734404 778 if (ret < 0)
8a73cd4c 779 goto err_clk;
8a73cd4c
NKC		 780
781 platform_set_drvdata(pdev, i2c);
782
10ff4c52
JMC		 783 clk_disable(i2c->clk);
784
785 return 0;
786
8a73cd4c
NKC		 787 err_clk:
788 clk_disable_unprepare(i2c->clk);
789 return ret;
790}
791
792static int exynos5_i2c_remove(struct platform_device *pdev)
793{
794 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
795
796 i2c_del_adapter(&i2c->adap);
8a73cd4c 797
10ff4c52
JMC		 798 clk_unprepare(i2c->clk);
799
8a73cd4c
NKC		 800 return 0;
801}
802
3917b84d 803#ifdef CONFIG_PM_SLEEP
8a73cd4c
NKC		 804static int exynos5_i2c_suspend_noirq(struct device *dev)
805{
9242e72a 806 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
8a73cd4c
NKC		 807
808 i2c->suspended = 1;
809
10ff4c52
JMC		 810 clk_unprepare(i2c->clk);
811
8a73cd4c
NKC		 812 return 0;
813}
814
815static int exynos5_i2c_resume_noirq(struct device *dev)
816{
9242e72a 817 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
8a73cd4c
NKC		 818 int ret = 0;
819
10ff4c52
JMC		 820 ret = clk_prepare_enable(i2c->clk);
821 if (ret)
822 return ret;
8a73cd4c
NKC		 823
824 ret = exynos5_hsi2c_clock_setup(i2c);
825 if (ret) {
826 clk_disable_unprepare(i2c->clk);
827 return ret;
828 }
829
830 exynos5_i2c_init(i2c);
10ff4c52 831 clk_disable(i2c->clk);
8a73cd4c
NKC		 832 i2c->suspended = 0;
833
834 return 0;
835}
3917b84d 836#endif
8a73cd4c 837
57186fe3 838static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
d4644bec
AL		 839 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
840 exynos5_i2c_resume_noirq)
57186fe3 841};
8a73cd4c
NKC		 842
843static struct platform_driver exynos5_i2c_driver = {
844 .probe = exynos5_i2c_probe,
845 .remove = exynos5_i2c_remove,
846 .driver = {
8a73cd4c
NKC		 847 .name = "exynos5-hsi2c",
848 .pm = &exynos5_i2c_dev_pm_ops,
849 .of_match_table = exynos5_i2c_match,
850 },
851};
852
853module_platform_driver(exynos5_i2c_driver);
854
855MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
856MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
857MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
858MODULE_LICENSE("GPL v2");
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