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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
b3b8df97 | 5 | Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
1da177e4 LT |
18 | */ |
19 | ||
20 | /* | |
ce316110 JD |
21 | * Supports the following Intel I/O Controller Hubs (ICH): |
22 | * | |
23 | * I/O Block I2C | |
24 | * region SMBus Block proc. block | |
25 | * Chip name PCI ID size PEC buffer call read | |
26 | * --------------------------------------------------------------------------- | |
27 | * 82801AA (ICH) 0x2413 16 no no no no | |
28 | * 82801AB (ICH0) 0x2423 16 no no no no | |
29 | * 82801BA (ICH2) 0x2443 16 no no no no | |
30 | * 82801CA (ICH3) 0x2483 32 soft no no no | |
31 | * 82801DB (ICH4) 0x24c3 32 hard yes no no | |
32 | * 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
33 | * 6300ESB 0x25a4 32 hard yes yes yes | |
34 | * 82801F (ICH6) 0x266a 32 hard yes yes yes | |
35 | * 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
36 | * 82801G (ICH7) 0x27da 32 hard yes yes yes | |
37 | * 82801H (ICH8) 0x283e 32 hard yes yes yes | |
38 | * 82801I (ICH9) 0x2930 32 hard yes yes yes | |
39 | * EP80579 (Tolapai) 0x5032 32 hard yes yes yes | |
40 | * ICH10 0x3a30 32 hard yes yes yes | |
41 | * ICH10 0x3a60 32 hard yes yes yes | |
42 | * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes | |
43 | * 6 Series (PCH) 0x1c22 32 hard yes yes yes | |
44 | * Patsburg (PCH) 0x1d22 32 hard yes yes yes | |
45 | * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes | |
46 | * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
47 | * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
48 | * DH89xxCC (PCH) 0x2330 32 hard yes yes yes | |
49 | * Panther Point (PCH) 0x1e22 32 hard yes yes yes | |
50 | * Lynx Point (PCH) 0x8c22 32 hard yes yes yes | |
51 | * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes | |
52 | * Avoton (SOC) 0x1f3c 32 hard yes yes yes | |
53 | * Wellsburg (PCH) 0x8d22 32 hard yes yes yes | |
54 | * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes | |
55 | * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes | |
56 | * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes | |
57 | * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes | |
b299de83 | 58 | * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes |
ce316110 JD |
59 | * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes |
60 | * BayTrail (SOC) 0x0f12 32 hard yes yes yes | |
3e27a844 | 61 | * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes |
3eee1799 | 62 | * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes |
84d7f2eb | 63 | * DNV (SOC) 0x19df 32 hard yes yes yes |
dd77f423 | 64 | * Broxton (SOC) 0x5ad4 32 hard yes yes yes |
cdc5a311 AY |
65 | * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes |
66 | * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes | |
ce316110 JD |
67 | * |
68 | * Features supported by this driver: | |
69 | * Software PEC no | |
70 | * Hardware PEC yes | |
71 | * Block buffer yes | |
72 | * Block process call transaction no | |
73 | * I2C block read transaction yes (doesn't use the block buffer) | |
74 | * Slave mode no | |
75 | * Interrupt processing yes | |
76 | * | |
77 | * See the file Documentation/i2c/busses/i2c-i801 for details. | |
78 | */ | |
1da177e4 | 79 | |
636752bc | 80 | #include <linux/interrupt.h> |
1da177e4 LT |
81 | #include <linux/module.h> |
82 | #include <linux/pci.h> | |
83 | #include <linux/kernel.h> | |
84 | #include <linux/stddef.h> | |
85 | #include <linux/delay.h> | |
1da177e4 LT |
86 | #include <linux/ioport.h> |
87 | #include <linux/init.h> | |
88 | #include <linux/i2c.h> | |
54fb4a05 | 89 | #include <linux/acpi.h> |
1561bfe5 | 90 | #include <linux/io.h> |
fa5bfab7 | 91 | #include <linux/dmi.h> |
665a96b7 | 92 | #include <linux/slab.h> |
636752bc | 93 | #include <linux/wait.h> |
3ad7ea18 | 94 | #include <linux/err.h> |
94246930 MW |
95 | #include <linux/platform_device.h> |
96 | #include <linux/platform_data/itco_wdt.h> | |
3ad7ea18 | 97 | |
79e3e5b8 JD |
98 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
99 | defined CONFIG_DMI | |
3ad7ea18 JD |
100 | #include <linux/gpio.h> |
101 | #include <linux/i2c-mux-gpio.h> | |
3ad7ea18 | 102 | #endif |
1da177e4 | 103 | |
1da177e4 | 104 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
105 | #define SMBHSTSTS(p) (0 + (p)->smba) |
106 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
107 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
108 | #define SMBHSTADD(p) (4 + (p)->smba) | |
109 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
110 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
111 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
112 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
113 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
114 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
115 | |
116 | /* PCI Address Constants */ | |
6dcc19df | 117 | #define SMBBAR 4 |
aeb8a3d1 | 118 | #define SMBPCICTL 0x004 |
636752bc | 119 | #define SMBPCISTS 0x006 |
1da177e4 | 120 | #define SMBHSTCFG 0x040 |
94246930 MW |
121 | #define TCOBASE 0x050 |
122 | #define TCOCTL 0x054 | |
123 | ||
124 | #define ACPIBASE 0x040 | |
125 | #define ACPIBASE_SMI_OFF 0x030 | |
126 | #define ACPICTRL 0x044 | |
127 | #define ACPICTRL_EN 0x080 | |
128 | ||
129 | #define SBREG_BAR 0x10 | |
130 | #define SBREG_SMBCTRL 0xc6000c | |
1da177e4 | 131 | |
636752bc DK |
132 | /* Host status bits for SMBPCISTS */ |
133 | #define SMBPCISTS_INTS 0x08 | |
134 | ||
aeb8a3d1 JD |
135 | /* Control bits for SMBPCICTL */ |
136 | #define SMBPCICTL_INTDIS 0x0400 | |
137 | ||
1da177e4 LT |
138 | /* Host configuration bits for SMBHSTCFG */ |
139 | #define SMBHSTCFG_HST_EN 1 | |
140 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
141 | #define SMBHSTCFG_I2C_EN 4 | |
142 | ||
94246930 MW |
143 | /* TCO configuration bits for TCOCTL */ |
144 | #define TCOCTL_EN 0x0100 | |
145 | ||
25985edc | 146 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
147 | #define SMBAUXCTL_CRC 1 |
148 | #define SMBAUXCTL_E32B 2 | |
149 | ||
1da177e4 | 150 | /* Other settings */ |
84c1af4c | 151 | #define MAX_RETRIES 400 |
1da177e4 LT |
152 | |
153 | /* I801 command constants */ | |
154 | #define I801_QUICK 0x00 | |
155 | #define I801_BYTE 0x04 | |
156 | #define I801_BYTE_DATA 0x08 | |
157 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 158 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 159 | #define I801_BLOCK_DATA 0x14 |
6342064c | 160 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
161 | |
162 | /* I801 Host Control register bits */ | |
163 | #define SMBHSTCNT_INTREN 0x01 | |
164 | #define SMBHSTCNT_KILL 0x02 | |
165 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
166 | #define SMBHSTCNT_START 0x40 | |
167 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 168 | |
ca8b9e32 OR |
169 | /* I801 Hosts Status register bits */ |
170 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
171 | #define SMBHSTSTS_INUSE_STS 0x40 | |
172 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
173 | #define SMBHSTSTS_FAILED 0x10 | |
174 | #define SMBHSTSTS_BUS_ERR 0x08 | |
175 | #define SMBHSTSTS_DEV_ERR 0x04 | |
176 | #define SMBHSTSTS_INTR 0x02 | |
177 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 178 | |
70a1cc19 DK |
179 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
180 | SMBHSTSTS_DEV_ERR) | |
181 | ||
182 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
183 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 184 | |
a6e5e2be | 185 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
ce316110 | 186 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 |
34b57f40 | 187 | #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df |
ce316110 JD |
188 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 |
189 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 | 190 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
ce316110 JD |
191 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 |
192 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
193 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
194 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 | |
195 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c | |
34b57f40 | 196 | #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 |
ce316110 JD |
197 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
198 | #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 | |
199 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
34b57f40 | 200 | #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 |
ce316110 | 201 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
b299de83 | 202 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 |
ce316110 JD |
203 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 |
204 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d | |
205 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e | |
206 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f | |
207 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 | |
afc65924 | 208 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 |
3eee1799 | 209 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 |
34b57f40 | 210 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 |
cdc5a311 AY |
211 | #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 |
212 | #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 | |
55fee8d7 | 213 | |
3ad7ea18 JD |
214 | struct i801_mux_config { |
215 | char *gpio_chip; | |
216 | unsigned values[3]; | |
217 | int n_values; | |
218 | unsigned classes[3]; | |
219 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
220 | int n_gpios; | |
221 | }; | |
222 | ||
0cd96eb0 DW |
223 | struct i801_priv { |
224 | struct i2c_adapter adapter; | |
225 | unsigned long smba; | |
226 | unsigned char original_hstcfg; | |
227 | struct pci_dev *pci_dev; | |
228 | unsigned int features; | |
636752bc DK |
229 | |
230 | /* isr processing */ | |
231 | wait_queue_head_t waitq; | |
232 | u8 status; | |
d3ff6ce4 DK |
233 | |
234 | /* Command state used by isr for byte-by-byte block transactions */ | |
235 | u8 cmd; | |
236 | bool is_read; | |
237 | int count; | |
238 | int len; | |
239 | u8 *data; | |
3ad7ea18 | 240 | |
79e3e5b8 JD |
241 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
242 | defined CONFIG_DMI | |
3ad7ea18 | 243 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
244 | struct platform_device *mux_pdev; |
245 | #endif | |
94246930 | 246 | struct platform_device *tco_pdev; |
0cd96eb0 DW |
247 | }; |
248 | ||
369f6f4a JD |
249 | #define FEATURE_SMBUS_PEC (1 << 0) |
250 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
251 | #define FEATURE_BLOCK_PROC (1 << 2) | |
252 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 253 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
254 | /* Not really a feature, but it's convenient to handle it as such */ |
255 | #define FEATURE_IDF (1 << 15) | |
94246930 | 256 | #define FEATURE_TCO (1 << 16) |
1da177e4 | 257 | |
adff687d JD |
258 | static const char *i801_feature_names[] = { |
259 | "SMBus PEC", | |
260 | "Block buffer", | |
261 | "Block process call", | |
262 | "I2C block read", | |
636752bc | 263 | "Interrupt", |
adff687d JD |
264 | }; |
265 | ||
266 | static unsigned int disable_features; | |
267 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
53229345 JD |
268 | MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" |
269 | "\t\t 0x01 disable SMBus PEC\n" | |
270 | "\t\t 0x02 disable the block buffer\n" | |
271 | "\t\t 0x08 disable the I2C block read functionality\n" | |
272 | "\t\t 0x10 don't use interrupts "); | |
adff687d | 273 | |
cf898dc5 JD |
274 | /* Make sure the SMBus host is ready to start transmitting. |
275 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 276 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 277 | { |
2b73809d | 278 | int status; |
1da177e4 | 279 | |
0cd96eb0 | 280 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 281 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 282 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
283 | return -EBUSY; |
284 | } | |
285 | ||
286 | status &= STATUS_FLAGS; | |
287 | if (status) { | |
0cd96eb0 | 288 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 289 | status); |
0cd96eb0 DW |
290 | outb_p(status, SMBHSTSTS(priv)); |
291 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 292 | if (status) { |
0cd96eb0 | 293 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
294 | "Failed clearing status flags (%02x)\n", |
295 | status); | |
97140342 | 296 | return -EBUSY; |
1da177e4 LT |
297 | } |
298 | } | |
299 | ||
cf898dc5 JD |
300 | return 0; |
301 | } | |
1da177e4 | 302 | |
6cad93c4 JD |
303 | /* |
304 | * Convert the status register to an error code, and clear it. | |
305 | * Note that status only contains the bits we want to clear, not the | |
306 | * actual register value. | |
307 | */ | |
308 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
309 | { |
310 | int result = 0; | |
1da177e4 | 311 | |
636752bc DK |
312 | /* |
313 | * If the SMBus is still busy, we give up | |
314 | * Note: This timeout condition only happens when using polling | |
315 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
316 | * DEV_ERR. | |
317 | */ | |
6cad93c4 | 318 | if (unlikely(status < 0)) { |
0cd96eb0 | 319 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 320 | /* try to stop the current command */ |
0cd96eb0 DW |
321 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
322 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
323 | SMBHSTCNT(priv)); | |
84c1af4c | 324 | usleep_range(1000, 2000); |
0cd96eb0 DW |
325 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
326 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
327 | |
328 | /* Check if it worked */ | |
0cd96eb0 | 329 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
330 | if ((status & SMBHSTSTS_HOST_BUSY) || |
331 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 332 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 333 | "Failed terminating the transaction\n"); |
0cd96eb0 | 334 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 335 | return -ETIMEDOUT; |
1da177e4 LT |
336 | } |
337 | ||
2b73809d | 338 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 339 | result = -EIO; |
0cd96eb0 | 340 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
341 | } |
342 | if (status & SMBHSTSTS_DEV_ERR) { | |
343 | result = -ENXIO; | |
0cd96eb0 | 344 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 345 | } |
2b73809d | 346 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 347 | result = -EAGAIN; |
0cd96eb0 | 348 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
349 | } |
350 | ||
6cad93c4 JD |
351 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
352 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 353 | |
1da177e4 LT |
354 | return result; |
355 | } | |
356 | ||
6cad93c4 JD |
357 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
358 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 359 | { |
cf898dc5 | 360 | int timeout = 0; |
6cad93c4 | 361 | int status; |
cf898dc5 JD |
362 | |
363 | /* We will always wait for a fraction of a second! */ | |
364 | do { | |
84c1af4c | 365 | usleep_range(250, 500); |
0cd96eb0 | 366 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
367 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
368 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
369 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 370 | |
6cad93c4 JD |
371 | if (timeout > MAX_RETRIES) { |
372 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
373 | return -ETIMEDOUT; | |
374 | } | |
375 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
376 | } |
377 | ||
6cad93c4 JD |
378 | /* Wait for either BYTE_DONE or an error flag being set */ |
379 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
380 | { |
381 | int timeout = 0; | |
2b73809d | 382 | int status; |
ca8b9e32 | 383 | |
6cad93c4 | 384 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 385 | do { |
84c1af4c | 386 | usleep_range(250, 500); |
0cd96eb0 | 387 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
388 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
389 | (timeout++ < MAX_RETRIES)); | |
390 | ||
391 | if (timeout > MAX_RETRIES) { | |
392 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
393 | return -ETIMEDOUT; | |
394 | } | |
395 | return status & STATUS_ERROR_FLAGS; | |
396 | } | |
397 | ||
398 | static int i801_transaction(struct i801_priv *priv, int xact) | |
399 | { | |
400 | int status; | |
401 | int result; | |
b3b8df97 | 402 | const struct i2c_adapter *adap = &priv->adapter; |
ca8b9e32 | 403 | |
6cad93c4 JD |
404 | result = i801_check_pre(priv); |
405 | if (result < 0) | |
406 | return result; | |
4ccc28f7 | 407 | |
636752bc DK |
408 | if (priv->features & FEATURE_IRQ) { |
409 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
410 | SMBHSTCNT(priv)); | |
b3b8df97 JD |
411 | result = wait_event_timeout(priv->waitq, |
412 | (status = priv->status), | |
413 | adap->timeout); | |
414 | if (!result) { | |
415 | status = -ETIMEDOUT; | |
416 | dev_warn(&priv->pci_dev->dev, | |
417 | "Timeout waiting for interrupt!\n"); | |
418 | } | |
636752bc DK |
419 | priv->status = 0; |
420 | return i801_check_post(priv, status); | |
421 | } | |
422 | ||
6cad93c4 JD |
423 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
424 | * SMBSCMD are passed in xact */ | |
425 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
426 | ||
427 | status = i801_wait_intr(priv); | |
428 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
429 | } |
430 | ||
0cd96eb0 DW |
431 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
432 | union i2c_smbus_data *data, | |
7edcb9ab OR |
433 | char read_write, int hwpec) |
434 | { | |
435 | int i, len; | |
97140342 | 436 | int status; |
7edcb9ab | 437 | |
0cd96eb0 | 438 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
439 | |
440 | /* Use 32-byte buffer to process this transaction */ | |
441 | if (read_write == I2C_SMBUS_WRITE) { | |
442 | len = data->block[0]; | |
0cd96eb0 | 443 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 444 | for (i = 0; i < len; i++) |
0cd96eb0 | 445 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
446 | } |
447 | ||
37af8711 | 448 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 449 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
450 | if (status) |
451 | return status; | |
7edcb9ab OR |
452 | |
453 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 454 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 455 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 456 | return -EPROTO; |
7edcb9ab OR |
457 | |
458 | data->block[0] = len; | |
459 | for (i = 0; i < len; i++) | |
0cd96eb0 | 460 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
461 | } |
462 | return 0; | |
463 | } | |
464 | ||
d3ff6ce4 DK |
465 | static void i801_isr_byte_done(struct i801_priv *priv) |
466 | { | |
467 | if (priv->is_read) { | |
468 | /* For SMBus block reads, length is received with first byte */ | |
469 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
470 | (priv->count == 0)) { | |
471 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
472 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
473 | dev_err(&priv->pci_dev->dev, | |
474 | "Illegal SMBus block read size %d\n", | |
475 | priv->len); | |
476 | /* FIXME: Recover */ | |
477 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
478 | } else { | |
479 | dev_dbg(&priv->pci_dev->dev, | |
480 | "SMBus block read size is %d\n", | |
481 | priv->len); | |
482 | } | |
483 | priv->data[-1] = priv->len; | |
484 | } | |
485 | ||
486 | /* Read next byte */ | |
487 | if (priv->count < priv->len) | |
488 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
489 | else | |
490 | dev_dbg(&priv->pci_dev->dev, | |
491 | "Discarding extra byte on block read\n"); | |
492 | ||
493 | /* Set LAST_BYTE for last byte of read transaction */ | |
494 | if (priv->count == priv->len - 1) | |
495 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
496 | SMBHSTCNT(priv)); | |
497 | } else if (priv->count < priv->len - 1) { | |
498 | /* Write next byte, except for IRQ after last byte */ | |
499 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
500 | } | |
501 | ||
502 | /* Clear BYTE_DONE to continue with next byte */ | |
503 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
504 | } | |
505 | ||
636752bc | 506 | /* |
d3ff6ce4 DK |
507 | * There are two kinds of interrupts: |
508 | * | |
509 | * 1) i801 signals transaction completion with one of these interrupts: | |
510 | * INTR - Success | |
511 | * DEV_ERR - Invalid command, NAK or communication timeout | |
512 | * BUS_ERR - SMI# transaction collision | |
513 | * FAILED - transaction was canceled due to a KILL request | |
514 | * When any of these occur, update ->status and wake up the waitq. | |
515 | * ->status must be cleared before kicking off the next transaction. | |
516 | * | |
517 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
518 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
519 | */ |
520 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
521 | { | |
522 | struct i801_priv *priv = dev_id; | |
523 | u16 pcists; | |
524 | u8 status; | |
525 | ||
526 | /* Confirm this is our interrupt */ | |
527 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
528 | if (!(pcists & SMBPCISTS_INTS)) | |
529 | return IRQ_NONE; | |
530 | ||
531 | status = inb_p(SMBHSTSTS(priv)); | |
d3ff6ce4 DK |
532 | if (status & SMBHSTSTS_BYTE_DONE) |
533 | i801_isr_byte_done(priv); | |
534 | ||
636752bc DK |
535 | /* |
536 | * Clear irq sources and report transaction result. | |
537 | * ->status must be cleared before the next transaction is started. | |
538 | */ | |
539 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
540 | if (status) { | |
541 | outb_p(status, SMBHSTSTS(priv)); | |
542 | priv->status |= status; | |
543 | wake_up(&priv->waitq); | |
544 | } | |
545 | ||
546 | return IRQ_HANDLED; | |
547 | } | |
548 | ||
efa3cb15 DK |
549 | /* |
550 | * For "byte-by-byte" block transactions: | |
551 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
552 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
553 | */ | |
0cd96eb0 DW |
554 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
555 | union i2c_smbus_data *data, | |
6342064c JD |
556 | char read_write, int command, |
557 | int hwpec) | |
1da177e4 LT |
558 | { |
559 | int i, len; | |
560 | int smbcmd; | |
2b73809d | 561 | int status; |
cf898dc5 | 562 | int result; |
b3b8df97 | 563 | const struct i2c_adapter *adap = &priv->adapter; |
cf898dc5 | 564 | |
0cd96eb0 | 565 | result = i801_check_pre(priv); |
cf898dc5 JD |
566 | if (result < 0) |
567 | return result; | |
1da177e4 | 568 | |
7edcb9ab | 569 | len = data->block[0]; |
1da177e4 LT |
570 | |
571 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
572 | outb_p(len, SMBHSTDAT0(priv)); |
573 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
574 | } |
575 | ||
efa3cb15 DK |
576 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
577 | read_write == I2C_SMBUS_READ) | |
578 | smbcmd = I801_I2C_BLOCK_DATA; | |
579 | else | |
580 | smbcmd = I801_BLOCK_DATA; | |
581 | ||
d3ff6ce4 DK |
582 | if (priv->features & FEATURE_IRQ) { |
583 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
584 | if (len == 1 && priv->is_read) | |
585 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
586 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
587 | priv->len = len; | |
588 | priv->count = 0; | |
589 | priv->data = &data->block[1]; | |
590 | ||
591 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
b3b8df97 JD |
592 | result = wait_event_timeout(priv->waitq, |
593 | (status = priv->status), | |
594 | adap->timeout); | |
595 | if (!result) { | |
596 | status = -ETIMEDOUT; | |
597 | dev_warn(&priv->pci_dev->dev, | |
598 | "Timeout waiting for interrupt!\n"); | |
599 | } | |
d3ff6ce4 DK |
600 | priv->status = 0; |
601 | return i801_check_post(priv, status); | |
602 | } | |
603 | ||
1da177e4 | 604 | for (i = 1; i <= len; i++) { |
efa3cb15 | 605 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 606 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 607 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 608 | |
1da177e4 | 609 | if (i == 1) |
edbeea63 | 610 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 611 | SMBHSTCNT(priv)); |
1da177e4 | 612 | |
6cad93c4 JD |
613 | status = i801_wait_byte_done(priv); |
614 | if (status) | |
615 | goto exit; | |
1da177e4 | 616 | |
6342064c JD |
617 | if (i == 1 && read_write == I2C_SMBUS_READ |
618 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 619 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 620 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 621 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
622 | "Illegal SMBus block read size %d\n", |
623 | len); | |
624 | /* Recover */ | |
0cd96eb0 DW |
625 | while (inb_p(SMBHSTSTS(priv)) & |
626 | SMBHSTSTS_HOST_BUSY) | |
627 | outb_p(SMBHSTSTS_BYTE_DONE, | |
628 | SMBHSTSTS(priv)); | |
629 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 630 | return -EPROTO; |
cf898dc5 | 631 | } |
1da177e4 LT |
632 | data->block[0] = len; |
633 | } | |
634 | ||
635 | /* Retrieve/store value in SMBBLKDAT */ | |
636 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 637 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 638 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 639 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 640 | |
cf898dc5 | 641 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 642 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 643 | } |
cf898dc5 | 644 | |
6cad93c4 JD |
645 | status = i801_wait_intr(priv); |
646 | exit: | |
647 | return i801_check_post(priv, status); | |
7edcb9ab | 648 | } |
1da177e4 | 649 | |
0cd96eb0 | 650 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 651 | { |
0cd96eb0 DW |
652 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
653 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 654 | return -EIO; |
7edcb9ab OR |
655 | return 0; |
656 | } | |
657 | ||
658 | /* Block transaction function */ | |
0cd96eb0 DW |
659 | static int i801_block_transaction(struct i801_priv *priv, |
660 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
661 | int command, int hwpec) |
662 | { | |
663 | int result = 0; | |
664 | unsigned char hostc; | |
665 | ||
666 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
667 | if (read_write == I2C_SMBUS_WRITE) { | |
668 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
669 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
670 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 671 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
672 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
673 | dev_err(&priv->pci_dev->dev, | |
6342064c | 674 | "I2C block read is unsupported!\n"); |
97140342 | 675 | return -EOPNOTSUPP; |
7edcb9ab OR |
676 | } |
677 | } | |
678 | ||
6342064c JD |
679 | if (read_write == I2C_SMBUS_WRITE |
680 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
681 | if (data->block[0] < 1) |
682 | data->block[0] = 1; | |
683 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
684 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
685 | } else { | |
6342064c | 686 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
687 | } |
688 | ||
c074c39d JD |
689 | /* Experience has shown that the block buffer can only be used for |
690 | SMBus (not I2C) block transactions, even though the datasheet | |
691 | doesn't mention this limitation. */ | |
0cd96eb0 | 692 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 693 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
694 | && i801_set_block_buffer_mode(priv) == 0) |
695 | result = i801_block_transaction_by_block(priv, data, | |
696 | read_write, hwpec); | |
7edcb9ab | 697 | else |
0cd96eb0 DW |
698 | result = i801_block_transaction_byte_by_byte(priv, data, |
699 | read_write, | |
6342064c | 700 | command, hwpec); |
7edcb9ab | 701 | |
6342064c JD |
702 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
703 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 704 | /* restore saved configuration register value */ |
0cd96eb0 | 705 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
706 | } |
707 | return result; | |
708 | } | |
709 | ||
97140342 | 710 | /* Return negative errno on error. */ |
3fb21c64 | 711 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 712 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 713 | int size, union i2c_smbus_data *data) |
1da177e4 | 714 | { |
e8aac4a9 | 715 | int hwpec; |
1da177e4 LT |
716 | int block = 0; |
717 | int ret, xact = 0; | |
0cd96eb0 | 718 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 719 | |
0cd96eb0 | 720 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
721 | && size != I2C_SMBUS_QUICK |
722 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
723 | |
724 | switch (size) { | |
725 | case I2C_SMBUS_QUICK: | |
726 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 727 | SMBHSTADD(priv)); |
1da177e4 LT |
728 | xact = I801_QUICK; |
729 | break; | |
730 | case I2C_SMBUS_BYTE: | |
731 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 732 | SMBHSTADD(priv)); |
1da177e4 | 733 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 734 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
735 | xact = I801_BYTE; |
736 | break; | |
737 | case I2C_SMBUS_BYTE_DATA: | |
738 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
739 | SMBHSTADD(priv)); |
740 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 741 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 742 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
743 | xact = I801_BYTE_DATA; |
744 | break; | |
745 | case I2C_SMBUS_WORD_DATA: | |
746 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
747 | SMBHSTADD(priv)); |
748 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 749 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
750 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
751 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
752 | } |
753 | xact = I801_WORD_DATA; | |
754 | break; | |
755 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 756 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
757 | SMBHSTADD(priv)); |
758 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
759 | block = 1; |
760 | break; | |
6342064c JD |
761 | case I2C_SMBUS_I2C_BLOCK_DATA: |
762 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
763 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 764 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
765 | if (read_write == I2C_SMBUS_READ) { |
766 | /* NB: page 240 of ICH5 datasheet also shows | |
767 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 768 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 769 | } else |
0cd96eb0 | 770 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
771 | block = 1; |
772 | break; | |
1da177e4 | 773 | default: |
0cd96eb0 DW |
774 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
775 | size); | |
97140342 | 776 | return -EOPNOTSUPP; |
1da177e4 LT |
777 | } |
778 | ||
ca8b9e32 | 779 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 780 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 781 | else |
0cd96eb0 DW |
782 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
783 | SMBAUXCTL(priv)); | |
e8aac4a9 | 784 | |
3fb21c64 | 785 | if (block) |
0cd96eb0 DW |
786 | ret = i801_block_transaction(priv, data, read_write, size, |
787 | hwpec); | |
7edcb9ab | 788 | else |
37af8711 | 789 | ret = i801_transaction(priv, xact); |
1da177e4 | 790 | |
c79cfbac | 791 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
792 | time, so we forcibly disable it after every transaction. Turn off |
793 | E32B for the same reason. */ | |
a0921b6c | 794 | if (hwpec || block) |
0cd96eb0 DW |
795 | outb_p(inb_p(SMBAUXCTL(priv)) & |
796 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 797 | |
3fb21c64 | 798 | if (block) |
1da177e4 | 799 | return ret; |
3fb21c64 | 800 | if (ret) |
97140342 | 801 | return ret; |
1da177e4 LT |
802 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
803 | return 0; | |
804 | ||
805 | switch (xact & 0x7f) { | |
806 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
807 | case I801_BYTE_DATA: | |
0cd96eb0 | 808 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
809 | break; |
810 | case I801_WORD_DATA: | |
0cd96eb0 DW |
811 | data->word = inb_p(SMBHSTDAT0(priv)) + |
812 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
813 | break; |
814 | } | |
815 | return 0; | |
816 | } | |
817 | ||
818 | ||
819 | static u32 i801_func(struct i2c_adapter *adapter) | |
820 | { | |
0cd96eb0 DW |
821 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
822 | ||
1da177e4 | 823 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
824 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
825 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
826 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
827 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 828 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
829 | } |
830 | ||
8f9082c5 | 831 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
832 | .smbus_xfer = i801_access, |
833 | .functionality = i801_func, | |
834 | }; | |
835 | ||
392debf1 | 836 | static const struct pci_device_id i801_ids[] = { |
1da177e4 LT |
837 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
838 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
839 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
840 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
841 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
842 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
843 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
844 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
845 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 846 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 847 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 848 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 849 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
850 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
851 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
852 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
853 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 854 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
855 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
856 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
857 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 858 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 859 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 860 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 861 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
c2db409c | 862 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, |
a3fc0ff0 JR |
863 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, |
864 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, | |
865 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, | |
866 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, | |
f39901c1 | 867 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, |
b299de83 | 868 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, |
afc65924 | 869 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, |
1b31e9b7 | 870 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, |
39e8e30e | 871 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, |
3e27a844 | 872 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, |
3eee1799 | 873 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, |
84d7f2eb | 874 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, |
dd77f423 | 875 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, |
cdc5a311 AY |
876 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, |
877 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, | |
1da177e4 LT |
878 | { 0, } |
879 | }; | |
880 | ||
3fb21c64 | 881 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 882 | |
8eacfceb | 883 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
884 | static unsigned char apanel_addr; |
885 | ||
886 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
887 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
888 | { | |
889 | ssize_t offset; | |
890 | const unsigned char signature[] = "FJKEYINF"; | |
891 | ||
892 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
893 | if (check_signature(bios + offset, signature, | |
894 | sizeof(signature)-1)) | |
895 | return bios + offset; | |
896 | } | |
897 | return NULL; | |
898 | } | |
899 | ||
900 | static void __init input_apanel_init(void) | |
901 | { | |
902 | void __iomem *bios; | |
903 | const void __iomem *p; | |
904 | ||
905 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
906 | p = bios_signature(bios); | |
907 | if (p) { | |
908 | /* just use the first address */ | |
909 | apanel_addr = readb(p + 8 + 3) >> 1; | |
910 | } | |
911 | iounmap(bios); | |
912 | } | |
1561bfe5 | 913 | |
fa5bfab7 HG |
914 | struct dmi_onboard_device_info { |
915 | const char *name; | |
916 | u8 type; | |
917 | unsigned short i2c_addr; | |
918 | const char *i2c_type; | |
919 | }; | |
920 | ||
0b255e92 | 921 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
922 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
923 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
924 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
925 | }; | |
926 | ||
0b255e92 BP |
927 | static void dmi_check_onboard_device(u8 type, const char *name, |
928 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
929 | { |
930 | int i; | |
931 | struct i2c_board_info info; | |
932 | ||
933 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
934 | /* & ~0x80, ignore enabled/disabled bit */ | |
935 | if ((type & ~0x80) != dmi_devices[i].type) | |
936 | continue; | |
faabd47f | 937 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
938 | continue; |
939 | ||
940 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
941 | info.addr = dmi_devices[i].i2c_addr; | |
942 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
943 | i2c_new_device(adap, &info); | |
944 | break; | |
945 | } | |
946 | } | |
947 | ||
948 | /* We use our own function to check for onboard devices instead of | |
949 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
950 | in marked as disabled */ | |
0b255e92 | 951 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
952 | { |
953 | int i, count; | |
954 | ||
955 | if (dm->type != 10) | |
956 | return; | |
957 | ||
958 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
959 | for (i = 0; i < count; i++) { | |
960 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
961 | const char *name = ((char *) dm) + dm->length; | |
962 | u8 type = d[0]; | |
963 | u8 s = d[1]; | |
964 | ||
965 | if (!s) | |
966 | continue; | |
967 | s--; | |
968 | while (s > 0 && name[0]) { | |
969 | name += strlen(name) + 1; | |
970 | s--; | |
971 | } | |
972 | if (name[0] == 0) /* Bogus string reference */ | |
973 | continue; | |
974 | ||
975 | dmi_check_onboard_device(type, name, adap); | |
976 | } | |
977 | } | |
fa5bfab7 | 978 | |
e7198fbf | 979 | /* Register optional slaves */ |
0b255e92 | 980 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
981 | { |
982 | /* Only register slaves on main SMBus channel */ | |
983 | if (priv->features & FEATURE_IDF) | |
984 | return; | |
985 | ||
e7198fbf JD |
986 | if (apanel_addr) { |
987 | struct i2c_board_info info; | |
988 | ||
989 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
990 | info.addr = apanel_addr; | |
991 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
992 | i2c_new_device(&priv->adapter, &info); | |
993 | } | |
8eacfceb | 994 | |
e7198fbf JD |
995 | if (dmi_name_in_vendors("FUJITSU")) |
996 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 997 | } |
8eacfceb JD |
998 | #else |
999 | static void __init input_apanel_init(void) {} | |
0b255e92 | 1000 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 1001 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 1002 | |
79e3e5b8 JD |
1003 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
1004 | defined CONFIG_DMI | |
3ad7ea18 JD |
1005 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
1006 | .gpio_chip = "gpio_ich", | |
1007 | .values = { 0x02, 0x03 }, | |
1008 | .n_values = 2, | |
1009 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
1010 | .gpios = { 52, 53 }, | |
1011 | .n_gpios = 2, | |
1012 | }; | |
1013 | ||
1014 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
1015 | .gpio_chip = "gpio_ich", | |
1016 | .values = { 0x02, 0x03, 0x01 }, | |
1017 | .n_values = 3, | |
1018 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
1019 | .gpios = { 52, 53 }, | |
1020 | .n_gpios = 2, | |
1021 | }; | |
1022 | ||
0b255e92 | 1023 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
1024 | { |
1025 | .matches = { | |
1026 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1027 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
1028 | }, | |
1029 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1030 | }, | |
1031 | { | |
1032 | .matches = { | |
1033 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1034 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
1035 | }, | |
1036 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1037 | }, | |
1038 | { | |
1039 | .matches = { | |
1040 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1041 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
1042 | }, | |
1043 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1044 | }, | |
1045 | { | |
1046 | .matches = { | |
1047 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1048 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
1049 | }, | |
1050 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1051 | }, | |
1052 | { | |
1053 | .matches = { | |
1054 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1055 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
1056 | }, | |
1057 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1058 | }, | |
1059 | { | |
1060 | .matches = { | |
1061 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1062 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
1063 | }, | |
1064 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1065 | }, | |
1066 | { | |
1067 | .matches = { | |
1068 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1069 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
1070 | }, | |
1071 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1072 | }, | |
1073 | { | |
1074 | .matches = { | |
1075 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1076 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1077 | }, | |
1078 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1079 | }, | |
1080 | { | |
1081 | .matches = { | |
1082 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1083 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1084 | }, | |
1085 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1086 | }, | |
1087 | { } | |
1088 | }; | |
1089 | ||
3ad7ea18 | 1090 | /* Setup multiplexing if needed */ |
0b255e92 | 1091 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1092 | { |
1093 | struct device *dev = &priv->adapter.dev; | |
1094 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1095 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1096 | int err; |
3ad7ea18 JD |
1097 | |
1098 | if (!priv->mux_drvdata) | |
1099 | return 0; | |
1100 | mux_config = priv->mux_drvdata; | |
1101 | ||
3ad7ea18 JD |
1102 | /* Prepare the platform data */ |
1103 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1104 | gpio_data.parent = priv->adapter.nr; | |
1105 | gpio_data.values = mux_config->values; | |
1106 | gpio_data.n_values = mux_config->n_values; | |
1107 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1108 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1109 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1110 | gpio_data.n_gpios = mux_config->n_gpios; |
1111 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1112 | ||
1113 | /* Register the mux device */ | |
1114 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1115 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1116 | sizeof(struct i2c_mux_gpio_platform_data)); |
1117 | if (IS_ERR(priv->mux_pdev)) { | |
1118 | err = PTR_ERR(priv->mux_pdev); | |
1119 | priv->mux_pdev = NULL; | |
1120 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1121 | return err; | |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
0b255e92 | 1127 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1128 | { |
1129 | if (priv->mux_pdev) | |
1130 | platform_device_unregister(priv->mux_pdev); | |
1131 | } | |
1132 | ||
0b255e92 | 1133 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1134 | { |
1135 | const struct dmi_system_id *id; | |
1136 | const struct i801_mux_config *mux_config; | |
1137 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1138 | int i; | |
1139 | ||
1140 | id = dmi_first_match(mux_dmi_table); | |
1141 | if (id) { | |
28901f57 | 1142 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1143 | mux_config = id->driver_data; |
1144 | for (i = 0; i < mux_config->n_values; i++) | |
1145 | class &= ~mux_config->classes[i]; | |
1146 | ||
1147 | /* Remember for later */ | |
1148 | priv->mux_drvdata = mux_config; | |
1149 | } | |
1150 | ||
1151 | return class; | |
1152 | } | |
1153 | #else | |
1154 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1155 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1156 | ||
1157 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1158 | { | |
1159 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1160 | } | |
1161 | #endif | |
1162 | ||
94246930 MW |
1163 | static const struct itco_wdt_platform_data tco_platform_data = { |
1164 | .name = "Intel PCH", | |
1165 | .version = 4, | |
1166 | }; | |
1167 | ||
1168 | static DEFINE_SPINLOCK(p2sb_spinlock); | |
1169 | ||
1170 | static void i801_add_tco(struct i801_priv *priv) | |
1171 | { | |
1172 | struct pci_dev *pci_dev = priv->pci_dev; | |
1173 | struct resource tco_res[3], *res; | |
1174 | struct platform_device *pdev; | |
1175 | unsigned int devfn; | |
1176 | u32 tco_base, tco_ctl; | |
1177 | u32 base_addr, ctrl_val; | |
1178 | u64 base64_addr; | |
1179 | ||
1180 | if (!(priv->features & FEATURE_TCO)) | |
1181 | return; | |
1182 | ||
1183 | pci_read_config_dword(pci_dev, TCOBASE, &tco_base); | |
1184 | pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); | |
1185 | if (!(tco_ctl & TCOCTL_EN)) | |
1186 | return; | |
1187 | ||
1188 | memset(tco_res, 0, sizeof(tco_res)); | |
1189 | ||
1190 | res = &tco_res[ICH_RES_IO_TCO]; | |
1191 | res->start = tco_base & ~1; | |
1192 | res->end = res->start + 32 - 1; | |
1193 | res->flags = IORESOURCE_IO; | |
1194 | ||
1195 | /* | |
1196 | * Power Management registers. | |
1197 | */ | |
1198 | devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); | |
1199 | pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); | |
1200 | ||
1201 | res = &tco_res[ICH_RES_IO_SMI]; | |
1202 | res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; | |
1203 | res->end = res->start + 3; | |
1204 | res->flags = IORESOURCE_IO; | |
1205 | ||
1206 | /* | |
1207 | * Enable the ACPI I/O space. | |
1208 | */ | |
1209 | pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); | |
1210 | ctrl_val |= ACPICTRL_EN; | |
1211 | pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); | |
1212 | ||
1213 | /* | |
1214 | * We must access the NO_REBOOT bit over the Primary to Sideband | |
1215 | * bridge (P2SB). The BIOS prevents the P2SB device from being | |
1216 | * enumerated by the PCI subsystem, so we need to unhide/hide it | |
1217 | * to lookup the P2SB BAR. | |
1218 | */ | |
1219 | spin_lock(&p2sb_spinlock); | |
1220 | ||
1221 | devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); | |
1222 | ||
1223 | /* Unhide the P2SB device */ | |
1224 | pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); | |
1225 | ||
1226 | pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); | |
1227 | base64_addr = base_addr & 0xfffffff0; | |
1228 | ||
1229 | pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); | |
1230 | base64_addr |= (u64)base_addr << 32; | |
1231 | ||
1232 | /* Hide the P2SB device */ | |
1233 | pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1); | |
1234 | spin_unlock(&p2sb_spinlock); | |
1235 | ||
1236 | res = &tco_res[ICH_RES_MEM_OFF]; | |
1237 | res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; | |
1238 | res->end = res->start + 3; | |
1239 | res->flags = IORESOURCE_MEM; | |
1240 | ||
1241 | pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, | |
1242 | tco_res, 3, &tco_platform_data, | |
1243 | sizeof(tco_platform_data)); | |
1244 | if (IS_ERR(pdev)) { | |
1245 | dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); | |
1246 | return; | |
1247 | } | |
1248 | ||
1249 | priv->tco_pdev = pdev; | |
1250 | } | |
1251 | ||
0b255e92 | 1252 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1253 | { |
02dd7ae2 | 1254 | unsigned char temp; |
adff687d | 1255 | int err, i; |
0cd96eb0 DW |
1256 | struct i801_priv *priv; |
1257 | ||
1621c59d | 1258 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); |
0cd96eb0 DW |
1259 | if (!priv) |
1260 | return -ENOMEM; | |
1261 | ||
1262 | i2c_set_adapdata(&priv->adapter, priv); | |
1263 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1264 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1265 | priv->adapter.algo = &smbus_algorithm; |
8eb5c87a DB |
1266 | priv->adapter.dev.parent = &dev->dev; |
1267 | ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); | |
1268 | priv->adapter.retries = 3; | |
1da177e4 | 1269 | |
0cd96eb0 | 1270 | priv->pci_dev = dev; |
250d1bd3 | 1271 | switch (dev->device) { |
94246930 MW |
1272 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: |
1273 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: | |
1a1503c5 AY |
1274 | case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: |
1275 | case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: | |
84d7f2eb | 1276 | case PCI_DEVICE_ID_INTEL_DNV_SMBUS: |
94246930 MW |
1277 | priv->features |= FEATURE_I2C_BLOCK_READ; |
1278 | priv->features |= FEATURE_IRQ; | |
1279 | priv->features |= FEATURE_SMBUS_PEC; | |
1280 | priv->features |= FEATURE_BLOCK_BUFFER; | |
1281 | priv->features |= FEATURE_TCO; | |
1282 | break; | |
1283 | ||
e7198fbf JD |
1284 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1285 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1286 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
a3fc0ff0 JR |
1287 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: |
1288 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: | |
1289 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: | |
e7198fbf JD |
1290 | priv->features |= FEATURE_IDF; |
1291 | /* fall through */ | |
e0e8398c | 1292 | default: |
0cd96eb0 | 1293 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1294 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1295 | /* fall through */ |
1296 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1297 | priv->features |= FEATURE_SMBUS_PEC; |
1298 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1299 | /* fall through */ |
1300 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
1301 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
1302 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1303 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1304 | break; |
250d1bd3 | 1305 | } |
02dd7ae2 | 1306 | |
adff687d JD |
1307 | /* Disable features on user request */ |
1308 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1309 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1310 | dev_notice(&dev->dev, "%s disabled by user\n", |
1311 | i801_feature_names[i]); | |
1312 | } | |
0cd96eb0 | 1313 | priv->features &= ~disable_features; |
adff687d | 1314 | |
fef220da | 1315 | err = pcim_enable_device(dev); |
02dd7ae2 JD |
1316 | if (err) { |
1317 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1318 | err); | |
fef220da | 1319 | return err; |
02dd7ae2 | 1320 | } |
fef220da | 1321 | pcim_pin_device(dev); |
02dd7ae2 JD |
1322 | |
1323 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1324 | priv->smba = pci_resource_start(dev, SMBBAR); |
1325 | if (!priv->smba) { | |
9cbbf3dc JN |
1326 | dev_err(&dev->dev, |
1327 | "SMBus base address uninitialized, upgrade BIOS\n"); | |
fef220da | 1328 | return -ENODEV; |
02dd7ae2 JD |
1329 | } |
1330 | ||
54fb4a05 | 1331 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab | 1332 | if (err) { |
fef220da | 1333 | return -ENODEV; |
18669eab | 1334 | } |
54fb4a05 | 1335 | |
fef220da JN |
1336 | err = pcim_iomap_regions(dev, 1 << SMBBAR, |
1337 | dev_driver_string(&dev->dev)); | |
02dd7ae2 | 1338 | if (err) { |
9cbbf3dc JN |
1339 | dev_err(&dev->dev, |
1340 | "Failed to request SMBus region 0x%lx-0x%Lx\n", | |
1341 | priv->smba, | |
598736c5 | 1342 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
fef220da | 1343 | return err; |
02dd7ae2 JD |
1344 | } |
1345 | ||
0cd96eb0 DW |
1346 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1347 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1348 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1349 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1350 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1351 | temp |= SMBHSTCFG_HST_EN; | |
1352 | } | |
0cd96eb0 | 1353 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1354 | |
636752bc | 1355 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1356 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1357 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1358 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1359 | } |
1da177e4 | 1360 | |
a0921b6c | 1361 | /* Clear special mode bits */ |
0cd96eb0 DW |
1362 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1363 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1364 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1365 | |
b3b8df97 JD |
1366 | /* Default timeout in interrupt mode: 200 ms */ |
1367 | priv->adapter.timeout = HZ / 5; | |
1368 | ||
aeb8a3d1 JD |
1369 | if (priv->features & FEATURE_IRQ) { |
1370 | u16 pcictl, pcists; | |
1371 | ||
1372 | /* Complain if an interrupt is already pending */ | |
1373 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
1374 | if (pcists & SMBPCISTS_INTS) | |
1375 | dev_warn(&dev->dev, "An interrupt is pending!\n"); | |
1376 | ||
1377 | /* Check if interrupts have been disabled */ | |
1378 | pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); | |
1379 | if (pcictl & SMBPCICTL_INTDIS) { | |
1380 | dev_info(&dev->dev, "Interrupts are disabled\n"); | |
1381 | priv->features &= ~FEATURE_IRQ; | |
1382 | } | |
1383 | } | |
1384 | ||
636752bc DK |
1385 | if (priv->features & FEATURE_IRQ) { |
1386 | init_waitqueue_head(&priv->waitq); | |
1387 | ||
1621c59d JN |
1388 | err = devm_request_irq(&dev->dev, dev->irq, i801_isr, |
1389 | IRQF_SHARED, | |
1390 | dev_driver_string(&dev->dev), priv); | |
636752bc DK |
1391 | if (err) { |
1392 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1393 | dev->irq, err); | |
ae944717 | 1394 | priv->features &= ~FEATURE_IRQ; |
636752bc DK |
1395 | } |
1396 | } | |
ae944717 JD |
1397 | dev_info(&dev->dev, "SMBus using %s\n", |
1398 | priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); | |
636752bc | 1399 | |
94246930 MW |
1400 | i801_add_tco(priv); |
1401 | ||
0cd96eb0 DW |
1402 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1403 | "SMBus I801 adapter at %04lx", priv->smba); | |
1404 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1405 | if (err) { |
1406 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
fef220da | 1407 | return err; |
02dd7ae2 | 1408 | } |
1561bfe5 | 1409 | |
e7198fbf | 1410 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1411 | /* We ignore errors - multiplexing is optional */ |
1412 | i801_add_mux(priv); | |
1561bfe5 | 1413 | |
0cd96eb0 | 1414 | pci_set_drvdata(dev, priv); |
636752bc | 1415 | |
d6fcb3b9 | 1416 | return 0; |
1da177e4 LT |
1417 | } |
1418 | ||
0b255e92 | 1419 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1420 | { |
0cd96eb0 DW |
1421 | struct i801_priv *priv = pci_get_drvdata(dev); |
1422 | ||
3ad7ea18 | 1423 | i801_del_mux(priv); |
0cd96eb0 DW |
1424 | i2c_del_adapter(&priv->adapter); |
1425 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc | 1426 | |
94246930 MW |
1427 | platform_device_unregister(priv->tco_pdev); |
1428 | ||
d6fcb3b9 DR |
1429 | /* |
1430 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1431 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1432 | */ | |
1da177e4 LT |
1433 | } |
1434 | ||
a5aaea37 JD |
1435 | #ifdef CONFIG_PM |
1436 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
1437 | { | |
0cd96eb0 DW |
1438 | struct i801_priv *priv = pci_get_drvdata(dev); |
1439 | ||
a5aaea37 | 1440 | pci_save_state(dev); |
0cd96eb0 | 1441 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1442 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | static int i801_resume(struct pci_dev *dev) | |
1447 | { | |
1448 | pci_set_power_state(dev, PCI_D0); | |
1449 | pci_restore_state(dev); | |
f85da3f5 | 1450 | return 0; |
a5aaea37 JD |
1451 | } |
1452 | #else | |
1453 | #define i801_suspend NULL | |
1454 | #define i801_resume NULL | |
1455 | #endif | |
1456 | ||
1da177e4 LT |
1457 | static struct pci_driver i801_driver = { |
1458 | .name = "i801_smbus", | |
1459 | .id_table = i801_ids, | |
1460 | .probe = i801_probe, | |
0b255e92 | 1461 | .remove = i801_remove, |
a5aaea37 JD |
1462 | .suspend = i801_suspend, |
1463 | .resume = i801_resume, | |
1da177e4 LT |
1464 | }; |
1465 | ||
1466 | static int __init i2c_i801_init(void) | |
1467 | { | |
6aa1464d JD |
1468 | if (dmi_name_in_vendors("FUJITSU")) |
1469 | input_apanel_init(); | |
1da177e4 LT |
1470 | return pci_register_driver(&i801_driver); |
1471 | } | |
1472 | ||
1473 | static void __exit i2c_i801_exit(void) | |
1474 | { | |
1475 | pci_unregister_driver(&i801_driver); | |
1476 | } | |
1477 | ||
7c81c60f | 1478 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); |
1da177e4 LT |
1479 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1480 | MODULE_LICENSE("GPL"); | |
1481 | ||
1482 | module_init(i2c_i801_init); | |
1483 | module_exit(i2c_i801_exit); |