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Commit | Line | Data |
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1da177e4 | 1 | /* |
455f3323 | 2 | i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware |
1da177e4 LT |
3 | monitoring |
4 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, | |
5 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
6 | <mdsxyz123@yahoo.com> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
ae7b0497 JD |
24 | Supports the following Intel I/O Controller Hubs (ICH): |
25 | ||
26 | I/O Block I2C | |
27 | region SMBus Block proc. block | |
28 | Chip name PCI ID size PEC buffer call read | |
29 | ---------------------------------------------------------------------- | |
30 | 82801AA (ICH) 0x2413 16 no no no no | |
31 | 82801AB (ICH0) 0x2423 16 no no no no | |
32 | 82801BA (ICH2) 0x2443 16 no no no no | |
33 | 82801CA (ICH3) 0x2483 32 soft no no no | |
34 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
35 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
36 | 6300ESB 0x25a4 32 hard yes yes yes | |
37 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
38 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
39 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
40 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
41 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
42 | Tolapai 0x5032 32 hard yes ? ? | |
43 | ||
44 | Features supported by this driver: | |
45 | Software PEC no | |
46 | Hardware PEC yes | |
47 | Block buffer yes | |
48 | Block process call transaction no | |
49 | I2C block read transaction no | |
50 | ||
51 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
52 | */ |
53 | ||
54 | /* Note: we assume there can only be one I801, with one SMBus interface */ | |
55 | ||
1da177e4 LT |
56 | #include <linux/module.h> |
57 | #include <linux/pci.h> | |
58 | #include <linux/kernel.h> | |
59 | #include <linux/stddef.h> | |
60 | #include <linux/delay.h> | |
1da177e4 LT |
61 | #include <linux/ioport.h> |
62 | #include <linux/init.h> | |
63 | #include <linux/i2c.h> | |
64 | #include <asm/io.h> | |
65 | ||
1da177e4 LT |
66 | /* I801 SMBus address offsets */ |
67 | #define SMBHSTSTS (0 + i801_smba) | |
68 | #define SMBHSTCNT (2 + i801_smba) | |
69 | #define SMBHSTCMD (3 + i801_smba) | |
70 | #define SMBHSTADD (4 + i801_smba) | |
71 | #define SMBHSTDAT0 (5 + i801_smba) | |
72 | #define SMBHSTDAT1 (6 + i801_smba) | |
73 | #define SMBBLKDAT (7 + i801_smba) | |
ae7b0497 JD |
74 | #define SMBPEC (8 + i801_smba) /* ICH3 and later */ |
75 | #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */ | |
76 | #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */ | |
1da177e4 LT |
77 | |
78 | /* PCI Address Constants */ | |
6dcc19df | 79 | #define SMBBAR 4 |
1da177e4 | 80 | #define SMBHSTCFG 0x040 |
1da177e4 LT |
81 | |
82 | /* Host configuration bits for SMBHSTCFG */ | |
83 | #define SMBHSTCFG_HST_EN 1 | |
84 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
85 | #define SMBHSTCFG_I2C_EN 4 | |
86 | ||
ca8b9e32 OR |
87 | /* Auxillary control register bits, ICH4+ only */ |
88 | #define SMBAUXCTL_CRC 1 | |
89 | #define SMBAUXCTL_E32B 2 | |
90 | ||
91 | /* kill bit for SMBHSTCNT */ | |
92 | #define SMBHSTCNT_KILL 2 | |
93 | ||
1da177e4 LT |
94 | /* Other settings */ |
95 | #define MAX_TIMEOUT 100 | |
96 | #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ | |
97 | ||
98 | /* I801 command constants */ | |
99 | #define I801_QUICK 0x00 | |
100 | #define I801_BYTE 0x04 | |
101 | #define I801_BYTE_DATA 0x08 | |
102 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 103 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 LT |
104 | #define I801_BLOCK_DATA 0x14 |
105 | #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */ | |
106 | #define I801_BLOCK_LAST 0x34 | |
107 | #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */ | |
108 | #define I801_START 0x40 | |
ae7b0497 | 109 | #define I801_PEC_EN 0x80 /* ICH3 and later */ |
1da177e4 | 110 | |
ca8b9e32 OR |
111 | /* I801 Hosts Status register bits */ |
112 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
113 | #define SMBHSTSTS_INUSE_STS 0x40 | |
114 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
115 | #define SMBHSTSTS_FAILED 0x10 | |
116 | #define SMBHSTSTS_BUS_ERR 0x08 | |
117 | #define SMBHSTSTS_DEV_ERR 0x04 | |
118 | #define SMBHSTSTS_INTR 0x02 | |
119 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 120 | |
6dcc19df | 121 | static unsigned long i801_smba; |
a5aaea37 | 122 | static unsigned char i801_original_hstcfg; |
d6072f84 | 123 | static struct pci_driver i801_driver; |
1da177e4 | 124 | static struct pci_dev *I801_dev; |
369f6f4a JD |
125 | |
126 | #define FEATURE_SMBUS_PEC (1 << 0) | |
127 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
128 | #define FEATURE_BLOCK_PROC (1 << 2) | |
129 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
130 | static unsigned int i801_features; | |
1da177e4 | 131 | |
7edcb9ab | 132 | static int i801_transaction(int xact) |
1da177e4 LT |
133 | { |
134 | int temp; | |
135 | int result = 0; | |
136 | int timeout = 0; | |
137 | ||
368609c5 | 138 | dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
139 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
140 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
141 | inb_p(SMBHSTDAT1)); | |
142 | ||
143 | /* Make sure the SMBus host is ready to start transmitting */ | |
144 | /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */ | |
145 | if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { | |
541e6a02 | 146 | dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n", |
1da177e4 LT |
147 | temp); |
148 | outb_p(temp, SMBHSTSTS); | |
149 | if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { | |
150 | dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp); | |
151 | return -1; | |
152 | } else { | |
fcdd96ec | 153 | dev_dbg(&I801_dev->dev, "Successful!\n"); |
1da177e4 LT |
154 | } |
155 | } | |
156 | ||
7edcb9ab OR |
157 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
158 | * INTREN, SMBSCMD are passed in xact */ | |
159 | outb_p(xact | I801_START, SMBHSTCNT); | |
1da177e4 LT |
160 | |
161 | /* We will always wait for a fraction of a second! */ | |
162 | do { | |
163 | msleep(1); | |
164 | temp = inb_p(SMBHSTSTS); | |
ca8b9e32 | 165 | } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); |
1da177e4 LT |
166 | |
167 | /* If the SMBus is still busy, we give up */ | |
168 | if (timeout >= MAX_TIMEOUT) { | |
169 | dev_dbg(&I801_dev->dev, "SMBus Timeout!\n"); | |
170 | result = -1; | |
ca8b9e32 OR |
171 | /* try to stop the current command */ |
172 | dev_dbg(&I801_dev->dev, "Terminating the current operation\n"); | |
173 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | |
174 | msleep(1); | |
175 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT); | |
1da177e4 LT |
176 | } |
177 | ||
ca8b9e32 | 178 | if (temp & SMBHSTSTS_FAILED) { |
1da177e4 LT |
179 | result = -1; |
180 | dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n"); | |
181 | } | |
182 | ||
ca8b9e32 | 183 | if (temp & SMBHSTSTS_BUS_ERR) { |
1da177e4 LT |
184 | result = -1; |
185 | dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked " | |
186 | "until next hard reset. (sorry!)\n"); | |
187 | /* Clock stops and slave is stuck in mid-transmission */ | |
188 | } | |
189 | ||
ca8b9e32 | 190 | if (temp & SMBHSTSTS_DEV_ERR) { |
1da177e4 LT |
191 | result = -1; |
192 | dev_dbg(&I801_dev->dev, "Error: no response!\n"); | |
193 | } | |
194 | ||
195 | if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00) | |
196 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
197 | ||
198 | if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { | |
368609c5 | 199 | dev_dbg(&I801_dev->dev, "Failed reset at end of transaction " |
1da177e4 LT |
200 | "(%02x)\n", temp); |
201 | } | |
202 | dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, " | |
203 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), | |
204 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
205 | inb_p(SMBHSTDAT1)); | |
206 | return result; | |
207 | } | |
208 | ||
ca8b9e32 OR |
209 | /* wait for INTR bit as advised by Intel */ |
210 | static void i801_wait_hwpec(void) | |
211 | { | |
212 | int timeout = 0; | |
213 | int temp; | |
214 | ||
215 | do { | |
216 | msleep(1); | |
217 | temp = inb_p(SMBHSTSTS); | |
218 | } while ((!(temp & SMBHSTSTS_INTR)) | |
219 | && (timeout++ < MAX_TIMEOUT)); | |
220 | ||
221 | if (timeout >= MAX_TIMEOUT) { | |
222 | dev_dbg(&I801_dev->dev, "PEC Timeout!\n"); | |
223 | } | |
224 | outb_p(temp, SMBHSTSTS); | |
225 | } | |
226 | ||
7edcb9ab OR |
227 | static int i801_block_transaction_by_block(union i2c_smbus_data *data, |
228 | char read_write, int hwpec) | |
229 | { | |
230 | int i, len; | |
231 | ||
232 | inb_p(SMBHSTCNT); /* reset the data buffer index */ | |
233 | ||
234 | /* Use 32-byte buffer to process this transaction */ | |
235 | if (read_write == I2C_SMBUS_WRITE) { | |
236 | len = data->block[0]; | |
237 | outb_p(len, SMBHSTDAT0); | |
238 | for (i = 0; i < len; i++) | |
239 | outb_p(data->block[i+1], SMBBLKDAT); | |
240 | } | |
241 | ||
242 | if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 | | |
243 | I801_PEC_EN * hwpec)) | |
244 | return -1; | |
245 | ||
246 | if (read_write == I2C_SMBUS_READ) { | |
247 | len = inb_p(SMBHSTDAT0); | |
248 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) | |
249 | return -1; | |
250 | ||
251 | data->block[0] = len; | |
252 | for (i = 0; i < len; i++) | |
253 | data->block[i + 1] = inb_p(SMBBLKDAT); | |
254 | } | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |
259 | char read_write, int hwpec) | |
1da177e4 LT |
260 | { |
261 | int i, len; | |
262 | int smbcmd; | |
263 | int temp; | |
264 | int result = 0; | |
265 | int timeout; | |
7edcb9ab | 266 | unsigned char errmask; |
1da177e4 | 267 | |
7edcb9ab | 268 | len = data->block[0]; |
1da177e4 LT |
269 | |
270 | if (read_write == I2C_SMBUS_WRITE) { | |
1da177e4 LT |
271 | outb_p(len, SMBHSTDAT0); |
272 | outb_p(data->block[1], SMBBLKDAT); | |
1da177e4 LT |
273 | } |
274 | ||
275 | for (i = 1; i <= len; i++) { | |
276 | if (i == len && read_write == I2C_SMBUS_READ) | |
277 | smbcmd = I801_BLOCK_LAST; | |
278 | else | |
279 | smbcmd = I801_BLOCK_DATA; | |
280 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT); | |
281 | ||
282 | dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, " | |
283 | "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i, | |
284 | inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD), | |
285 | inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT)); | |
286 | ||
287 | /* Make sure the SMBus host is ready to start transmitting */ | |
288 | temp = inb_p(SMBHSTSTS); | |
289 | if (i == 1) { | |
002cf631 | 290 | /* Erroneous conditions before transaction: |
1da177e4 | 291 | * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */ |
ca8b9e32 | 292 | errmask = 0x9f; |
1da177e4 | 293 | } else { |
002cf631 | 294 | /* Erroneous conditions during transaction: |
1da177e4 | 295 | * Failed, Bus_Err, Dev_Err, Intr */ |
ca8b9e32 | 296 | errmask = 0x1e; |
1da177e4 LT |
297 | } |
298 | if (temp & errmask) { | |
299 | dev_dbg(&I801_dev->dev, "SMBus busy (%02x). " | |
541e6a02 | 300 | "Resetting...\n", temp); |
1da177e4 LT |
301 | outb_p(temp, SMBHSTSTS); |
302 | if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) { | |
303 | dev_err(&I801_dev->dev, | |
304 | "Reset failed! (%02x)\n", temp); | |
7edcb9ab | 305 | return -1; |
1da177e4 | 306 | } |
7edcb9ab | 307 | if (i != 1) |
1da177e4 | 308 | /* if die in middle of block transaction, fail */ |
7edcb9ab | 309 | return -1; |
1da177e4 LT |
310 | } |
311 | ||
312 | if (i == 1) | |
313 | outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); | |
314 | ||
315 | /* We will always wait for a fraction of a second! */ | |
316 | timeout = 0; | |
317 | do { | |
1da177e4 | 318 | msleep(1); |
397e2f66 | 319 | temp = inb_p(SMBHSTSTS); |
1da177e4 | 320 | } |
ca8b9e32 OR |
321 | while ((!(temp & SMBHSTSTS_BYTE_DONE)) |
322 | && (timeout++ < MAX_TIMEOUT)); | |
1da177e4 LT |
323 | |
324 | /* If the SMBus is still busy, we give up */ | |
325 | if (timeout >= MAX_TIMEOUT) { | |
ca8b9e32 OR |
326 | /* try to stop the current command */ |
327 | dev_dbg(&I801_dev->dev, "Terminating the current " | |
328 | "operation\n"); | |
329 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | |
330 | msleep(1); | |
331 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), | |
332 | SMBHSTCNT); | |
1da177e4 LT |
333 | result = -1; |
334 | dev_dbg(&I801_dev->dev, "SMBus Timeout!\n"); | |
335 | } | |
336 | ||
ca8b9e32 | 337 | if (temp & SMBHSTSTS_FAILED) { |
1da177e4 LT |
338 | result = -1; |
339 | dev_dbg(&I801_dev->dev, | |
340 | "Error: Failed bus transaction\n"); | |
ca8b9e32 | 341 | } else if (temp & SMBHSTSTS_BUS_ERR) { |
1da177e4 LT |
342 | result = -1; |
343 | dev_err(&I801_dev->dev, "Bus collision!\n"); | |
ca8b9e32 | 344 | } else if (temp & SMBHSTSTS_DEV_ERR) { |
1da177e4 LT |
345 | result = -1; |
346 | dev_dbg(&I801_dev->dev, "Error: no response!\n"); | |
347 | } | |
348 | ||
349 | if (i == 1 && read_write == I2C_SMBUS_READ) { | |
350 | len = inb_p(SMBHSTDAT0); | |
7edcb9ab OR |
351 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
352 | return -1; | |
1da177e4 LT |
353 | data->block[0] = len; |
354 | } | |
355 | ||
356 | /* Retrieve/store value in SMBBLKDAT */ | |
357 | if (read_write == I2C_SMBUS_READ) | |
358 | data->block[i] = inb_p(SMBBLKDAT); | |
359 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) | |
360 | outb_p(data->block[i+1], SMBBLKDAT); | |
361 | if ((temp & 0x9e) != 0x00) | |
362 | outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */ | |
363 | ||
364 | if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) { | |
365 | dev_dbg(&I801_dev->dev, | |
366 | "Bad status (%02x) at end of transaction\n", | |
367 | temp); | |
368 | } | |
369 | dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, " | |
370 | "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i, | |
371 | inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD), | |
372 | inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT)); | |
373 | ||
374 | if (result < 0) | |
7edcb9ab | 375 | return result; |
1da177e4 | 376 | } |
7edcb9ab OR |
377 | return result; |
378 | } | |
1da177e4 | 379 | |
7edcb9ab OR |
380 | static int i801_set_block_buffer_mode(void) |
381 | { | |
382 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL); | |
383 | if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0) | |
384 | return -1; | |
385 | return 0; | |
386 | } | |
387 | ||
388 | /* Block transaction function */ | |
389 | static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | |
390 | int command, int hwpec) | |
391 | { | |
392 | int result = 0; | |
393 | unsigned char hostc; | |
394 | ||
395 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
396 | if (read_write == I2C_SMBUS_WRITE) { | |
397 | /* set I2C_EN bit in configuration register */ | |
398 | pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc); | |
399 | pci_write_config_byte(I801_dev, SMBHSTCFG, | |
400 | hostc | SMBHSTCFG_I2C_EN); | |
401 | } else { | |
402 | dev_err(&I801_dev->dev, | |
403 | "I2C_SMBUS_I2C_BLOCK_READ not DB!\n"); | |
404 | return -1; | |
405 | } | |
406 | } | |
407 | ||
408 | if (read_write == I2C_SMBUS_WRITE) { | |
409 | if (data->block[0] < 1) | |
410 | data->block[0] = 1; | |
411 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
412 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
413 | } else { | |
414 | data->block[0] = 32; /* max for reads */ | |
415 | } | |
416 | ||
369f6f4a JD |
417 | if ((i801_features & FEATURE_BLOCK_BUFFER) |
418 | && i801_set_block_buffer_mode() == 0) | |
7edcb9ab OR |
419 | result = i801_block_transaction_by_block(data, read_write, |
420 | hwpec); | |
421 | else | |
422 | result = i801_block_transaction_byte_by_byte(data, read_write, | |
423 | hwpec); | |
424 | ||
425 | if (result == 0 && hwpec) | |
ca8b9e32 | 426 | i801_wait_hwpec(); |
1da177e4 | 427 | |
1da177e4 LT |
428 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { |
429 | /* restore saved configuration register value */ | |
430 | pci_write_config_byte(I801_dev, SMBHSTCFG, hostc); | |
431 | } | |
432 | return result; | |
433 | } | |
434 | ||
435 | /* Return -1 on error. */ | |
436 | static s32 i801_access(struct i2c_adapter * adap, u16 addr, | |
437 | unsigned short flags, char read_write, u8 command, | |
438 | int size, union i2c_smbus_data * data) | |
439 | { | |
e8aac4a9 | 440 | int hwpec; |
1da177e4 LT |
441 | int block = 0; |
442 | int ret, xact = 0; | |
443 | ||
369f6f4a | 444 | hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
445 | && size != I2C_SMBUS_QUICK |
446 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
447 | |
448 | switch (size) { | |
449 | case I2C_SMBUS_QUICK: | |
450 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
451 | SMBHSTADD); | |
452 | xact = I801_QUICK; | |
453 | break; | |
454 | case I2C_SMBUS_BYTE: | |
455 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
456 | SMBHSTADD); | |
457 | if (read_write == I2C_SMBUS_WRITE) | |
458 | outb_p(command, SMBHSTCMD); | |
459 | xact = I801_BYTE; | |
460 | break; | |
461 | case I2C_SMBUS_BYTE_DATA: | |
462 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
463 | SMBHSTADD); | |
464 | outb_p(command, SMBHSTCMD); | |
465 | if (read_write == I2C_SMBUS_WRITE) | |
466 | outb_p(data->byte, SMBHSTDAT0); | |
467 | xact = I801_BYTE_DATA; | |
468 | break; | |
469 | case I2C_SMBUS_WORD_DATA: | |
470 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
471 | SMBHSTADD); | |
472 | outb_p(command, SMBHSTCMD); | |
473 | if (read_write == I2C_SMBUS_WRITE) { | |
474 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
475 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
476 | } | |
477 | xact = I801_WORD_DATA; | |
478 | break; | |
479 | case I2C_SMBUS_BLOCK_DATA: | |
480 | case I2C_SMBUS_I2C_BLOCK_DATA: | |
1da177e4 LT |
481 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
482 | SMBHSTADD); | |
483 | outb_p(command, SMBHSTCMD); | |
484 | block = 1; | |
485 | break; | |
486 | case I2C_SMBUS_PROC_CALL: | |
487 | default: | |
488 | dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size); | |
489 | return -1; | |
490 | } | |
491 | ||
ca8b9e32 OR |
492 | if (hwpec) /* enable/disable hardware PEC */ |
493 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL); | |
494 | else | |
495 | outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL); | |
e8aac4a9 | 496 | |
1da177e4 | 497 | if(block) |
585b3160 | 498 | ret = i801_block_transaction(data, read_write, size, hwpec); |
7edcb9ab OR |
499 | else |
500 | ret = i801_transaction(xact | ENABLE_INT9); | |
1da177e4 | 501 | |
c79cfbac | 502 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
503 | time, so we forcibly disable it after every transaction. Turn off |
504 | E32B for the same reason. */ | |
c79cfbac | 505 | if (hwpec) |
7edcb9ab OR |
506 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), |
507 | SMBAUXCTL); | |
c79cfbac | 508 | |
1da177e4 LT |
509 | if(block) |
510 | return ret; | |
511 | if(ret) | |
512 | return -1; | |
513 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) | |
514 | return 0; | |
515 | ||
516 | switch (xact & 0x7f) { | |
517 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
518 | case I801_BYTE_DATA: | |
519 | data->byte = inb_p(SMBHSTDAT0); | |
520 | break; | |
521 | case I801_WORD_DATA: | |
522 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
523 | break; | |
524 | } | |
525 | return 0; | |
526 | } | |
527 | ||
528 | ||
529 | static u32 i801_func(struct i2c_adapter *adapter) | |
530 | { | |
531 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
369f6f4a JD |
532 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
533 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
534 | ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0); | |
1da177e4 LT |
535 | } |
536 | ||
8f9082c5 | 537 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
538 | .smbus_xfer = i801_access, |
539 | .functionality = i801_func, | |
540 | }; | |
541 | ||
542 | static struct i2c_adapter i801_adapter = { | |
543 | .owner = THIS_MODULE, | |
9ace555d | 544 | .id = I2C_HW_SMBUS_I801, |
1da177e4 LT |
545 | .class = I2C_CLASS_HWMON, |
546 | .algo = &smbus_algorithm, | |
1da177e4 LT |
547 | }; |
548 | ||
549 | static struct pci_device_id i801_ids[] = { | |
550 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, | |
551 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
552 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
553 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
554 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
555 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
556 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
557 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
558 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 559 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 560 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 561 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
e07bc679 | 562 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) }, |
1da177e4 LT |
563 | { 0, } |
564 | }; | |
565 | ||
566 | MODULE_DEVICE_TABLE (pci, i801_ids); | |
567 | ||
568 | static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
569 | { | |
02dd7ae2 | 570 | unsigned char temp; |
455f3323 | 571 | int err; |
1da177e4 | 572 | |
02dd7ae2 | 573 | I801_dev = dev; |
369f6f4a | 574 | i801_features = 0; |
250d1bd3 JD |
575 | switch (dev->device) { |
576 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
577 | case PCI_DEVICE_ID_INTEL_82801EB_3: | |
578 | case PCI_DEVICE_ID_INTEL_ESB_4: | |
579 | case PCI_DEVICE_ID_INTEL_ICH6_16: | |
580 | case PCI_DEVICE_ID_INTEL_ICH7_17: | |
581 | case PCI_DEVICE_ID_INTEL_ESB2_17: | |
582 | case PCI_DEVICE_ID_INTEL_ICH8_5: | |
583 | case PCI_DEVICE_ID_INTEL_ICH9_6: | |
e07bc679 | 584 | case PCI_DEVICE_ID_INTEL_TOLAPAI_1: |
369f6f4a JD |
585 | i801_features |= FEATURE_SMBUS_PEC; |
586 | i801_features |= FEATURE_BLOCK_BUFFER; | |
250d1bd3 | 587 | break; |
250d1bd3 | 588 | } |
02dd7ae2 JD |
589 | |
590 | err = pci_enable_device(dev); | |
591 | if (err) { | |
592 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
593 | err); | |
594 | goto exit; | |
595 | } | |
596 | ||
597 | /* Determine the address of the SMBus area */ | |
598 | i801_smba = pci_resource_start(dev, SMBBAR); | |
599 | if (!i801_smba) { | |
600 | dev_err(&dev->dev, "SMBus base address uninitialized, " | |
601 | "upgrade BIOS\n"); | |
602 | err = -ENODEV; | |
d6fcb3b9 | 603 | goto exit; |
02dd7ae2 JD |
604 | } |
605 | ||
606 | err = pci_request_region(dev, SMBBAR, i801_driver.name); | |
607 | if (err) { | |
608 | dev_err(&dev->dev, "Failed to request SMBus region " | |
598736c5 AM |
609 | "0x%lx-0x%Lx\n", i801_smba, |
610 | (unsigned long long)pci_resource_end(dev, SMBBAR)); | |
d6fcb3b9 | 611 | goto exit; |
02dd7ae2 JD |
612 | } |
613 | ||
614 | pci_read_config_byte(I801_dev, SMBHSTCFG, &temp); | |
a5aaea37 | 615 | i801_original_hstcfg = temp; |
02dd7ae2 JD |
616 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
617 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
618 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
619 | temp |= SMBHSTCFG_HST_EN; | |
620 | } | |
621 | pci_write_config_byte(I801_dev, SMBHSTCFG, temp); | |
622 | ||
623 | if (temp & SMBHSTCFG_SMB_SMI_EN) | |
624 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | |
625 | else | |
626 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | |
1da177e4 | 627 | |
405ae7d3 | 628 | /* set up the sysfs linkage to our parent device */ |
1da177e4 LT |
629 | i801_adapter.dev.parent = &dev->dev; |
630 | ||
2096b956 | 631 | snprintf(i801_adapter.name, sizeof(i801_adapter.name), |
6dcc19df | 632 | "SMBus I801 adapter at %04lx", i801_smba); |
02dd7ae2 JD |
633 | err = i2c_add_adapter(&i801_adapter); |
634 | if (err) { | |
635 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
d6fcb3b9 | 636 | goto exit_release; |
02dd7ae2 | 637 | } |
d6fcb3b9 | 638 | return 0; |
02dd7ae2 | 639 | |
d6fcb3b9 DR |
640 | exit_release: |
641 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 JD |
642 | exit: |
643 | return err; | |
1da177e4 LT |
644 | } |
645 | ||
646 | static void __devexit i801_remove(struct pci_dev *dev) | |
647 | { | |
648 | i2c_del_adapter(&i801_adapter); | |
a5aaea37 | 649 | pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg); |
6dcc19df | 650 | pci_release_region(dev, SMBBAR); |
d6fcb3b9 DR |
651 | /* |
652 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
653 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
654 | */ | |
1da177e4 LT |
655 | } |
656 | ||
a5aaea37 JD |
657 | #ifdef CONFIG_PM |
658 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
659 | { | |
660 | pci_save_state(dev); | |
661 | pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg); | |
662 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static int i801_resume(struct pci_dev *dev) | |
667 | { | |
668 | pci_set_power_state(dev, PCI_D0); | |
669 | pci_restore_state(dev); | |
670 | return pci_enable_device(dev); | |
671 | } | |
672 | #else | |
673 | #define i801_suspend NULL | |
674 | #define i801_resume NULL | |
675 | #endif | |
676 | ||
1da177e4 LT |
677 | static struct pci_driver i801_driver = { |
678 | .name = "i801_smbus", | |
679 | .id_table = i801_ids, | |
680 | .probe = i801_probe, | |
681 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
682 | .suspend = i801_suspend, |
683 | .resume = i801_resume, | |
1da177e4 LT |
684 | }; |
685 | ||
686 | static int __init i2c_i801_init(void) | |
687 | { | |
688 | return pci_register_driver(&i801_driver); | |
689 | } | |
690 | ||
691 | static void __exit i2c_i801_exit(void) | |
692 | { | |
693 | pci_unregister_driver(&i801_driver); | |
694 | } | |
695 | ||
696 | MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, " | |
697 | "Philip Edelbrock <phil@netroedge.com>, " | |
698 | "and Mark D. Studebaker <mdsxyz123@yahoo.com>"); | |
699 | MODULE_DESCRIPTION("I801 SMBus driver"); | |
700 | MODULE_LICENSE("GPL"); | |
701 | ||
702 | module_init(i2c_i801_init); | |
703 | module_exit(i2c_i801_exit); |