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27bce457 JH |
1 | /* |
2 | * I2C adapter for the IMG Serial Control Bus (SCB) IP block. | |
3 | * | |
4 | * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * There are three ways that this I2C controller can be driven: | |
11 | * | |
12 | * - Raw control of the SDA and SCK signals. | |
13 | * | |
14 | * This corresponds to MODE_RAW, which takes control of the signals | |
15 | * directly for a certain number of clock cycles (the INT_TIMING | |
16 | * interrupt can be used for timing). | |
17 | * | |
18 | * - Atomic commands. A low level I2C symbol (such as generate | |
19 | * start/stop/ack/nack bit, generate byte, receive byte, and receive | |
20 | * ACK) is given to the hardware, with detection of completion by bits | |
21 | * in the LINESTAT register. | |
22 | * | |
23 | * This mode of operation is used by MODE_ATOMIC, which uses an I2C | |
24 | * state machine in the interrupt handler to compose/react to I2C | |
25 | * transactions using atomic mode commands, and also by MODE_SEQUENCE, | |
26 | * which emits a simple fixed sequence of atomic mode commands. | |
27 | * | |
28 | * Due to software control, the use of atomic commands usually results | |
29 | * in suboptimal use of the bus, with gaps between the I2C symbols while | |
30 | * the driver decides what to do next. | |
31 | * | |
32 | * - Automatic mode. A bus address, and whether to read/write is | |
33 | * specified, and the hardware takes care of the I2C state machine, | |
34 | * using a FIFO to send/receive bytes of data to an I2C slave. The | |
35 | * driver just has to keep the FIFO drained or filled in response to the | |
36 | * appropriate FIFO interrupts. | |
37 | * | |
38 | * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals | |
39 | * with control of repeated start bits between I2C messages. | |
40 | * | |
41 | * Use of automatic mode and the FIFO can make much more efficient use | |
42 | * of the bus compared to individual atomic commands, with potentially | |
43 | * no wasted time between I2C symbols or I2C messages. | |
44 | * | |
45 | * In most cases MODE_AUTOMATIC is used, however if any of the messages in | |
46 | * a transaction are zero byte writes (e.g. used by i2cdetect for probing | |
47 | * the bus), MODE_ATOMIC must be used since automatic mode is normally | |
48 | * started by the writing of data into the FIFO. | |
49 | * | |
50 | * The other modes are used in specific circumstances where MODE_ATOMIC and | |
51 | * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus | |
52 | * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure | |
53 | * it is in a sane state. | |
54 | * | |
55 | * Notice that the driver implements a timer-based timeout mechanism. | |
56 | * The reason for this mechanism is to reduce the number of interrupts | |
57 | * received in automatic mode. | |
58 | * | |
59 | * The driver would get a slave event and transaction done interrupts for | |
60 | * each atomic mode command that gets completed. However, these events are | |
61 | * not needed in automatic mode, becase those atomic mode commands are | |
62 | * managed automatically by the hardware. | |
63 | * | |
64 | * In practice, normal I2C transactions will be complete well before you | |
65 | * get the timer interrupt, as the timer is re-scheduled during FIFO | |
66 | * maintenance and disabled after the transaction is complete. | |
67 | * | |
68 | * In this way normal automatic mode operation isn't impacted by | |
69 | * unnecessary interrupts, but the exceptional abort condition can still be | |
70 | * detected (with a slight delay). | |
71 | */ | |
72 | ||
73 | #include <linux/bitops.h> | |
74 | #include <linux/clk.h> | |
75 | #include <linux/completion.h> | |
76 | #include <linux/err.h> | |
77 | #include <linux/i2c.h> | |
78 | #include <linux/init.h> | |
79 | #include <linux/interrupt.h> | |
80 | #include <linux/io.h> | |
81 | #include <linux/kernel.h> | |
82 | #include <linux/module.h> | |
83 | #include <linux/of_platform.h> | |
84 | #include <linux/platform_device.h> | |
85 | #include <linux/slab.h> | |
86 | #include <linux/timer.h> | |
87 | ||
88 | /* Register offsets */ | |
89 | ||
90 | #define SCB_STATUS_REG 0x00 | |
91 | #define SCB_OVERRIDE_REG 0x04 | |
92 | #define SCB_READ_ADDR_REG 0x08 | |
93 | #define SCB_READ_COUNT_REG 0x0c | |
94 | #define SCB_WRITE_ADDR_REG 0x10 | |
95 | #define SCB_READ_DATA_REG 0x14 | |
96 | #define SCB_WRITE_DATA_REG 0x18 | |
97 | #define SCB_FIFO_STATUS_REG 0x1c | |
98 | #define SCB_CONTROL_SOFT_RESET 0x1f | |
99 | #define SCB_CLK_SET_REG 0x3c | |
100 | #define SCB_INT_STATUS_REG 0x40 | |
101 | #define SCB_INT_CLEAR_REG 0x44 | |
102 | #define SCB_INT_MASK_REG 0x48 | |
103 | #define SCB_CONTROL_REG 0x4c | |
104 | #define SCB_TIME_TPL_REG 0x50 | |
105 | #define SCB_TIME_TPH_REG 0x54 | |
106 | #define SCB_TIME_TP2S_REG 0x58 | |
107 | #define SCB_TIME_TBI_REG 0x60 | |
108 | #define SCB_TIME_TSL_REG 0x64 | |
109 | #define SCB_TIME_TDL_REG 0x68 | |
110 | #define SCB_TIME_TSDL_REG 0x6c | |
111 | #define SCB_TIME_TSDH_REG 0x70 | |
112 | #define SCB_READ_XADDR_REG 0x74 | |
113 | #define SCB_WRITE_XADDR_REG 0x78 | |
114 | #define SCB_WRITE_COUNT_REG 0x7c | |
115 | #define SCB_CORE_REV_REG 0x80 | |
116 | #define SCB_TIME_TCKH_REG 0x84 | |
117 | #define SCB_TIME_TCKL_REG 0x88 | |
118 | #define SCB_FIFO_FLUSH_REG 0x8c | |
119 | #define SCB_READ_FIFO_REG 0x94 | |
120 | #define SCB_CLEAR_REG 0x98 | |
121 | ||
122 | /* SCB_CONTROL_REG bits */ | |
123 | ||
124 | #define SCB_CONTROL_CLK_ENABLE 0x1e0 | |
125 | #define SCB_CONTROL_TRANSACTION_HALT 0x200 | |
126 | ||
127 | #define FIFO_READ_FULL BIT(0) | |
128 | #define FIFO_READ_EMPTY BIT(1) | |
129 | #define FIFO_WRITE_FULL BIT(2) | |
130 | #define FIFO_WRITE_EMPTY BIT(3) | |
131 | ||
132 | /* SCB_CLK_SET_REG bits */ | |
133 | #define SCB_FILT_DISABLE BIT(31) | |
134 | #define SCB_FILT_BYPASS BIT(30) | |
135 | #define SCB_FILT_INC_MASK 0x7f | |
136 | #define SCB_FILT_INC_SHIFT 16 | |
137 | #define SCB_INC_MASK 0x7f | |
138 | #define SCB_INC_SHIFT 8 | |
139 | ||
140 | /* SCB_INT_*_REG bits */ | |
141 | ||
142 | #define INT_BUS_INACTIVE BIT(0) | |
143 | #define INT_UNEXPECTED_START BIT(1) | |
144 | #define INT_SCLK_LOW_TIMEOUT BIT(2) | |
145 | #define INT_SDAT_LOW_TIMEOUT BIT(3) | |
146 | #define INT_WRITE_ACK_ERR BIT(4) | |
147 | #define INT_ADDR_ACK_ERR BIT(5) | |
148 | #define INT_FIFO_FULL BIT(9) | |
149 | #define INT_FIFO_FILLING BIT(10) | |
150 | #define INT_FIFO_EMPTY BIT(11) | |
151 | #define INT_FIFO_EMPTYING BIT(12) | |
152 | #define INT_TRANSACTION_DONE BIT(15) | |
153 | #define INT_SLAVE_EVENT BIT(16) | |
c7b0a7c1 | 154 | #define INT_MASTER_HALTED BIT(17) |
27bce457 | 155 | #define INT_TIMING BIT(18) |
dd29207e | 156 | #define INT_STOP_DETECTED BIT(19) |
27bce457 JH |
157 | |
158 | #define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) | |
27bce457 JH |
159 | |
160 | /* Level interrupts need clearing after handling instead of before */ | |
161 | #define INT_LEVEL 0x01e00 | |
162 | ||
163 | /* Don't allow any interrupts while the clock may be off */ | |
164 | #define INT_ENABLE_MASK_INACTIVE 0x00000 | |
165 | ||
166 | /* Interrupt masks for the different driver modes */ | |
167 | ||
168 | #define INT_ENABLE_MASK_RAW INT_TIMING | |
169 | ||
170 | #define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \ | |
171 | INT_SLAVE_EVENT | \ | |
172 | INT_ADDR_ACK_ERR | \ | |
173 | INT_WRITE_ACK_ERR) | |
174 | ||
175 | #define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \ | |
176 | INT_ADDR_ACK_ERR | \ | |
177 | INT_WRITE_ACK_ERR | \ | |
178 | INT_FIFO_FULL | \ | |
179 | INT_FIFO_FILLING | \ | |
dd29207e | 180 | INT_FIFO_EMPTY | \ |
c7b0a7c1 | 181 | INT_MASTER_HALTED | \ |
dd29207e | 182 | INT_STOP_DETECTED) |
27bce457 JH |
183 | |
184 | #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ | |
185 | INT_ADDR_ACK_ERR | \ | |
186 | INT_WRITE_ACK_ERR) | |
187 | ||
188 | /* SCB_STATUS_REG fields */ | |
189 | ||
190 | #define LINESTAT_SCLK_LINE_STATUS BIT(0) | |
191 | #define LINESTAT_SCLK_EN BIT(1) | |
192 | #define LINESTAT_SDAT_LINE_STATUS BIT(2) | |
193 | #define LINESTAT_SDAT_EN BIT(3) | |
194 | #define LINESTAT_DET_START_STATUS BIT(4) | |
195 | #define LINESTAT_DET_STOP_STATUS BIT(5) | |
196 | #define LINESTAT_DET_ACK_STATUS BIT(6) | |
197 | #define LINESTAT_DET_NACK_STATUS BIT(7) | |
198 | #define LINESTAT_BUS_IDLE BIT(8) | |
199 | #define LINESTAT_T_DONE_STATUS BIT(9) | |
200 | #define LINESTAT_SCLK_OUT_STATUS BIT(10) | |
201 | #define LINESTAT_SDAT_OUT_STATUS BIT(11) | |
202 | #define LINESTAT_GEN_LINE_MASK_STATUS BIT(12) | |
203 | #define LINESTAT_START_BIT_DET BIT(13) | |
204 | #define LINESTAT_STOP_BIT_DET BIT(14) | |
205 | #define LINESTAT_ACK_DET BIT(15) | |
206 | #define LINESTAT_NACK_DET BIT(16) | |
207 | #define LINESTAT_INPUT_HELD_V BIT(17) | |
208 | #define LINESTAT_ABORT_DET BIT(18) | |
209 | #define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET) | |
210 | #define LINESTAT_INPUT_DATA 0xff000000 | |
211 | #define LINESTAT_INPUT_DATA_SHIFT 24 | |
212 | ||
213 | #define LINESTAT_CLEAR_SHIFT 13 | |
214 | #define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT) | |
215 | ||
216 | /* SCB_OVERRIDE_REG fields */ | |
217 | ||
218 | #define OVERRIDE_SCLK_OVR BIT(0) | |
219 | #define OVERRIDE_SCLKEN_OVR BIT(1) | |
220 | #define OVERRIDE_SDAT_OVR BIT(2) | |
221 | #define OVERRIDE_SDATEN_OVR BIT(3) | |
222 | #define OVERRIDE_MASTER BIT(9) | |
223 | #define OVERRIDE_LINE_OVR_EN BIT(10) | |
224 | #define OVERRIDE_DIRECT BIT(11) | |
225 | #define OVERRIDE_CMD_SHIFT 4 | |
226 | #define OVERRIDE_CMD_MASK 0x1f | |
227 | #define OVERRIDE_DATA_SHIFT 24 | |
228 | ||
229 | #define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \ | |
230 | OVERRIDE_SCLKEN_OVR) | |
231 | #define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \ | |
232 | OVERRIDE_SCLKEN_OVR | \ | |
233 | OVERRIDE_SCLK_OVR) | |
234 | #define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \ | |
235 | OVERRIDE_SDATEN_OVR) | |
236 | #define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \ | |
237 | OVERRIDE_SDATEN_OVR | \ | |
238 | OVERRIDE_SDAT_OVR) | |
239 | ||
240 | /* OVERRIDE_CMD values */ | |
241 | ||
242 | #define CMD_PAUSE 0x00 | |
243 | #define CMD_GEN_DATA 0x01 | |
244 | #define CMD_GEN_START 0x02 | |
245 | #define CMD_GEN_STOP 0x03 | |
246 | #define CMD_GEN_ACK 0x04 | |
247 | #define CMD_GEN_NACK 0x05 | |
248 | #define CMD_RET_DATA 0x08 | |
249 | #define CMD_RET_ACK 0x09 | |
250 | ||
251 | /* Fixed timing values */ | |
252 | ||
253 | #define TIMEOUT_TBI 0x0 | |
254 | #define TIMEOUT_TSL 0xffff | |
255 | #define TIMEOUT_TDL 0x0 | |
256 | ||
257 | /* Transaction timeout */ | |
258 | ||
259 | #define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
260 | ||
261 | /* | |
262 | * Worst incs are 1 (innacurate) and 16*256 (irregular). | |
263 | * So a sensible inc is the logarithmic mean: 64 (2^6), which is | |
264 | * in the middle of the valid range (0-127). | |
265 | */ | |
266 | #define SCB_OPT_INC 64 | |
267 | ||
268 | /* Setup the clock enable filtering for 25 ns */ | |
269 | #define SCB_FILT_GLITCH 25 | |
270 | ||
271 | /* | |
272 | * Bits to return from interrupt handler functions for different modes. | |
273 | * This delays completion until we've finished with the registers, so that the | |
274 | * function waiting for completion can safely disable the clock to save power. | |
275 | */ | |
276 | #define ISR_COMPLETE_M BIT(31) | |
277 | #define ISR_FATAL_M BIT(30) | |
278 | #define ISR_WAITSTOP BIT(29) | |
279 | #define ISR_STATUS_M 0x0000ffff /* contains +ve errno */ | |
280 | #define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err))) | |
281 | #define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M) | |
282 | ||
27bce457 JH |
283 | enum img_i2c_mode { |
284 | MODE_INACTIVE, | |
285 | MODE_RAW, | |
286 | MODE_ATOMIC, | |
287 | MODE_AUTOMATIC, | |
288 | MODE_SEQUENCE, | |
289 | MODE_FATAL, | |
290 | MODE_WAITSTOP, | |
291 | MODE_SUSPEND, | |
292 | }; | |
293 | ||
294 | /* Timing parameters for i2c modes (in ns) */ | |
295 | struct img_i2c_timings { | |
296 | const char *name; | |
297 | unsigned int max_bitrate; | |
298 | unsigned int tckh, tckl, tsdh, tsdl; | |
299 | unsigned int tp2s, tpl, tph; | |
300 | }; | |
301 | ||
302 | /* The timings array must be ordered from slower to faster */ | |
303 | static struct img_i2c_timings timings[] = { | |
304 | /* Standard mode */ | |
305 | { | |
306 | .name = "standard", | |
307 | .max_bitrate = 100000, | |
308 | .tckh = 4000, | |
309 | .tckl = 4700, | |
310 | .tsdh = 4700, | |
311 | .tsdl = 8700, | |
312 | .tp2s = 4700, | |
313 | .tpl = 4700, | |
314 | .tph = 4000, | |
315 | }, | |
316 | /* Fast mode */ | |
317 | { | |
318 | .name = "fast", | |
319 | .max_bitrate = 400000, | |
320 | .tckh = 600, | |
321 | .tckl = 1300, | |
322 | .tsdh = 600, | |
323 | .tsdl = 1200, | |
324 | .tp2s = 1300, | |
325 | .tpl = 600, | |
326 | .tph = 600, | |
327 | }, | |
328 | }; | |
329 | ||
330 | /* Reset dance */ | |
331 | static u8 img_i2c_reset_seq[] = { CMD_GEN_START, | |
332 | CMD_GEN_DATA, 0xff, | |
333 | CMD_RET_ACK, | |
334 | CMD_GEN_START, | |
335 | CMD_GEN_STOP, | |
336 | 0 }; | |
337 | /* Just issue a stop (after an abort condition) */ | |
338 | static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP, | |
339 | 0 }; | |
340 | ||
341 | /* We're interested in different interrupts depending on the mode */ | |
342 | static unsigned int img_i2c_int_enable_by_mode[] = { | |
343 | [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE, | |
344 | [MODE_RAW] = INT_ENABLE_MASK_RAW, | |
345 | [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC, | |
346 | [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC, | |
347 | [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC, | |
348 | [MODE_FATAL] = 0, | |
349 | [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP, | |
350 | [MODE_SUSPEND] = 0, | |
351 | }; | |
352 | ||
353 | /* Atomic command names */ | |
354 | static const char * const img_i2c_atomic_cmd_names[] = { | |
355 | [CMD_PAUSE] = "PAUSE", | |
356 | [CMD_GEN_DATA] = "GEN_DATA", | |
357 | [CMD_GEN_START] = "GEN_START", | |
358 | [CMD_GEN_STOP] = "GEN_STOP", | |
359 | [CMD_GEN_ACK] = "GEN_ACK", | |
360 | [CMD_GEN_NACK] = "GEN_NACK", | |
361 | [CMD_RET_DATA] = "RET_DATA", | |
362 | [CMD_RET_ACK] = "RET_ACK", | |
363 | }; | |
364 | ||
365 | struct img_i2c { | |
366 | struct i2c_adapter adap; | |
367 | ||
368 | void __iomem *base; | |
369 | ||
370 | /* | |
371 | * The scb core clock is used to get the input frequency, and to disable | |
372 | * it after every set of transactions to save some power. | |
373 | */ | |
374 | struct clk *scb_clk, *sys_clk; | |
375 | unsigned int bitrate; | |
376 | bool need_wr_rd_fence; | |
377 | ||
378 | /* state */ | |
379 | struct completion msg_complete; | |
380 | spinlock_t lock; /* lock before doing anything with the state */ | |
381 | struct i2c_msg msg; | |
382 | ||
383 | /* After the last transaction, wait for a stop bit */ | |
384 | bool last_msg; | |
385 | int msg_status; | |
386 | ||
387 | enum img_i2c_mode mode; | |
388 | u32 int_enable; /* depends on mode */ | |
389 | u32 line_status; /* line status over command */ | |
390 | ||
391 | /* | |
392 | * To avoid slave event interrupts in automatic mode, use a timer to | |
393 | * poll the abort condition if we don't get an interrupt for too long. | |
394 | */ | |
395 | struct timer_list check_timer; | |
396 | bool t_halt; | |
397 | ||
398 | /* atomic mode state */ | |
399 | bool at_t_done; | |
400 | bool at_slave_event; | |
401 | int at_cur_cmd; | |
402 | u8 at_cur_data; | |
403 | ||
404 | /* Sequence: either reset or stop. See img_i2c_sequence. */ | |
405 | u8 *seq; | |
406 | ||
407 | /* raw mode */ | |
408 | unsigned int raw_timeout; | |
409 | }; | |
410 | ||
411 | static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value) | |
412 | { | |
413 | writel(value, i2c->base + offset); | |
414 | } | |
415 | ||
416 | static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset) | |
417 | { | |
418 | return readl(i2c->base + offset); | |
419 | } | |
420 | ||
421 | /* | |
422 | * The code to read from the master read fifo, and write to the master | |
423 | * write fifo, checks a bit in an SCB register before every byte to | |
424 | * ensure that the fifo is not full (write fifo) or empty (read fifo). | |
425 | * Due to clock domain crossing inside the SCB block the updated value | |
426 | * of this bit is only visible after 2 cycles. | |
427 | * | |
428 | * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only | |
429 | * revision register), and it's called after reading from or writing to the | |
430 | * fifos to ensure that subsequent reads of the fifo status bits do not read | |
431 | * stale values. | |
432 | */ | |
433 | static void img_i2c_wr_rd_fence(struct img_i2c *i2c) | |
434 | { | |
435 | if (i2c->need_wr_rd_fence) { | |
436 | img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); | |
437 | img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); | |
438 | } | |
439 | } | |
440 | ||
441 | static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode) | |
442 | { | |
443 | i2c->mode = mode; | |
444 | i2c->int_enable = img_i2c_int_enable_by_mode[mode]; | |
445 | i2c->line_status = 0; | |
446 | } | |
447 | ||
448 | static void img_i2c_raw_op(struct img_i2c *i2c) | |
449 | { | |
450 | i2c->raw_timeout = 0; | |
451 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, | |
452 | OVERRIDE_SCLKEN_OVR | | |
453 | OVERRIDE_SDATEN_OVR | | |
454 | OVERRIDE_MASTER | | |
455 | OVERRIDE_LINE_OVR_EN | | |
456 | OVERRIDE_DIRECT | | |
457 | ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | | |
458 | (i2c->at_cur_data << OVERRIDE_DATA_SHIFT)); | |
459 | } | |
460 | ||
461 | static const char *img_i2c_atomic_op_name(unsigned int cmd) | |
462 | { | |
463 | if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names))) | |
464 | return "UNKNOWN"; | |
465 | return img_i2c_atomic_cmd_names[cmd]; | |
466 | } | |
467 | ||
468 | /* Send a single atomic mode command to the hardware */ | |
469 | static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data) | |
470 | { | |
471 | i2c->at_cur_cmd = cmd; | |
472 | i2c->at_cur_data = data; | |
473 | ||
474 | /* work around lack of data setup time when generating data */ | |
475 | if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) { | |
476 | u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); | |
477 | ||
478 | if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) { | |
479 | /* hold the data line down for a moment */ | |
480 | img_i2c_switch_mode(i2c, MODE_RAW); | |
481 | img_i2c_raw_op(i2c); | |
482 | return; | |
483 | } | |
484 | } | |
485 | ||
486 | dev_dbg(i2c->adap.dev.parent, | |
487 | "atomic cmd=%s (%d) data=%#x\n", | |
488 | img_i2c_atomic_op_name(cmd), cmd, data); | |
489 | i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK); | |
490 | i2c->at_slave_event = false; | |
491 | i2c->line_status = 0; | |
492 | ||
493 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, | |
494 | ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | | |
495 | OVERRIDE_MASTER | | |
496 | OVERRIDE_DIRECT | | |
497 | (data << OVERRIDE_DATA_SHIFT)); | |
498 | } | |
499 | ||
500 | /* Start a transaction in atomic mode */ | |
501 | static void img_i2c_atomic_start(struct img_i2c *i2c) | |
502 | { | |
503 | img_i2c_switch_mode(i2c, MODE_ATOMIC); | |
504 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
505 | img_i2c_atomic_op(i2c, CMD_GEN_START, 0x00); | |
506 | } | |
507 | ||
508 | static void img_i2c_soft_reset(struct img_i2c *i2c) | |
509 | { | |
510 | i2c->t_halt = false; | |
511 | img_i2c_writel(i2c, SCB_CONTROL_REG, 0); | |
512 | img_i2c_writel(i2c, SCB_CONTROL_REG, | |
513 | SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET); | |
514 | } | |
515 | ||
c20821a7 SN |
516 | /* |
517 | * Enable or release transaction halt for control of repeated starts. | |
518 | * In version 3.3 of the IP when transaction halt is set, an interrupt | |
519 | * will be generated after each byte of a transfer instead of after | |
520 | * every transfer but before the stop bit. | |
521 | * Due to this behaviour we have to be careful that every time we | |
522 | * release the transaction halt we have to re-enable it straight away | |
523 | * so that we only process a single byte, not doing so will result in | |
524 | * all remaining bytes been processed and a stop bit being issued, | |
525 | * which will prevent us having a repeated start. | |
526 | */ | |
27bce457 JH |
527 | static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt) |
528 | { | |
529 | u32 val; | |
530 | ||
531 | if (i2c->t_halt == t_halt) | |
532 | return; | |
533 | i2c->t_halt = t_halt; | |
534 | val = img_i2c_readl(i2c, SCB_CONTROL_REG); | |
535 | if (t_halt) | |
536 | val |= SCB_CONTROL_TRANSACTION_HALT; | |
537 | else | |
538 | val &= ~SCB_CONTROL_TRANSACTION_HALT; | |
539 | img_i2c_writel(i2c, SCB_CONTROL_REG, val); | |
540 | } | |
541 | ||
542 | /* Drain data from the FIFO into the buffer (automatic mode) */ | |
543 | static void img_i2c_read_fifo(struct img_i2c *i2c) | |
544 | { | |
545 | while (i2c->msg.len) { | |
546 | u32 fifo_status; | |
547 | u8 data; | |
548 | ||
2aefb1bd | 549 | img_i2c_wr_rd_fence(i2c); |
27bce457 JH |
550 | fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); |
551 | if (fifo_status & FIFO_READ_EMPTY) | |
552 | break; | |
553 | ||
554 | data = img_i2c_readl(i2c, SCB_READ_DATA_REG); | |
555 | *i2c->msg.buf = data; | |
556 | ||
557 | img_i2c_writel(i2c, SCB_READ_FIFO_REG, 0xff); | |
27bce457 JH |
558 | i2c->msg.len--; |
559 | i2c->msg.buf++; | |
560 | } | |
561 | } | |
562 | ||
563 | /* Fill the FIFO with data from the buffer (automatic mode) */ | |
564 | static void img_i2c_write_fifo(struct img_i2c *i2c) | |
565 | { | |
566 | while (i2c->msg.len) { | |
567 | u32 fifo_status; | |
568 | ||
2aefb1bd | 569 | img_i2c_wr_rd_fence(i2c); |
27bce457 JH |
570 | fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); |
571 | if (fifo_status & FIFO_WRITE_FULL) | |
572 | break; | |
573 | ||
574 | img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf); | |
27bce457 JH |
575 | i2c->msg.len--; |
576 | i2c->msg.buf++; | |
577 | } | |
578 | ||
579 | /* Disable fifo emptying interrupt if nothing more to write */ | |
580 | if (!i2c->msg.len) | |
581 | i2c->int_enable &= ~INT_FIFO_EMPTYING; | |
582 | } | |
583 | ||
584 | /* Start a read transaction in automatic mode */ | |
585 | static void img_i2c_read(struct img_i2c *i2c) | |
586 | { | |
587 | img_i2c_switch_mode(i2c, MODE_AUTOMATIC); | |
588 | if (!i2c->last_msg) | |
589 | i2c->int_enable |= INT_SLAVE_EVENT; | |
590 | ||
591 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
592 | img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr); | |
593 | img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len); | |
594 | ||
27bce457 JH |
595 | mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); |
596 | } | |
597 | ||
598 | /* Start a write transaction in automatic mode */ | |
599 | static void img_i2c_write(struct img_i2c *i2c) | |
600 | { | |
601 | img_i2c_switch_mode(i2c, MODE_AUTOMATIC); | |
602 | if (!i2c->last_msg) | |
603 | i2c->int_enable |= INT_SLAVE_EVENT; | |
604 | ||
605 | img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr); | |
606 | img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len); | |
607 | ||
27bce457 JH |
608 | mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); |
609 | img_i2c_write_fifo(i2c); | |
610 | ||
611 | /* img_i2c_write_fifo() may modify int_enable */ | |
612 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
613 | } | |
614 | ||
615 | /* | |
616 | * Indicate that the transaction is complete. This is called from the | |
617 | * ISR to wake up the waiting thread, after which the ISR must not | |
618 | * access any more SCB registers. | |
619 | */ | |
620 | static void img_i2c_complete_transaction(struct img_i2c *i2c, int status) | |
621 | { | |
622 | img_i2c_switch_mode(i2c, MODE_INACTIVE); | |
623 | if (status) { | |
624 | i2c->msg_status = status; | |
625 | img_i2c_transaction_halt(i2c, false); | |
626 | } | |
627 | complete(&i2c->msg_complete); | |
628 | } | |
629 | ||
630 | static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c, | |
631 | u32 int_status, u32 line_status) | |
632 | { | |
633 | /* Stay in raw mode for this, so we don't just loop infinitely */ | |
634 | img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data); | |
635 | img_i2c_switch_mode(i2c, MODE_ATOMIC); | |
636 | return 0; | |
637 | } | |
638 | ||
639 | static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status, | |
640 | u32 line_status) | |
641 | { | |
642 | if (int_status & INT_TIMING) { | |
643 | if (i2c->raw_timeout == 0) | |
644 | return img_i2c_raw_atomic_delay_handler(i2c, | |
645 | int_status, line_status); | |
646 | --i2c->raw_timeout; | |
647 | } | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status) | |
652 | { | |
653 | static const unsigned int continue_bits[] = { | |
654 | [CMD_GEN_START] = LINESTAT_START_BIT_DET, | |
655 | [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V, | |
656 | [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET, | |
657 | [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V, | |
658 | [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET, | |
659 | }; | |
660 | int next_cmd = -1; | |
661 | u8 next_data = 0x00; | |
662 | ||
663 | if (int_status & INT_SLAVE_EVENT) | |
664 | i2c->at_slave_event = true; | |
665 | if (int_status & INT_TRANSACTION_DONE) | |
666 | i2c->at_t_done = true; | |
667 | ||
668 | if (!i2c->at_slave_event || !i2c->at_t_done) | |
669 | return 0; | |
670 | ||
671 | /* wait if no continue bits are set */ | |
672 | if (i2c->at_cur_cmd >= 0 && | |
673 | i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) { | |
674 | unsigned int cont_bits = continue_bits[i2c->at_cur_cmd]; | |
675 | ||
676 | if (cont_bits) { | |
677 | cont_bits |= LINESTAT_ABORT_DET; | |
678 | if (!(i2c->line_status & cont_bits)) | |
679 | return 0; | |
680 | } | |
681 | } | |
682 | ||
683 | /* follow the sequence of commands in i2c->seq */ | |
684 | next_cmd = *i2c->seq; | |
685 | /* stop on a nil */ | |
686 | if (!next_cmd) { | |
687 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); | |
688 | return ISR_COMPLETE(0); | |
689 | } | |
690 | /* when generating data, the next byte is the data */ | |
691 | if (next_cmd == CMD_GEN_DATA) { | |
692 | ++i2c->seq; | |
693 | next_data = *i2c->seq; | |
694 | } | |
695 | ++i2c->seq; | |
696 | img_i2c_atomic_op(i2c, next_cmd, next_data); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | static void img_i2c_reset_start(struct img_i2c *i2c) | |
702 | { | |
703 | /* Initiate the magic dance */ | |
704 | img_i2c_switch_mode(i2c, MODE_SEQUENCE); | |
705 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
706 | i2c->seq = img_i2c_reset_seq; | |
707 | i2c->at_slave_event = true; | |
708 | i2c->at_t_done = true; | |
709 | i2c->at_cur_cmd = -1; | |
710 | ||
711 | /* img_i2c_reset_seq isn't empty so the following won't fail */ | |
712 | img_i2c_sequence(i2c, 0); | |
713 | } | |
714 | ||
715 | static void img_i2c_stop_start(struct img_i2c *i2c) | |
716 | { | |
717 | /* Initiate a stop bit sequence */ | |
718 | img_i2c_switch_mode(i2c, MODE_SEQUENCE); | |
719 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
720 | i2c->seq = img_i2c_stop_seq; | |
721 | i2c->at_slave_event = true; | |
722 | i2c->at_t_done = true; | |
723 | i2c->at_cur_cmd = -1; | |
724 | ||
725 | /* img_i2c_stop_seq isn't empty so the following won't fail */ | |
726 | img_i2c_sequence(i2c, 0); | |
727 | } | |
728 | ||
729 | static unsigned int img_i2c_atomic(struct img_i2c *i2c, | |
730 | u32 int_status, | |
731 | u32 line_status) | |
732 | { | |
733 | int next_cmd = -1; | |
734 | u8 next_data = 0x00; | |
735 | ||
736 | if (int_status & INT_SLAVE_EVENT) | |
737 | i2c->at_slave_event = true; | |
738 | if (int_status & INT_TRANSACTION_DONE) | |
739 | i2c->at_t_done = true; | |
740 | ||
741 | if (!i2c->at_slave_event || !i2c->at_t_done) | |
742 | goto next_atomic_cmd; | |
743 | if (i2c->line_status & LINESTAT_ABORT_DET) { | |
744 | dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); | |
745 | next_cmd = CMD_GEN_STOP; | |
746 | i2c->msg_status = -EIO; | |
747 | goto next_atomic_cmd; | |
748 | } | |
749 | ||
750 | /* i2c->at_cur_cmd may have completed */ | |
751 | switch (i2c->at_cur_cmd) { | |
752 | case CMD_GEN_START: | |
753 | next_cmd = CMD_GEN_DATA; | |
754 | next_data = (i2c->msg.addr << 1); | |
755 | if (i2c->msg.flags & I2C_M_RD) | |
756 | next_data |= 0x1; | |
757 | break; | |
758 | case CMD_GEN_DATA: | |
759 | if (i2c->line_status & LINESTAT_INPUT_HELD_V) | |
760 | next_cmd = CMD_RET_ACK; | |
761 | break; | |
762 | case CMD_RET_ACK: | |
c55ebe0e SN |
763 | if (i2c->line_status & LINESTAT_ACK_DET || |
764 | (i2c->line_status & LINESTAT_NACK_DET && | |
765 | i2c->msg.flags & I2C_M_IGNORE_NAK)) { | |
27bce457 JH |
766 | if (i2c->msg.len == 0) { |
767 | next_cmd = CMD_GEN_STOP; | |
768 | } else if (i2c->msg.flags & I2C_M_RD) { | |
769 | next_cmd = CMD_RET_DATA; | |
770 | } else { | |
771 | next_cmd = CMD_GEN_DATA; | |
772 | next_data = *i2c->msg.buf; | |
773 | --i2c->msg.len; | |
774 | ++i2c->msg.buf; | |
775 | } | |
776 | } else if (i2c->line_status & LINESTAT_NACK_DET) { | |
777 | i2c->msg_status = -EIO; | |
778 | next_cmd = CMD_GEN_STOP; | |
779 | } | |
780 | break; | |
781 | case CMD_RET_DATA: | |
782 | if (i2c->line_status & LINESTAT_INPUT_HELD_V) { | |
783 | *i2c->msg.buf = (i2c->line_status & | |
784 | LINESTAT_INPUT_DATA) | |
785 | >> LINESTAT_INPUT_DATA_SHIFT; | |
786 | --i2c->msg.len; | |
787 | ++i2c->msg.buf; | |
788 | if (i2c->msg.len) | |
789 | next_cmd = CMD_GEN_ACK; | |
790 | else | |
791 | next_cmd = CMD_GEN_NACK; | |
792 | } | |
793 | break; | |
794 | case CMD_GEN_ACK: | |
795 | if (i2c->line_status & LINESTAT_ACK_DET) { | |
796 | next_cmd = CMD_RET_DATA; | |
797 | } else { | |
798 | i2c->msg_status = -EIO; | |
799 | next_cmd = CMD_GEN_STOP; | |
800 | } | |
801 | break; | |
802 | case CMD_GEN_NACK: | |
803 | next_cmd = CMD_GEN_STOP; | |
804 | break; | |
805 | case CMD_GEN_STOP: | |
806 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); | |
807 | return ISR_COMPLETE(0); | |
808 | default: | |
809 | dev_err(i2c->adap.dev.parent, "bad atomic command %d\n", | |
810 | i2c->at_cur_cmd); | |
811 | i2c->msg_status = -EIO; | |
812 | next_cmd = CMD_GEN_STOP; | |
813 | break; | |
814 | } | |
815 | ||
816 | next_atomic_cmd: | |
817 | if (next_cmd != -1) { | |
818 | /* don't actually stop unless we're the last transaction */ | |
819 | if (next_cmd == CMD_GEN_STOP && !i2c->msg_status && | |
820 | !i2c->last_msg) | |
821 | return ISR_COMPLETE(0); | |
822 | img_i2c_atomic_op(i2c, next_cmd, next_data); | |
823 | } | |
824 | return 0; | |
825 | } | |
826 | ||
827 | /* | |
828 | * Timer function to check if something has gone wrong in automatic mode (so we | |
829 | * don't have to handle so many interrupts just to catch an exception). | |
830 | */ | |
831 | static void img_i2c_check_timer(unsigned long arg) | |
832 | { | |
833 | struct img_i2c *i2c = (struct img_i2c *)arg; | |
834 | unsigned long flags; | |
835 | unsigned int line_status; | |
836 | ||
837 | spin_lock_irqsave(&i2c->lock, flags); | |
838 | line_status = img_i2c_readl(i2c, SCB_STATUS_REG); | |
839 | ||
840 | /* check for an abort condition */ | |
841 | if (line_status & LINESTAT_ABORT_DET) { | |
842 | dev_dbg(i2c->adap.dev.parent, | |
843 | "abort condition detected by check timer\n"); | |
844 | /* enable slave event interrupt mask to trigger irq */ | |
845 | img_i2c_writel(i2c, SCB_INT_MASK_REG, | |
846 | i2c->int_enable | INT_SLAVE_EVENT); | |
847 | } | |
848 | ||
849 | spin_unlock_irqrestore(&i2c->lock, flags); | |
850 | } | |
851 | ||
852 | static unsigned int img_i2c_auto(struct img_i2c *i2c, | |
853 | unsigned int int_status, | |
854 | unsigned int line_status) | |
855 | { | |
856 | if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR)) | |
857 | return ISR_COMPLETE(EIO); | |
858 | ||
859 | if (line_status & LINESTAT_ABORT_DET) { | |
860 | dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); | |
861 | /* empty the read fifo */ | |
862 | if ((i2c->msg.flags & I2C_M_RD) && | |
863 | (int_status & INT_FIFO_FULL_FILLING)) | |
864 | img_i2c_read_fifo(i2c); | |
865 | /* use atomic mode and try to force a stop bit */ | |
866 | i2c->msg_status = -EIO; | |
867 | img_i2c_stop_start(i2c); | |
868 | return 0; | |
869 | } | |
870 | ||
871 | /* Enable transaction halt on start bit */ | |
0f0a3189 | 872 | if (!i2c->last_msg && line_status & LINESTAT_START_BIT_DET) { |
c20821a7 | 873 | img_i2c_transaction_halt(i2c, !i2c->last_msg); |
27bce457 JH |
874 | /* we're no longer interested in the slave event */ |
875 | i2c->int_enable &= ~INT_SLAVE_EVENT; | |
876 | } | |
877 | ||
878 | mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); | |
879 | ||
dd29207e SN |
880 | if (int_status & INT_STOP_DETECTED) { |
881 | /* Drain remaining data in FIFO and complete transaction */ | |
882 | if (i2c->msg.flags & I2C_M_RD) | |
883 | img_i2c_read_fifo(i2c); | |
884 | return ISR_COMPLETE(0); | |
885 | } | |
886 | ||
27bce457 | 887 | if (i2c->msg.flags & I2C_M_RD) { |
c7b0a7c1 | 888 | if (int_status & (INT_FIFO_FULL_FILLING | INT_MASTER_HALTED)) { |
27bce457 JH |
889 | img_i2c_read_fifo(i2c); |
890 | if (i2c->msg.len == 0) | |
891 | return ISR_WAITSTOP; | |
892 | } | |
893 | } else { | |
c7b0a7c1 SN |
894 | if (int_status & (INT_FIFO_EMPTY | INT_MASTER_HALTED)) { |
895 | if ((int_status & INT_FIFO_EMPTY) && | |
896 | i2c->msg.len == 0) | |
27bce457 JH |
897 | return ISR_WAITSTOP; |
898 | img_i2c_write_fifo(i2c); | |
899 | } | |
900 | } | |
c7b0a7c1 SN |
901 | if (int_status & INT_MASTER_HALTED) { |
902 | /* | |
903 | * Release and then enable transaction halt, to | |
904 | * allow only a single byte to proceed. | |
905 | */ | |
906 | img_i2c_transaction_halt(i2c, false); | |
907 | img_i2c_transaction_halt(i2c, !i2c->last_msg); | |
908 | } | |
27bce457 JH |
909 | |
910 | return 0; | |
911 | } | |
912 | ||
913 | static irqreturn_t img_i2c_isr(int irq, void *dev_id) | |
914 | { | |
915 | struct img_i2c *i2c = (struct img_i2c *)dev_id; | |
916 | u32 int_status, line_status; | |
917 | /* We handle transaction completion AFTER accessing registers */ | |
918 | unsigned int hret; | |
919 | ||
920 | /* Read interrupt status register. */ | |
921 | int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG); | |
922 | /* Clear detected interrupts. */ | |
923 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status); | |
924 | ||
925 | /* | |
926 | * Read line status and clear it until it actually is clear. We have | |
927 | * to be careful not to lose any line status bits that get latched. | |
928 | */ | |
929 | line_status = img_i2c_readl(i2c, SCB_STATUS_REG); | |
930 | if (line_status & LINESTAT_LATCHED) { | |
931 | img_i2c_writel(i2c, SCB_CLEAR_REG, | |
932 | (line_status & LINESTAT_LATCHED) | |
933 | >> LINESTAT_CLEAR_SHIFT); | |
934 | img_i2c_wr_rd_fence(i2c); | |
935 | } | |
936 | ||
937 | spin_lock(&i2c->lock); | |
938 | ||
939 | /* Keep track of line status bits received */ | |
940 | i2c->line_status &= ~LINESTAT_INPUT_DATA; | |
941 | i2c->line_status |= line_status; | |
942 | ||
943 | /* | |
944 | * Certain interrupts indicate that sclk low timeout is not | |
945 | * a problem. If any of these are set, just continue. | |
946 | */ | |
947 | if ((int_status & INT_SCLK_LOW_TIMEOUT) && | |
948 | !(int_status & (INT_SLAVE_EVENT | | |
949 | INT_FIFO_EMPTY | | |
950 | INT_FIFO_FULL))) { | |
951 | dev_crit(i2c->adap.dev.parent, | |
952 | "fatal: clock low timeout occurred %s addr 0x%02x\n", | |
953 | (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing", | |
954 | i2c->msg.addr); | |
955 | hret = ISR_FATAL(EIO); | |
956 | goto out; | |
957 | } | |
958 | ||
959 | if (i2c->mode == MODE_ATOMIC) | |
960 | hret = img_i2c_atomic(i2c, int_status, line_status); | |
961 | else if (i2c->mode == MODE_AUTOMATIC) | |
962 | hret = img_i2c_auto(i2c, int_status, line_status); | |
963 | else if (i2c->mode == MODE_SEQUENCE) | |
964 | hret = img_i2c_sequence(i2c, int_status); | |
965 | else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) && | |
966 | (line_status & LINESTAT_STOP_BIT_DET)) | |
967 | hret = ISR_COMPLETE(0); | |
968 | else if (i2c->mode == MODE_RAW) | |
969 | hret = img_i2c_raw(i2c, int_status, line_status); | |
970 | else | |
971 | hret = 0; | |
972 | ||
973 | /* Clear detected level interrupts. */ | |
974 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status & INT_LEVEL); | |
975 | ||
976 | out: | |
977 | if (hret & ISR_WAITSTOP) { | |
978 | /* | |
979 | * Only wait for stop on last message. | |
980 | * Also we may already have detected the stop bit. | |
981 | */ | |
982 | if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET) | |
983 | hret = ISR_COMPLETE(0); | |
984 | else | |
985 | img_i2c_switch_mode(i2c, MODE_WAITSTOP); | |
986 | } | |
987 | ||
988 | /* now we've finished using regs, handle transaction completion */ | |
989 | if (hret & ISR_COMPLETE_M) { | |
990 | int status = -(hret & ISR_STATUS_M); | |
991 | ||
992 | img_i2c_complete_transaction(i2c, status); | |
993 | if (hret & ISR_FATAL_M) | |
994 | img_i2c_switch_mode(i2c, MODE_FATAL); | |
995 | } | |
996 | ||
997 | /* Enable interrupts (int_enable may be altered by changing mode) */ | |
998 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
999 | ||
1000 | spin_unlock(&i2c->lock); | |
1001 | ||
1002 | return IRQ_HANDLED; | |
1003 | } | |
1004 | ||
1005 | /* Force a bus reset sequence and wait for it to complete */ | |
1006 | static int img_i2c_reset_bus(struct img_i2c *i2c) | |
1007 | { | |
1008 | unsigned long flags; | |
913b1d85 | 1009 | unsigned long time_left; |
27bce457 JH |
1010 | |
1011 | spin_lock_irqsave(&i2c->lock, flags); | |
1012 | reinit_completion(&i2c->msg_complete); | |
1013 | img_i2c_reset_start(i2c); | |
1014 | spin_unlock_irqrestore(&i2c->lock, flags); | |
1015 | ||
913b1d85 NMG |
1016 | time_left = wait_for_completion_timeout(&i2c->msg_complete, |
1017 | IMG_I2C_TIMEOUT); | |
1018 | if (time_left == 0) | |
27bce457 JH |
1019 | return -ETIMEDOUT; |
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, | |
1024 | int num) | |
1025 | { | |
1026 | struct img_i2c *i2c = i2c_get_adapdata(adap); | |
1027 | bool atomic = false; | |
1028 | int i, ret; | |
913b1d85 | 1029 | unsigned long time_left; |
27bce457 JH |
1030 | |
1031 | if (i2c->mode == MODE_SUSPEND) { | |
1032 | WARN(1, "refusing to service transaction in suspended state\n"); | |
1033 | return -EIO; | |
1034 | } | |
1035 | ||
1036 | if (i2c->mode == MODE_FATAL) | |
1037 | return -EIO; | |
1038 | ||
1039 | for (i = 0; i < num; i++) { | |
27bce457 JH |
1040 | /* |
1041 | * 0 byte reads are not possible because the slave could try | |
1042 | * and pull the data line low, preventing a stop bit. | |
1043 | */ | |
c55ebe0e | 1044 | if (!msgs[i].len && msgs[i].flags & I2C_M_RD) |
27bce457 JH |
1045 | return -EIO; |
1046 | /* | |
1047 | * 0 byte writes are possible and used for probing, but we | |
1048 | * cannot do them in automatic mode, so use atomic mode | |
1049 | * instead. | |
c55ebe0e SN |
1050 | * |
1051 | * Also, the I2C_M_IGNORE_NAK mode can only be implemented | |
1052 | * in atomic mode. | |
27bce457 | 1053 | */ |
c55ebe0e SN |
1054 | if (!msgs[i].len || |
1055 | (msgs[i].flags & I2C_M_IGNORE_NAK)) | |
1056 | atomic = true; | |
27bce457 JH |
1057 | } |
1058 | ||
1059 | ret = clk_prepare_enable(i2c->scb_clk); | |
1060 | if (ret) | |
1061 | return ret; | |
1062 | ||
1063 | for (i = 0; i < num; i++) { | |
1064 | struct i2c_msg *msg = &msgs[i]; | |
1065 | unsigned long flags; | |
1066 | ||
1067 | spin_lock_irqsave(&i2c->lock, flags); | |
1068 | ||
1069 | /* | |
1070 | * Make a copy of the message struct. We mustn't modify the | |
1071 | * original or we'll confuse drivers and i2c-dev. | |
1072 | */ | |
1073 | i2c->msg = *msg; | |
1074 | i2c->msg_status = 0; | |
1075 | ||
1076 | /* | |
1077 | * After the last message we must have waited for a stop bit. | |
1078 | * Not waiting can cause problems when the clock is disabled | |
1079 | * before the stop bit is sent, and the linux I2C interface | |
1080 | * requires separate transfers not to joined with repeated | |
1081 | * start. | |
1082 | */ | |
1083 | i2c->last_msg = (i == num - 1); | |
1084 | reinit_completion(&i2c->msg_complete); | |
1085 | ||
1ed6faed SN |
1086 | /* |
1087 | * Clear line status and all interrupts before starting a | |
1088 | * transfer, as we may have unserviced interrupts from | |
1089 | * previous transfers that might be handled in the context | |
1090 | * of the new transfer. | |
1091 | */ | |
1092 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); | |
1093 | img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); | |
1094 | ||
c20821a7 | 1095 | if (atomic) { |
27bce457 | 1096 | img_i2c_atomic_start(i2c); |
c20821a7 SN |
1097 | } else { |
1098 | /* | |
1099 | * Enable transaction halt if not the last message in | |
1100 | * the queue so that we can control repeated starts. | |
1101 | */ | |
1102 | img_i2c_transaction_halt(i2c, !i2c->last_msg); | |
1103 | ||
1104 | if (msg->flags & I2C_M_RD) | |
1105 | img_i2c_read(i2c); | |
1106 | else | |
1107 | img_i2c_write(i2c); | |
1108 | ||
1109 | /* | |
1110 | * Release and then enable transaction halt, to | |
1111 | * allow only a single byte to proceed. | |
1112 | * This doesn't have an effect on the initial transfer | |
1113 | * but will allow the following transfers to start | |
1114 | * processing if the previous transfer was marked as | |
1115 | * complete while the i2c block was halted. | |
1116 | */ | |
1117 | img_i2c_transaction_halt(i2c, false); | |
1118 | img_i2c_transaction_halt(i2c, !i2c->last_msg); | |
1119 | } | |
27bce457 JH |
1120 | spin_unlock_irqrestore(&i2c->lock, flags); |
1121 | ||
913b1d85 NMG |
1122 | time_left = wait_for_completion_timeout(&i2c->msg_complete, |
1123 | IMG_I2C_TIMEOUT); | |
27bce457 JH |
1124 | del_timer_sync(&i2c->check_timer); |
1125 | ||
913b1d85 | 1126 | if (time_left == 0) { |
27bce457 JH |
1127 | dev_err(adap->dev.parent, "i2c transfer timed out\n"); |
1128 | i2c->msg_status = -ETIMEDOUT; | |
1129 | break; | |
1130 | } | |
1131 | ||
1132 | if (i2c->msg_status) | |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | clk_disable_unprepare(i2c->scb_clk); | |
1137 | ||
1138 | return i2c->msg_status ? i2c->msg_status : num; | |
1139 | } | |
1140 | ||
1141 | static u32 img_i2c_func(struct i2c_adapter *adap) | |
1142 | { | |
1143 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
1144 | } | |
1145 | ||
1146 | static const struct i2c_algorithm img_i2c_algo = { | |
1147 | .master_xfer = img_i2c_xfer, | |
1148 | .functionality = img_i2c_func, | |
1149 | }; | |
1150 | ||
1151 | static int img_i2c_init(struct img_i2c *i2c) | |
1152 | { | |
1153 | unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh; | |
1154 | unsigned int i, ret, data, prescale, inc, int_bitrate, filt; | |
1155 | struct img_i2c_timings timing; | |
1156 | u32 rev; | |
1157 | ||
1158 | ret = clk_prepare_enable(i2c->scb_clk); | |
1159 | if (ret) | |
1160 | return ret; | |
1161 | ||
1162 | rev = img_i2c_readl(i2c, SCB_CORE_REV_REG); | |
1163 | if ((rev & 0x00ffffff) < 0x00020200) { | |
1164 | dev_info(i2c->adap.dev.parent, | |
1165 | "Unknown hardware revision (%d.%d.%d.%d)\n", | |
1166 | (rev >> 24) & 0xff, (rev >> 16) & 0xff, | |
1167 | (rev >> 8) & 0xff, rev & 0xff); | |
1168 | clk_disable_unprepare(i2c->scb_clk); | |
1169 | return -EINVAL; | |
1170 | } | |
1171 | ||
0e59378b SN |
1172 | /* Fencing enabled by default. */ |
1173 | i2c->need_wr_rd_fence = true; | |
27bce457 | 1174 | |
27bce457 JH |
1175 | /* Determine what mode we're in from the bitrate */ |
1176 | timing = timings[0]; | |
1177 | for (i = 0; i < ARRAY_SIZE(timings); i++) { | |
1178 | if (i2c->bitrate <= timings[i].max_bitrate) { | |
1179 | timing = timings[i]; | |
1180 | break; | |
1181 | } | |
1182 | } | |
58b0497d SN |
1183 | if (i2c->bitrate > timings[ARRAY_SIZE(timings) - 1].max_bitrate) { |
1184 | dev_warn(i2c->adap.dev.parent, | |
1185 | "requested bitrate (%u) is higher than the max bitrate supported (%u)\n", | |
1186 | i2c->bitrate, | |
1187 | timings[ARRAY_SIZE(timings) - 1].max_bitrate); | |
1188 | timing = timings[ARRAY_SIZE(timings) - 1]; | |
1189 | i2c->bitrate = timing.max_bitrate; | |
1190 | } | |
1191 | ||
1192 | bitrate_khz = i2c->bitrate / 1000; | |
1193 | clk_khz = clk_get_rate(i2c->scb_clk) / 1000; | |
27bce457 JH |
1194 | |
1195 | /* Find the prescale that would give us that inc (approx delay = 0) */ | |
1196 | prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz); | |
1197 | prescale = clamp_t(unsigned int, prescale, 1, 8); | |
1198 | clk_khz /= prescale; | |
1199 | ||
1200 | /* Setup the clock increment value */ | |
1201 | inc = (256 * 16 * bitrate_khz) / clk_khz; | |
1202 | ||
1203 | /* | |
1204 | * The clock generation logic allows to filter glitches on the bus. | |
1205 | * This filter is able to remove bus glitches shorter than 50ns. | |
1206 | * If the clock enable rate is greater than 20 MHz, no filtering | |
1207 | * is required, so we need to disable it. | |
1208 | * If it's between the 20-40 MHz range, there's no need to divide | |
1209 | * the clock to get a filter. | |
1210 | */ | |
1211 | if (clk_khz < 20000) { | |
1212 | filt = SCB_FILT_DISABLE; | |
1213 | } else if (clk_khz < 40000) { | |
1214 | filt = SCB_FILT_BYPASS; | |
1215 | } else { | |
1216 | /* Calculate filter clock */ | |
1217 | filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH)); | |
1218 | ||
1219 | /* Scale up if needed */ | |
1220 | if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH)) | |
1221 | inc++; | |
1222 | ||
1223 | if (filt > SCB_FILT_INC_MASK) | |
1224 | filt = SCB_FILT_INC_MASK; | |
1225 | ||
1226 | filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT; | |
1227 | } | |
1228 | data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1); | |
1229 | img_i2c_writel(i2c, SCB_CLK_SET_REG, data); | |
1230 | ||
1231 | /* Obtain the clock period of the fx16 clock in ns */ | |
1232 | clk_period = (256 * 1000000) / (clk_khz * inc); | |
1233 | ||
1234 | /* Calculate the bitrate in terms of internal clock pulses */ | |
1235 | int_bitrate = 1000000 / (bitrate_khz * clk_period); | |
1236 | if ((1000000 % (bitrate_khz * clk_period)) >= | |
1237 | ((bitrate_khz * clk_period) / 2)) | |
1238 | int_bitrate++; | |
1239 | ||
987008db SN |
1240 | /* |
1241 | * Setup clock duty cycle, start with 50% and adjust TCKH and TCKL | |
1242 | * values from there if they don't meet minimum timing requirements | |
1243 | */ | |
1244 | tckh = int_bitrate / 2; | |
1245 | tckl = int_bitrate - tckh; | |
27bce457 | 1246 | |
987008db SN |
1247 | /* Adjust TCKH and TCKL values */ |
1248 | data = DIV_ROUND_UP(timing.tckl, clk_period); | |
27bce457 | 1249 | |
987008db SN |
1250 | if (tckl < data) { |
1251 | tckl = data; | |
1252 | tckh = int_bitrate - tckl; | |
1253 | } | |
27bce457 | 1254 | |
987008db SN |
1255 | if (tckh > 0) |
1256 | --tckh; | |
27bce457 JH |
1257 | |
1258 | if (tckl > 0) | |
987008db | 1259 | --tckl; |
27bce457 | 1260 | |
987008db SN |
1261 | img_i2c_writel(i2c, SCB_TIME_TCKH_REG, tckh); |
1262 | img_i2c_writel(i2c, SCB_TIME_TCKL_REG, tckl); | |
27bce457 JH |
1263 | |
1264 | /* Setup TSDH value */ | |
5728d95f | 1265 | tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); |
27bce457 JH |
1266 | |
1267 | if (tsdh > 1) | |
1268 | data = tsdh - 1; | |
1269 | else | |
1270 | data = 0x01; | |
1271 | img_i2c_writel(i2c, SCB_TIME_TSDH_REG, data); | |
1272 | ||
1273 | /* This value is used later */ | |
1274 | tsdh = data; | |
1275 | ||
1276 | /* Setup TPL value */ | |
1277 | data = timing.tpl / clk_period; | |
1278 | if (data > 0) | |
1279 | --data; | |
1280 | img_i2c_writel(i2c, SCB_TIME_TPL_REG, data); | |
1281 | ||
1282 | /* Setup TPH value */ | |
1283 | data = timing.tph / clk_period; | |
1284 | if (data > 0) | |
1285 | --data; | |
1286 | img_i2c_writel(i2c, SCB_TIME_TPH_REG, data); | |
1287 | ||
1288 | /* Setup TSDL value to TPL + TSDH + 2 */ | |
1289 | img_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2); | |
1290 | ||
1291 | /* Setup TP2S value */ | |
1292 | data = timing.tp2s / clk_period; | |
1293 | if (data > 0) | |
1294 | --data; | |
1295 | img_i2c_writel(i2c, SCB_TIME_TP2S_REG, data); | |
1296 | ||
1297 | img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI); | |
1298 | img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL); | |
1299 | img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL); | |
1300 | ||
1301 | /* Take module out of soft reset and enable clocks */ | |
1302 | img_i2c_soft_reset(i2c); | |
1303 | ||
1304 | /* Disable all interrupts */ | |
1305 | img_i2c_writel(i2c, SCB_INT_MASK_REG, 0); | |
1306 | ||
1307 | /* Clear all interrupts */ | |
1308 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); | |
1309 | ||
1310 | /* Clear the scb_line_status events */ | |
1311 | img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); | |
1312 | ||
1313 | /* Enable interrupts */ | |
1314 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
1315 | ||
1316 | /* Perform a synchronous sequence to reset the bus */ | |
1317 | ret = img_i2c_reset_bus(i2c); | |
1318 | ||
1319 | clk_disable_unprepare(i2c->scb_clk); | |
1320 | ||
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | static int img_i2c_probe(struct platform_device *pdev) | |
1325 | { | |
1326 | struct device_node *node = pdev->dev.of_node; | |
1327 | struct img_i2c *i2c; | |
1328 | struct resource *res; | |
1329 | int irq, ret; | |
1330 | u32 val; | |
1331 | ||
1332 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL); | |
1333 | if (!i2c) | |
1334 | return -ENOMEM; | |
1335 | ||
1336 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1337 | i2c->base = devm_ioremap_resource(&pdev->dev, res); | |
1338 | if (IS_ERR(i2c->base)) | |
1339 | return PTR_ERR(i2c->base); | |
1340 | ||
1341 | irq = platform_get_irq(pdev, 0); | |
1342 | if (irq < 0) { | |
1343 | dev_err(&pdev->dev, "can't get irq number\n"); | |
1344 | return irq; | |
1345 | } | |
1346 | ||
1347 | i2c->sys_clk = devm_clk_get(&pdev->dev, "sys"); | |
1348 | if (IS_ERR(i2c->sys_clk)) { | |
1349 | dev_err(&pdev->dev, "can't get system clock\n"); | |
1350 | return PTR_ERR(i2c->sys_clk); | |
1351 | } | |
1352 | ||
1353 | i2c->scb_clk = devm_clk_get(&pdev->dev, "scb"); | |
1354 | if (IS_ERR(i2c->scb_clk)) { | |
1355 | dev_err(&pdev->dev, "can't get core clock\n"); | |
1356 | return PTR_ERR(i2c->scb_clk); | |
1357 | } | |
1358 | ||
1359 | ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0, | |
1360 | pdev->name, i2c); | |
1361 | if (ret) { | |
1362 | dev_err(&pdev->dev, "can't request irq %d\n", irq); | |
1363 | return ret; | |
1364 | } | |
1365 | ||
1366 | /* Set up the exception check timer */ | |
1367 | init_timer(&i2c->check_timer); | |
1368 | i2c->check_timer.function = img_i2c_check_timer; | |
1369 | i2c->check_timer.data = (unsigned long)i2c; | |
1370 | ||
1371 | i2c->bitrate = timings[0].max_bitrate; | |
1372 | if (!of_property_read_u32(node, "clock-frequency", &val)) | |
1373 | i2c->bitrate = val; | |
1374 | ||
1375 | i2c_set_adapdata(&i2c->adap, i2c); | |
1376 | i2c->adap.dev.parent = &pdev->dev; | |
1377 | i2c->adap.dev.of_node = node; | |
1378 | i2c->adap.owner = THIS_MODULE; | |
1379 | i2c->adap.algo = &img_i2c_algo; | |
1380 | i2c->adap.retries = 5; | |
1381 | i2c->adap.nr = pdev->id; | |
1382 | snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C"); | |
1383 | ||
1384 | img_i2c_switch_mode(i2c, MODE_INACTIVE); | |
1385 | spin_lock_init(&i2c->lock); | |
1386 | init_completion(&i2c->msg_complete); | |
1387 | ||
1388 | platform_set_drvdata(pdev, i2c); | |
1389 | ||
1390 | ret = clk_prepare_enable(i2c->sys_clk); | |
1391 | if (ret) | |
1392 | return ret; | |
1393 | ||
1394 | ret = img_i2c_init(i2c); | |
1395 | if (ret) | |
1396 | goto disable_clk; | |
1397 | ||
1398 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1399 | if (ret < 0) { | |
1400 | dev_err(&pdev->dev, "failed to add adapter\n"); | |
1401 | goto disable_clk; | |
1402 | } | |
1403 | ||
1404 | return 0; | |
1405 | ||
1406 | disable_clk: | |
1407 | clk_disable_unprepare(i2c->sys_clk); | |
1408 | return ret; | |
1409 | } | |
1410 | ||
1411 | static int img_i2c_remove(struct platform_device *dev) | |
1412 | { | |
1413 | struct img_i2c *i2c = platform_get_drvdata(dev); | |
1414 | ||
1415 | i2c_del_adapter(&i2c->adap); | |
1416 | clk_disable_unprepare(i2c->sys_clk); | |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
1421 | #ifdef CONFIG_PM_SLEEP | |
1422 | static int img_i2c_suspend(struct device *dev) | |
1423 | { | |
1424 | struct img_i2c *i2c = dev_get_drvdata(dev); | |
1425 | ||
1426 | img_i2c_switch_mode(i2c, MODE_SUSPEND); | |
1427 | ||
1428 | clk_disable_unprepare(i2c->sys_clk); | |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
1433 | static int img_i2c_resume(struct device *dev) | |
1434 | { | |
1435 | struct img_i2c *i2c = dev_get_drvdata(dev); | |
1436 | int ret; | |
1437 | ||
1438 | ret = clk_prepare_enable(i2c->sys_clk); | |
1439 | if (ret) | |
1440 | return ret; | |
1441 | ||
1442 | img_i2c_init(i2c); | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | #endif /* CONFIG_PM_SLEEP */ | |
1447 | ||
1448 | static SIMPLE_DEV_PM_OPS(img_i2c_pm, img_i2c_suspend, img_i2c_resume); | |
1449 | ||
1450 | static const struct of_device_id img_scb_i2c_match[] = { | |
1451 | { .compatible = "img,scb-i2c" }, | |
1452 | { } | |
1453 | }; | |
1454 | MODULE_DEVICE_TABLE(of, img_scb_i2c_match); | |
1455 | ||
1456 | static struct platform_driver img_scb_i2c_driver = { | |
1457 | .driver = { | |
1458 | .name = "img-i2c-scb", | |
1459 | .of_match_table = img_scb_i2c_match, | |
1460 | .pm = &img_i2c_pm, | |
1461 | }, | |
1462 | .probe = img_i2c_probe, | |
1463 | .remove = img_i2c_remove, | |
1464 | }; | |
1465 | module_platform_driver(img_scb_i2c_driver); | |
1466 | ||
1467 | MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>"); | |
1468 | MODULE_DESCRIPTION("IMG host I2C driver"); | |
1469 | MODULE_LICENSE("GPL v2"); |