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aa11e38c DA |
1 | /* |
2 | * Copyright (C) 2002 Motorola GSG-China | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, | |
17 | * USA. | |
18 | * | |
19 | * Author: | |
20 | * Darius Augulis, Teltonika Inc. | |
21 | * | |
22 | * Desc.: | |
23 | * Implementation of I2C Adapter/Algorithm Driver | |
24 | * for I2C Bus integrated in Freescale i.MX/MXC processors | |
25 | * | |
26 | * Derived from Motorola GSG China I2C example driver | |
27 | * | |
28 | * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de | |
29 | * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de | |
30 | * Copyright (C) 2007 RightHand Technologies, Inc. | |
31 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> | |
32 | * | |
d533f049 JL |
33 | * Copyright 2013 Freescale Semiconductor, Inc. |
34 | * | |
aa11e38c DA |
35 | */ |
36 | ||
37 | /** Includes ******************************************************************* | |
38 | *******************************************************************************/ | |
39 | ||
40 | #include <linux/init.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/module.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/delay.h> | |
47 | #include <linux/i2c.h> | |
48 | #include <linux/io.h> | |
49 | #include <linux/sched.h> | |
50 | #include <linux/platform_device.h> | |
51 | #include <linux/clk.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
dfcd04b1 SG |
53 | #include <linux/of.h> |
54 | #include <linux/of_device.h> | |
55 | #include <linux/of_i2c.h> | |
82906b13 | 56 | #include <linux/platform_data/i2c-imx.h> |
aa11e38c DA |
57 | |
58 | /** Defines ******************************************************************** | |
59 | *******************************************************************************/ | |
60 | ||
61 | /* This will be the driver name the kernel reports */ | |
62 | #define DRIVER_NAME "imx-i2c" | |
63 | ||
64 | /* Default value */ | |
65 | #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ | |
66 | ||
67 | /* IMX I2C registers */ | |
68 | #define IMX_I2C_IADR 0x00 /* i2c slave address */ | |
69 | #define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ | |
70 | #define IMX_I2C_I2CR 0x08 /* i2c control */ | |
71 | #define IMX_I2C_I2SR 0x0C /* i2c status */ | |
72 | #define IMX_I2C_I2DR 0x10 /* i2c transfer data */ | |
73 | ||
74 | /* Bits of IMX I2C registers */ | |
75 | #define I2SR_RXAK 0x01 | |
76 | #define I2SR_IIF 0x02 | |
77 | #define I2SR_SRW 0x04 | |
78 | #define I2SR_IAL 0x10 | |
79 | #define I2SR_IBB 0x20 | |
80 | #define I2SR_IAAS 0x40 | |
81 | #define I2SR_ICF 0x80 | |
82 | #define I2CR_RSTA 0x04 | |
83 | #define I2CR_TXAK 0x08 | |
84 | #define I2CR_MTX 0x10 | |
85 | #define I2CR_MSTA 0x20 | |
86 | #define I2CR_IIEN 0x40 | |
87 | #define I2CR_IEN 0x80 | |
88 | ||
89 | /** Variables ****************************************************************** | |
90 | *******************************************************************************/ | |
91 | ||
aa11e38c DA |
92 | /* |
93 | * sorted list of clock divider, register value pairs | |
94 | * taken from table 26-5, p.26-9, Freescale i.MX | |
95 | * Integrated Portable System Processor Reference Manual | |
96 | * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 | |
97 | * | |
98 | * Duplicated divider values removed from list | |
99 | */ | |
d533f049 JL |
100 | struct imx_i2c_clk_pair { |
101 | u16 div; | |
102 | u16 val; | |
103 | }; | |
aa11e38c | 104 | |
d533f049 | 105 | static struct imx_i2c_clk_pair __initdata i2c_clk_div[] = { |
aa11e38c DA |
106 | { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, |
107 | { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, | |
108 | { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, | |
109 | { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, | |
110 | { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, | |
111 | { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, | |
112 | { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, | |
113 | { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, | |
114 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, | |
115 | { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, | |
116 | { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, | |
117 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, | |
118 | { 3072, 0x1E }, { 3840, 0x1F } | |
119 | }; | |
120 | ||
5bdfba29 SG |
121 | enum imx_i2c_type { |
122 | IMX1_I2C, | |
123 | IMX21_I2C, | |
124 | }; | |
125 | ||
aa11e38c DA |
126 | struct imx_i2c_struct { |
127 | struct i2c_adapter adapter; | |
aa11e38c DA |
128 | struct clk *clk; |
129 | void __iomem *base; | |
aa11e38c DA |
130 | wait_queue_head_t queue; |
131 | unsigned long i2csr; | |
65de394d | 132 | unsigned int disable_delay; |
43309f3b | 133 | int stopped; |
db3a3d4e | 134 | unsigned int ifdr; /* IMX_I2C_IFDR */ |
5bdfba29 SG |
135 | enum imx_i2c_type devtype; |
136 | }; | |
137 | ||
138 | static struct platform_device_id imx_i2c_devtype[] = { | |
139 | { | |
140 | .name = "imx1-i2c", | |
141 | .driver_data = IMX1_I2C, | |
142 | }, { | |
143 | .name = "imx21-i2c", | |
144 | .driver_data = IMX21_I2C, | |
145 | }, { | |
146 | /* sentinel */ | |
147 | } | |
aa11e38c | 148 | }; |
5bdfba29 | 149 | MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); |
aa11e38c | 150 | |
dfcd04b1 | 151 | static const struct of_device_id i2c_imx_dt_ids[] = { |
5bdfba29 SG |
152 | { .compatible = "fsl,imx1-i2c", .data = &imx_i2c_devtype[IMX1_I2C], }, |
153 | { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], }, | |
dfcd04b1 SG |
154 | { /* sentinel */ } |
155 | }; | |
2f641a8b | 156 | MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); |
dfcd04b1 | 157 | |
5bdfba29 SG |
158 | static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) |
159 | { | |
160 | return i2c_imx->devtype == IMX1_I2C; | |
161 | } | |
162 | ||
1d5ef2a8 JL |
163 | static inline void imx_i2c_write_reg(unsigned int val, |
164 | struct imx_i2c_struct *i2c_imx, unsigned int reg) | |
165 | { | |
166 | writeb(val, i2c_imx->base + reg); | |
167 | } | |
168 | ||
169 | static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, | |
170 | unsigned int reg) | |
171 | { | |
172 | return readb(i2c_imx->base + reg); | |
173 | } | |
174 | ||
aa11e38c DA |
175 | /** Functions for IMX I2C adapter driver *************************************** |
176 | *******************************************************************************/ | |
177 | ||
43309f3b | 178 | static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) |
aa11e38c DA |
179 | { |
180 | unsigned long orig_jiffies = jiffies; | |
43309f3b | 181 | unsigned int temp; |
aa11e38c DA |
182 | |
183 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
184 | ||
43309f3b | 185 | while (1) { |
1d5ef2a8 | 186 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
43309f3b RZ |
187 | if (for_busy && (temp & I2SR_IBB)) |
188 | break; | |
189 | if (!for_busy && !(temp & I2SR_IBB)) | |
190 | break; | |
da9c99fc | 191 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
aa11e38c DA |
192 | dev_dbg(&i2c_imx->adapter.dev, |
193 | "<%s> I2C bus is busy\n", __func__); | |
da9c99fc | 194 | return -ETIMEDOUT; |
aa11e38c DA |
195 | } |
196 | schedule(); | |
197 | } | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) | |
203 | { | |
e39428d5 | 204 | wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); |
aa11e38c | 205 | |
e39428d5 | 206 | if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { |
aa11e38c DA |
207 | dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); |
208 | return -ETIMEDOUT; | |
209 | } | |
210 | dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); | |
211 | i2c_imx->i2csr = 0; | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) | |
216 | { | |
1d5ef2a8 | 217 | if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { |
aa11e38c DA |
218 | dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); |
219 | return -EIO; /* No ACK */ | |
220 | } | |
221 | ||
222 | dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); | |
223 | return 0; | |
224 | } | |
225 | ||
43309f3b | 226 | static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) |
aa11e38c DA |
227 | { |
228 | unsigned int temp = 0; | |
43309f3b | 229 | int result; |
aa11e38c DA |
230 | |
231 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
232 | ||
83914337 | 233 | clk_prepare_enable(i2c_imx->clk); |
1d5ef2a8 | 234 | imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); |
aa11e38c | 235 | /* Enable I2C controller */ |
1d5ef2a8 JL |
236 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); |
237 | imx_i2c_write_reg(I2CR_IEN, i2c_imx, IMX_I2C_I2CR); | |
43309f3b RZ |
238 | |
239 | /* Wait controller to be stable */ | |
240 | udelay(50); | |
241 | ||
aa11e38c | 242 | /* Start I2C transaction */ |
1d5ef2a8 | 243 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 244 | temp |= I2CR_MSTA; |
1d5ef2a8 | 245 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
246 | result = i2c_imx_bus_busy(i2c_imx, 1); |
247 | if (result) | |
248 | return result; | |
249 | i2c_imx->stopped = 0; | |
250 | ||
aa11e38c | 251 | temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; |
1d5ef2a8 | 252 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b | 253 | return result; |
aa11e38c DA |
254 | } |
255 | ||
256 | static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) | |
257 | { | |
258 | unsigned int temp = 0; | |
259 | ||
43309f3b RZ |
260 | if (!i2c_imx->stopped) { |
261 | /* Stop I2C transaction */ | |
262 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
1d5ef2a8 | 263 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
43309f3b | 264 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1d5ef2a8 | 265 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b | 266 | } |
5bdfba29 | 267 | if (is_imx1_i2c(i2c_imx)) { |
a4094a76 RZ |
268 | /* |
269 | * This delay caused by an i.MXL hardware bug. | |
270 | * If no (or too short) delay, no "STOP" bit will be generated. | |
271 | */ | |
272 | udelay(i2c_imx->disable_delay); | |
273 | } | |
43309f3b | 274 | |
a1ee06b7 | 275 | if (!i2c_imx->stopped) { |
43309f3b | 276 | i2c_imx_bus_busy(i2c_imx, 0); |
a1ee06b7 VL |
277 | i2c_imx->stopped = 1; |
278 | } | |
43309f3b | 279 | |
aa11e38c | 280 | /* Disable I2C controller */ |
1d5ef2a8 | 281 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); |
83914337 | 282 | clk_disable_unprepare(i2c_imx->clk); |
aa11e38c DA |
283 | } |
284 | ||
285 | static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, | |
286 | unsigned int rate) | |
287 | { | |
288 | unsigned int i2c_clk_rate; | |
289 | unsigned int div; | |
290 | int i; | |
291 | ||
292 | /* Divider value calculation */ | |
293 | i2c_clk_rate = clk_get_rate(i2c_imx->clk); | |
294 | div = (i2c_clk_rate + rate - 1) / rate; | |
d533f049 | 295 | if (div < i2c_clk_div[0].div) |
aa11e38c | 296 | i = 0; |
d533f049 | 297 | else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1].div) |
aa11e38c DA |
298 | i = ARRAY_SIZE(i2c_clk_div) - 1; |
299 | else | |
d533f049 | 300 | for (i = 0; i2c_clk_div[i].div < div; i++); |
aa11e38c | 301 | |
db3a3d4e | 302 | /* Store divider value */ |
d533f049 | 303 | i2c_imx->ifdr = i2c_clk_div[i].val; |
aa11e38c DA |
304 | |
305 | /* | |
306 | * There dummy delay is calculated. | |
307 | * It should be about one I2C clock period long. | |
308 | * This delay is used in I2C bus disable function | |
309 | * to fix chip hardware bug. | |
310 | */ | |
d533f049 | 311 | i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div |
aa11e38c DA |
312 | + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); |
313 | ||
314 | /* dev_dbg() can't be used, because adapter is not yet registered */ | |
315 | #ifdef CONFIG_I2C_DEBUG_BUS | |
002f002d | 316 | dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n", |
aa11e38c | 317 | __func__, i2c_clk_rate, div); |
002f002d | 318 | dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n", |
d533f049 | 319 | __func__, i2c_clk_div[i].val, i2c_clk_div[i].div); |
aa11e38c DA |
320 | #endif |
321 | } | |
322 | ||
323 | static irqreturn_t i2c_imx_isr(int irq, void *dev_id) | |
324 | { | |
325 | struct imx_i2c_struct *i2c_imx = dev_id; | |
326 | unsigned int temp; | |
327 | ||
1d5ef2a8 | 328 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
aa11e38c DA |
329 | if (temp & I2SR_IIF) { |
330 | /* save status register */ | |
331 | i2c_imx->i2csr = temp; | |
332 | temp &= ~I2SR_IIF; | |
1d5ef2a8 | 333 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); |
e39428d5 | 334 | wake_up(&i2c_imx->queue); |
aa11e38c DA |
335 | return IRQ_HANDLED; |
336 | } | |
337 | ||
338 | return IRQ_NONE; | |
339 | } | |
340 | ||
341 | static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
342 | { | |
343 | int i, result; | |
344 | ||
345 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", | |
346 | __func__, msgs->addr << 1); | |
347 | ||
348 | /* write slave address */ | |
1d5ef2a8 | 349 | imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
350 | result = i2c_imx_trx_complete(i2c_imx); |
351 | if (result) | |
352 | return result; | |
353 | result = i2c_imx_acked(i2c_imx); | |
354 | if (result) | |
355 | return result; | |
356 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); | |
357 | ||
358 | /* write data */ | |
359 | for (i = 0; i < msgs->len; i++) { | |
360 | dev_dbg(&i2c_imx->adapter.dev, | |
361 | "<%s> write byte: B%d=0x%X\n", | |
362 | __func__, i, msgs->buf[i]); | |
1d5ef2a8 | 363 | imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
364 | result = i2c_imx_trx_complete(i2c_imx); |
365 | if (result) | |
366 | return result; | |
367 | result = i2c_imx_acked(i2c_imx); | |
368 | if (result) | |
369 | return result; | |
370 | } | |
371 | return 0; | |
372 | } | |
373 | ||
374 | static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
375 | { | |
376 | int i, result; | |
377 | unsigned int temp; | |
378 | ||
379 | dev_dbg(&i2c_imx->adapter.dev, | |
380 | "<%s> write slave address: addr=0x%x\n", | |
381 | __func__, (msgs->addr << 1) | 0x01); | |
382 | ||
383 | /* write slave address */ | |
1d5ef2a8 | 384 | imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
385 | result = i2c_imx_trx_complete(i2c_imx); |
386 | if (result) | |
387 | return result; | |
388 | result = i2c_imx_acked(i2c_imx); | |
389 | if (result) | |
390 | return result; | |
391 | ||
392 | dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); | |
393 | ||
394 | /* setup bus to read data */ | |
1d5ef2a8 | 395 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c DA |
396 | temp &= ~I2CR_MTX; |
397 | if (msgs->len - 1) | |
398 | temp &= ~I2CR_TXAK; | |
1d5ef2a8 JL |
399 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
400 | imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ | |
aa11e38c DA |
401 | |
402 | dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); | |
403 | ||
404 | /* read data */ | |
405 | for (i = 0; i < msgs->len; i++) { | |
406 | result = i2c_imx_trx_complete(i2c_imx); | |
407 | if (result) | |
408 | return result; | |
409 | if (i == (msgs->len - 1)) { | |
43309f3b RZ |
410 | /* It must generate STOP before read I2DR to prevent |
411 | controller from generating another clock cycle */ | |
aa11e38c DA |
412 | dev_dbg(&i2c_imx->adapter.dev, |
413 | "<%s> clear MSTA\n", __func__); | |
1d5ef2a8 | 414 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
43309f3b | 415 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1d5ef2a8 | 416 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
417 | i2c_imx_bus_busy(i2c_imx, 0); |
418 | i2c_imx->stopped = 1; | |
aa11e38c DA |
419 | } else if (i == (msgs->len - 2)) { |
420 | dev_dbg(&i2c_imx->adapter.dev, | |
421 | "<%s> set TXAK\n", __func__); | |
1d5ef2a8 | 422 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 423 | temp |= I2CR_TXAK; |
1d5ef2a8 | 424 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 425 | } |
1d5ef2a8 | 426 | msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
427 | dev_dbg(&i2c_imx->adapter.dev, |
428 | "<%s> read byte: B%d=0x%X\n", | |
429 | __func__, i, msgs->buf[i]); | |
430 | } | |
431 | return 0; | |
432 | } | |
433 | ||
434 | static int i2c_imx_xfer(struct i2c_adapter *adapter, | |
435 | struct i2c_msg *msgs, int num) | |
436 | { | |
437 | unsigned int i, temp; | |
438 | int result; | |
439 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); | |
440 | ||
441 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
442 | ||
43309f3b RZ |
443 | /* Start I2C transfer */ |
444 | result = i2c_imx_start(i2c_imx); | |
aa11e38c DA |
445 | if (result) |
446 | goto fail0; | |
447 | ||
aa11e38c DA |
448 | /* read/write data */ |
449 | for (i = 0; i < num; i++) { | |
450 | if (i) { | |
451 | dev_dbg(&i2c_imx->adapter.dev, | |
452 | "<%s> repeated start\n", __func__); | |
1d5ef2a8 | 453 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 454 | temp |= I2CR_RSTA; |
1d5ef2a8 | 455 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
456 | result = i2c_imx_bus_busy(i2c_imx, 1); |
457 | if (result) | |
458 | goto fail0; | |
aa11e38c DA |
459 | } |
460 | dev_dbg(&i2c_imx->adapter.dev, | |
461 | "<%s> transfer message: %d\n", __func__, i); | |
462 | /* write/read data */ | |
463 | #ifdef CONFIG_I2C_DEBUG_BUS | |
1d5ef2a8 | 464 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c DA |
465 | dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " |
466 | "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, | |
467 | (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), | |
468 | (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), | |
469 | (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); | |
1d5ef2a8 | 470 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
aa11e38c DA |
471 | dev_dbg(&i2c_imx->adapter.dev, |
472 | "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " | |
473 | "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, | |
474 | (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), | |
475 | (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), | |
476 | (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), | |
477 | (temp & I2SR_RXAK ? 1 : 0)); | |
478 | #endif | |
479 | if (msgs[i].flags & I2C_M_RD) | |
480 | result = i2c_imx_read(i2c_imx, &msgs[i]); | |
481 | else | |
482 | result = i2c_imx_write(i2c_imx, &msgs[i]); | |
da9c99fc AP |
483 | if (result) |
484 | goto fail0; | |
aa11e38c DA |
485 | } |
486 | ||
487 | fail0: | |
488 | /* Stop I2C transfer */ | |
489 | i2c_imx_stop(i2c_imx); | |
490 | ||
491 | dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, | |
492 | (result < 0) ? "error" : "success msg", | |
493 | (result < 0) ? result : num); | |
494 | return (result < 0) ? result : num; | |
495 | } | |
496 | ||
497 | static u32 i2c_imx_func(struct i2c_adapter *adapter) | |
498 | { | |
499 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
500 | } | |
501 | ||
502 | static struct i2c_algorithm i2c_imx_algo = { | |
503 | .master_xfer = i2c_imx_xfer, | |
504 | .functionality = i2c_imx_func, | |
505 | }; | |
506 | ||
507 | static int __init i2c_imx_probe(struct platform_device *pdev) | |
508 | { | |
5bdfba29 SG |
509 | const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, |
510 | &pdev->dev); | |
aa11e38c DA |
511 | struct imx_i2c_struct *i2c_imx; |
512 | struct resource *res; | |
593702c7 | 513 | struct imxi2c_platform_data *pdata = pdev->dev.platform_data; |
0fc1347a | 514 | const struct platform_device_id *imx_id; |
aa11e38c | 515 | void __iomem *base; |
8c88ab04 WS |
516 | int irq, ret; |
517 | u32 bitrate; | |
aa11e38c DA |
518 | |
519 | dev_dbg(&pdev->dev, "<%s>\n", __func__); | |
520 | ||
aa11e38c DA |
521 | irq = platform_get_irq(pdev, 0); |
522 | if (irq < 0) { | |
523 | dev_err(&pdev->dev, "can't get irq number\n"); | |
524 | return -ENOENT; | |
525 | } | |
526 | ||
3cc2d009 | 527 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
528 | base = devm_ioremap_resource(&pdev->dev, res); |
529 | if (IS_ERR(base)) | |
530 | return PTR_ERR(base); | |
aa11e38c | 531 | |
9f8a3e7f RZ |
532 | i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct), |
533 | GFP_KERNEL); | |
aa11e38c DA |
534 | if (!i2c_imx) { |
535 | dev_err(&pdev->dev, "can't allocate interface\n"); | |
9f8a3e7f | 536 | return -ENOMEM; |
309c18d2 DA |
537 | } |
538 | ||
5bdfba29 | 539 | if (of_id) |
0fc1347a JL |
540 | imx_id = of_id->data; |
541 | else | |
542 | imx_id = platform_get_device_id(pdev); | |
543 | ||
544 | i2c_imx->devtype = imx_id->driver_data; | |
5bdfba29 | 545 | |
aa11e38c | 546 | /* Setup i2c_imx driver structure */ |
973c5ed4 | 547 | strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); |
aa11e38c DA |
548 | i2c_imx->adapter.owner = THIS_MODULE; |
549 | i2c_imx->adapter.algo = &i2c_imx_algo; | |
550 | i2c_imx->adapter.dev.parent = &pdev->dev; | |
551 | i2c_imx->adapter.nr = pdev->id; | |
dfcd04b1 | 552 | i2c_imx->adapter.dev.of_node = pdev->dev.of_node; |
aa11e38c | 553 | i2c_imx->base = base; |
aa11e38c DA |
554 | |
555 | /* Get I2C clock */ | |
1f09c672 | 556 | i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); |
aa11e38c | 557 | if (IS_ERR(i2c_imx->clk)) { |
aa11e38c | 558 | dev_err(&pdev->dev, "can't get I2C clock\n"); |
9f8a3e7f | 559 | return PTR_ERR(i2c_imx->clk); |
aa11e38c | 560 | } |
aa11e38c | 561 | |
46f2832b JL |
562 | ret = clk_prepare_enable(i2c_imx->clk); |
563 | if (ret) { | |
564 | dev_err(&pdev->dev, "can't enable I2C clock\n"); | |
565 | return ret; | |
566 | } | |
aa11e38c | 567 | /* Request IRQ */ |
9f8a3e7f RZ |
568 | ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0, |
569 | pdev->name, i2c_imx); | |
aa11e38c | 570 | if (ret) { |
9f8a3e7f RZ |
571 | dev_err(&pdev->dev, "can't claim irq %d\n", irq); |
572 | return ret; | |
aa11e38c DA |
573 | } |
574 | ||
575 | /* Init queue */ | |
576 | init_waitqueue_head(&i2c_imx->queue); | |
577 | ||
578 | /* Set up adapter data */ | |
579 | i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); | |
580 | ||
581 | /* Set up clock divider */ | |
dfcd04b1 SG |
582 | bitrate = IMX_I2C_BIT_RATE; |
583 | ret = of_property_read_u32(pdev->dev.of_node, | |
584 | "clock-frequency", &bitrate); | |
585 | if (ret < 0 && pdata && pdata->bitrate) | |
586 | bitrate = pdata->bitrate; | |
587 | i2c_imx_set_clk(i2c_imx, bitrate); | |
aa11e38c DA |
588 | |
589 | /* Set up chip registers to defaults */ | |
1d5ef2a8 JL |
590 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); |
591 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); | |
aa11e38c DA |
592 | |
593 | /* Add I2C adapter */ | |
594 | ret = i2c_add_numbered_adapter(&i2c_imx->adapter); | |
595 | if (ret < 0) { | |
596 | dev_err(&pdev->dev, "registration failed\n"); | |
9f8a3e7f | 597 | return ret; |
aa11e38c DA |
598 | } |
599 | ||
dfcd04b1 SG |
600 | of_i2c_register_devices(&i2c_imx->adapter); |
601 | ||
aa11e38c DA |
602 | /* Set up platform driver data */ |
603 | platform_set_drvdata(pdev, i2c_imx); | |
46f2832b | 604 | clk_disable_unprepare(i2c_imx->clk); |
aa11e38c | 605 | |
9f8a3e7f | 606 | dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); |
aa11e38c | 607 | dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", |
9f8a3e7f RZ |
608 | res->start, res->end); |
609 | dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n", | |
610 | resource_size(res), res->start); | |
aa11e38c DA |
611 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", |
612 | i2c_imx->adapter.name); | |
06d141e9 | 613 | dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); |
aa11e38c DA |
614 | |
615 | return 0; /* Return OK */ | |
aa11e38c DA |
616 | } |
617 | ||
618 | static int __exit i2c_imx_remove(struct platform_device *pdev) | |
619 | { | |
620 | struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); | |
aa11e38c DA |
621 | |
622 | /* remove adapter */ | |
623 | dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); | |
624 | i2c_del_adapter(&i2c_imx->adapter); | |
aa11e38c | 625 | |
aa11e38c | 626 | /* setup chip registers to defaults */ |
1d5ef2a8 JL |
627 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); |
628 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); | |
629 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); | |
630 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); | |
aa11e38c | 631 | |
aa11e38c DA |
632 | return 0; |
633 | } | |
634 | ||
635 | static struct platform_driver i2c_imx_driver = { | |
aa11e38c DA |
636 | .remove = __exit_p(i2c_imx_remove), |
637 | .driver = { | |
638 | .name = DRIVER_NAME, | |
639 | .owner = THIS_MODULE, | |
dfcd04b1 | 640 | .of_match_table = i2c_imx_dt_ids, |
5bdfba29 SG |
641 | }, |
642 | .id_table = imx_i2c_devtype, | |
aa11e38c DA |
643 | }; |
644 | ||
645 | static int __init i2c_adap_imx_init(void) | |
646 | { | |
647 | return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe); | |
648 | } | |
5d3f3331 | 649 | subsys_initcall(i2c_adap_imx_init); |
aa11e38c DA |
650 | |
651 | static void __exit i2c_adap_imx_exit(void) | |
652 | { | |
653 | platform_driver_unregister(&i2c_imx_driver); | |
654 | } | |
aa11e38c DA |
655 | module_exit(i2c_adap_imx_exit); |
656 | ||
657 | MODULE_LICENSE("GPL"); | |
658 | MODULE_AUTHOR("Darius Augulis"); | |
659 | MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); | |
660 | MODULE_ALIAS("platform:" DRIVER_NAME); |