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aa11e38c DA |
1 | /* |
2 | * Copyright (C) 2002 Motorola GSG-China | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, | |
17 | * USA. | |
18 | * | |
19 | * Author: | |
20 | * Darius Augulis, Teltonika Inc. | |
21 | * | |
22 | * Desc.: | |
23 | * Implementation of I2C Adapter/Algorithm Driver | |
24 | * for I2C Bus integrated in Freescale i.MX/MXC processors | |
25 | * | |
26 | * Derived from Motorola GSG China I2C example driver | |
27 | * | |
28 | * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de | |
29 | * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de | |
30 | * Copyright (C) 2007 RightHand Technologies, Inc. | |
31 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> | |
32 | * | |
33 | */ | |
34 | ||
35 | /** Includes ******************************************************************* | |
36 | *******************************************************************************/ | |
37 | ||
38 | #include <linux/init.h> | |
39 | #include <linux/kernel.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/errno.h> | |
42 | #include <linux/err.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/i2c.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/sched.h> | |
48 | #include <linux/platform_device.h> | |
49 | #include <linux/clk.h> | |
50 | ||
51 | #include <mach/irqs.h> | |
52 | #include <mach/hardware.h> | |
53 | #include <mach/i2c.h> | |
54 | ||
55 | /** Defines ******************************************************************** | |
56 | *******************************************************************************/ | |
57 | ||
58 | /* This will be the driver name the kernel reports */ | |
59 | #define DRIVER_NAME "imx-i2c" | |
60 | ||
61 | /* Default value */ | |
62 | #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ | |
63 | ||
64 | /* IMX I2C registers */ | |
65 | #define IMX_I2C_IADR 0x00 /* i2c slave address */ | |
66 | #define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ | |
67 | #define IMX_I2C_I2CR 0x08 /* i2c control */ | |
68 | #define IMX_I2C_I2SR 0x0C /* i2c status */ | |
69 | #define IMX_I2C_I2DR 0x10 /* i2c transfer data */ | |
70 | ||
71 | /* Bits of IMX I2C registers */ | |
72 | #define I2SR_RXAK 0x01 | |
73 | #define I2SR_IIF 0x02 | |
74 | #define I2SR_SRW 0x04 | |
75 | #define I2SR_IAL 0x10 | |
76 | #define I2SR_IBB 0x20 | |
77 | #define I2SR_IAAS 0x40 | |
78 | #define I2SR_ICF 0x80 | |
79 | #define I2CR_RSTA 0x04 | |
80 | #define I2CR_TXAK 0x08 | |
81 | #define I2CR_MTX 0x10 | |
82 | #define I2CR_MSTA 0x20 | |
83 | #define I2CR_IIEN 0x40 | |
84 | #define I2CR_IEN 0x80 | |
85 | ||
86 | /** Variables ****************************************************************** | |
87 | *******************************************************************************/ | |
88 | ||
aa11e38c DA |
89 | /* |
90 | * sorted list of clock divider, register value pairs | |
91 | * taken from table 26-5, p.26-9, Freescale i.MX | |
92 | * Integrated Portable System Processor Reference Manual | |
93 | * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 | |
94 | * | |
95 | * Duplicated divider values removed from list | |
96 | */ | |
97 | ||
98 | static u16 __initdata i2c_clk_div[50][2] = { | |
99 | { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, | |
100 | { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, | |
101 | { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, | |
102 | { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, | |
103 | { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, | |
104 | { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, | |
105 | { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, | |
106 | { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, | |
107 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, | |
108 | { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, | |
109 | { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, | |
110 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, | |
111 | { 3072, 0x1E }, { 3840, 0x1F } | |
112 | }; | |
113 | ||
114 | struct imx_i2c_struct { | |
115 | struct i2c_adapter adapter; | |
116 | struct resource *res; | |
117 | struct clk *clk; | |
118 | void __iomem *base; | |
119 | int irq; | |
120 | wait_queue_head_t queue; | |
121 | unsigned long i2csr; | |
65de394d | 122 | unsigned int disable_delay; |
43309f3b | 123 | int stopped; |
aa11e38c DA |
124 | }; |
125 | ||
126 | /** Functions for IMX I2C adapter driver *************************************** | |
127 | *******************************************************************************/ | |
128 | ||
43309f3b | 129 | static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) |
aa11e38c DA |
130 | { |
131 | unsigned long orig_jiffies = jiffies; | |
43309f3b | 132 | unsigned int temp; |
aa11e38c DA |
133 | |
134 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
135 | ||
43309f3b RZ |
136 | while (1) { |
137 | temp = readb(i2c_imx->base + IMX_I2C_I2SR); | |
138 | if (for_busy && (temp & I2SR_IBB)) | |
139 | break; | |
140 | if (!for_busy && !(temp & I2SR_IBB)) | |
141 | break; | |
aa11e38c DA |
142 | if (signal_pending(current)) { |
143 | dev_dbg(&i2c_imx->adapter.dev, | |
144 | "<%s> I2C Interrupted\n", __func__); | |
145 | return -EINTR; | |
146 | } | |
147 | if (time_after(jiffies, orig_jiffies + HZ / 1000)) { | |
148 | dev_dbg(&i2c_imx->adapter.dev, | |
149 | "<%s> I2C bus is busy\n", __func__); | |
150 | return -EIO; | |
151 | } | |
152 | schedule(); | |
153 | } | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) | |
159 | { | |
160 | int result; | |
161 | ||
162 | result = wait_event_interruptible_timeout(i2c_imx->queue, | |
163 | i2c_imx->i2csr & I2SR_IIF, HZ / 10); | |
164 | ||
165 | if (unlikely(result < 0)) { | |
166 | dev_dbg(&i2c_imx->adapter.dev, "<%s> result < 0\n", __func__); | |
167 | return result; | |
168 | } else if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { | |
169 | dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); | |
170 | return -ETIMEDOUT; | |
171 | } | |
172 | dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); | |
173 | i2c_imx->i2csr = 0; | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) | |
178 | { | |
179 | if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) { | |
180 | dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); | |
181 | return -EIO; /* No ACK */ | |
182 | } | |
183 | ||
184 | dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); | |
185 | return 0; | |
186 | } | |
187 | ||
43309f3b | 188 | static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) |
aa11e38c DA |
189 | { |
190 | unsigned int temp = 0; | |
43309f3b | 191 | int result; |
aa11e38c DA |
192 | |
193 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
194 | ||
195 | /* Enable I2C controller */ | |
43309f3b | 196 | writeb(0, i2c_imx->base + IMX_I2C_I2SR); |
aa11e38c | 197 | writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR); |
43309f3b RZ |
198 | |
199 | /* Wait controller to be stable */ | |
200 | udelay(50); | |
201 | ||
aa11e38c DA |
202 | /* Start I2C transaction */ |
203 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
204 | temp |= I2CR_MSTA; | |
205 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
43309f3b RZ |
206 | result = i2c_imx_bus_busy(i2c_imx, 1); |
207 | if (result) | |
208 | return result; | |
209 | i2c_imx->stopped = 0; | |
210 | ||
aa11e38c DA |
211 | temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; |
212 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
43309f3b | 213 | return result; |
aa11e38c DA |
214 | } |
215 | ||
216 | static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) | |
217 | { | |
218 | unsigned int temp = 0; | |
219 | ||
43309f3b RZ |
220 | if (!i2c_imx->stopped) { |
221 | /* Stop I2C transaction */ | |
222 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
223 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
224 | temp &= ~(I2CR_MSTA | I2CR_MTX); | |
225 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
226 | i2c_imx->stopped = 1; | |
227 | } | |
aa11e38c DA |
228 | /* |
229 | * This delay caused by an i.MXL hardware bug. | |
230 | * If no (or too short) delay, no "STOP" bit will be generated. | |
231 | */ | |
65de394d | 232 | udelay(i2c_imx->disable_delay); |
43309f3b RZ |
233 | |
234 | if (!i2c_imx->stopped) | |
235 | i2c_imx_bus_busy(i2c_imx, 0); | |
236 | ||
aa11e38c DA |
237 | /* Disable I2C controller */ |
238 | writeb(0, i2c_imx->base + IMX_I2C_I2CR); | |
239 | } | |
240 | ||
241 | static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, | |
242 | unsigned int rate) | |
243 | { | |
244 | unsigned int i2c_clk_rate; | |
245 | unsigned int div; | |
246 | int i; | |
247 | ||
248 | /* Divider value calculation */ | |
249 | i2c_clk_rate = clk_get_rate(i2c_imx->clk); | |
250 | div = (i2c_clk_rate + rate - 1) / rate; | |
251 | if (div < i2c_clk_div[0][0]) | |
252 | i = 0; | |
253 | else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) | |
254 | i = ARRAY_SIZE(i2c_clk_div) - 1; | |
255 | else | |
256 | for (i = 0; i2c_clk_div[i][0] < div; i++); | |
257 | ||
258 | /* Write divider value to register */ | |
259 | writeb(i2c_clk_div[i][1], i2c_imx->base + IMX_I2C_IFDR); | |
260 | ||
261 | /* | |
262 | * There dummy delay is calculated. | |
263 | * It should be about one I2C clock period long. | |
264 | * This delay is used in I2C bus disable function | |
265 | * to fix chip hardware bug. | |
266 | */ | |
65de394d | 267 | i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0] |
aa11e38c DA |
268 | + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); |
269 | ||
270 | /* dev_dbg() can't be used, because adapter is not yet registered */ | |
271 | #ifdef CONFIG_I2C_DEBUG_BUS | |
272 | printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n", | |
273 | __func__, i2c_clk_rate, div); | |
274 | printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n", | |
275 | __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]); | |
276 | #endif | |
277 | } | |
278 | ||
279 | static irqreturn_t i2c_imx_isr(int irq, void *dev_id) | |
280 | { | |
281 | struct imx_i2c_struct *i2c_imx = dev_id; | |
282 | unsigned int temp; | |
283 | ||
284 | temp = readb(i2c_imx->base + IMX_I2C_I2SR); | |
285 | if (temp & I2SR_IIF) { | |
286 | /* save status register */ | |
287 | i2c_imx->i2csr = temp; | |
288 | temp &= ~I2SR_IIF; | |
289 | writeb(temp, i2c_imx->base + IMX_I2C_I2SR); | |
290 | wake_up_interruptible(&i2c_imx->queue); | |
291 | return IRQ_HANDLED; | |
292 | } | |
293 | ||
294 | return IRQ_NONE; | |
295 | } | |
296 | ||
297 | static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
298 | { | |
299 | int i, result; | |
300 | ||
301 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", | |
302 | __func__, msgs->addr << 1); | |
303 | ||
304 | /* write slave address */ | |
305 | writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR); | |
306 | result = i2c_imx_trx_complete(i2c_imx); | |
307 | if (result) | |
308 | return result; | |
309 | result = i2c_imx_acked(i2c_imx); | |
310 | if (result) | |
311 | return result; | |
312 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); | |
313 | ||
314 | /* write data */ | |
315 | for (i = 0; i < msgs->len; i++) { | |
316 | dev_dbg(&i2c_imx->adapter.dev, | |
317 | "<%s> write byte: B%d=0x%X\n", | |
318 | __func__, i, msgs->buf[i]); | |
319 | writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR); | |
320 | result = i2c_imx_trx_complete(i2c_imx); | |
321 | if (result) | |
322 | return result; | |
323 | result = i2c_imx_acked(i2c_imx); | |
324 | if (result) | |
325 | return result; | |
326 | } | |
327 | return 0; | |
328 | } | |
329 | ||
330 | static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
331 | { | |
332 | int i, result; | |
333 | unsigned int temp; | |
334 | ||
335 | dev_dbg(&i2c_imx->adapter.dev, | |
336 | "<%s> write slave address: addr=0x%x\n", | |
337 | __func__, (msgs->addr << 1) | 0x01); | |
338 | ||
339 | /* write slave address */ | |
340 | writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR); | |
341 | result = i2c_imx_trx_complete(i2c_imx); | |
342 | if (result) | |
343 | return result; | |
344 | result = i2c_imx_acked(i2c_imx); | |
345 | if (result) | |
346 | return result; | |
347 | ||
348 | dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); | |
349 | ||
350 | /* setup bus to read data */ | |
351 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
352 | temp &= ~I2CR_MTX; | |
353 | if (msgs->len - 1) | |
354 | temp &= ~I2CR_TXAK; | |
355 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
356 | readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */ | |
357 | ||
358 | dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); | |
359 | ||
360 | /* read data */ | |
361 | for (i = 0; i < msgs->len; i++) { | |
362 | result = i2c_imx_trx_complete(i2c_imx); | |
363 | if (result) | |
364 | return result; | |
365 | if (i == (msgs->len - 1)) { | |
43309f3b RZ |
366 | /* It must generate STOP before read I2DR to prevent |
367 | controller from generating another clock cycle */ | |
aa11e38c DA |
368 | dev_dbg(&i2c_imx->adapter.dev, |
369 | "<%s> clear MSTA\n", __func__); | |
370 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
43309f3b | 371 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
aa11e38c | 372 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); |
43309f3b RZ |
373 | i2c_imx_bus_busy(i2c_imx, 0); |
374 | i2c_imx->stopped = 1; | |
aa11e38c DA |
375 | } else if (i == (msgs->len - 2)) { |
376 | dev_dbg(&i2c_imx->adapter.dev, | |
377 | "<%s> set TXAK\n", __func__); | |
378 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
379 | temp |= I2CR_TXAK; | |
380 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
381 | } | |
382 | msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR); | |
383 | dev_dbg(&i2c_imx->adapter.dev, | |
384 | "<%s> read byte: B%d=0x%X\n", | |
385 | __func__, i, msgs->buf[i]); | |
386 | } | |
387 | return 0; | |
388 | } | |
389 | ||
390 | static int i2c_imx_xfer(struct i2c_adapter *adapter, | |
391 | struct i2c_msg *msgs, int num) | |
392 | { | |
393 | unsigned int i, temp; | |
394 | int result; | |
395 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); | |
396 | ||
397 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
398 | ||
43309f3b RZ |
399 | /* Start I2C transfer */ |
400 | result = i2c_imx_start(i2c_imx); | |
aa11e38c DA |
401 | if (result) |
402 | goto fail0; | |
403 | ||
aa11e38c DA |
404 | /* read/write data */ |
405 | for (i = 0; i < num; i++) { | |
406 | if (i) { | |
407 | dev_dbg(&i2c_imx->adapter.dev, | |
408 | "<%s> repeated start\n", __func__); | |
409 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
410 | temp |= I2CR_RSTA; | |
411 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
43309f3b RZ |
412 | result = i2c_imx_bus_busy(i2c_imx, 1); |
413 | if (result) | |
414 | goto fail0; | |
aa11e38c DA |
415 | } |
416 | dev_dbg(&i2c_imx->adapter.dev, | |
417 | "<%s> transfer message: %d\n", __func__, i); | |
418 | /* write/read data */ | |
419 | #ifdef CONFIG_I2C_DEBUG_BUS | |
420 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
421 | dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " | |
422 | "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, | |
423 | (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), | |
424 | (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), | |
425 | (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); | |
426 | temp = readb(i2c_imx->base + IMX_I2C_I2SR); | |
427 | dev_dbg(&i2c_imx->adapter.dev, | |
428 | "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " | |
429 | "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, | |
430 | (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), | |
431 | (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), | |
432 | (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), | |
433 | (temp & I2SR_RXAK ? 1 : 0)); | |
434 | #endif | |
435 | if (msgs[i].flags & I2C_M_RD) | |
436 | result = i2c_imx_read(i2c_imx, &msgs[i]); | |
437 | else | |
438 | result = i2c_imx_write(i2c_imx, &msgs[i]); | |
439 | } | |
440 | ||
441 | fail0: | |
442 | /* Stop I2C transfer */ | |
443 | i2c_imx_stop(i2c_imx); | |
444 | ||
445 | dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, | |
446 | (result < 0) ? "error" : "success msg", | |
447 | (result < 0) ? result : num); | |
448 | return (result < 0) ? result : num; | |
449 | } | |
450 | ||
451 | static u32 i2c_imx_func(struct i2c_adapter *adapter) | |
452 | { | |
453 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
454 | } | |
455 | ||
456 | static struct i2c_algorithm i2c_imx_algo = { | |
457 | .master_xfer = i2c_imx_xfer, | |
458 | .functionality = i2c_imx_func, | |
459 | }; | |
460 | ||
461 | static int __init i2c_imx_probe(struct platform_device *pdev) | |
462 | { | |
463 | struct imx_i2c_struct *i2c_imx; | |
464 | struct resource *res; | |
465 | struct imxi2c_platform_data *pdata; | |
466 | void __iomem *base; | |
467 | resource_size_t res_size; | |
468 | int irq; | |
469 | int ret; | |
470 | ||
471 | dev_dbg(&pdev->dev, "<%s>\n", __func__); | |
472 | ||
473 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
474 | if (!res) { | |
475 | dev_err(&pdev->dev, "can't get device resources\n"); | |
476 | return -ENOENT; | |
477 | } | |
478 | irq = platform_get_irq(pdev, 0); | |
479 | if (irq < 0) { | |
480 | dev_err(&pdev->dev, "can't get irq number\n"); | |
481 | return -ENOENT; | |
482 | } | |
483 | ||
484 | pdata = pdev->dev.platform_data; | |
485 | ||
486 | if (pdata && pdata->init) { | |
487 | ret = pdata->init(&pdev->dev); | |
488 | if (ret) | |
489 | return ret; | |
490 | } | |
491 | ||
492 | res_size = resource_size(res); | |
493 | base = ioremap(res->start, res_size); | |
494 | if (!base) { | |
495 | dev_err(&pdev->dev, "ioremap failed\n"); | |
496 | ret = -EIO; | |
497 | goto fail0; | |
498 | } | |
499 | ||
500 | i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL); | |
501 | if (!i2c_imx) { | |
502 | dev_err(&pdev->dev, "can't allocate interface\n"); | |
503 | ret = -ENOMEM; | |
504 | goto fail1; | |
505 | } | |
506 | ||
309c18d2 DA |
507 | if (!request_mem_region(res->start, res_size, DRIVER_NAME)) { |
508 | ret = -EBUSY; | |
509 | goto fail2; | |
510 | } | |
511 | ||
aa11e38c DA |
512 | /* Setup i2c_imx driver structure */ |
513 | strcpy(i2c_imx->adapter.name, pdev->name); | |
514 | i2c_imx->adapter.owner = THIS_MODULE; | |
515 | i2c_imx->adapter.algo = &i2c_imx_algo; | |
516 | i2c_imx->adapter.dev.parent = &pdev->dev; | |
517 | i2c_imx->adapter.nr = pdev->id; | |
518 | i2c_imx->irq = irq; | |
519 | i2c_imx->base = base; | |
520 | i2c_imx->res = res; | |
521 | ||
522 | /* Get I2C clock */ | |
523 | i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk"); | |
524 | if (IS_ERR(i2c_imx->clk)) { | |
525 | ret = PTR_ERR(i2c_imx->clk); | |
526 | dev_err(&pdev->dev, "can't get I2C clock\n"); | |
309c18d2 | 527 | goto fail3; |
aa11e38c DA |
528 | } |
529 | clk_enable(i2c_imx->clk); | |
530 | ||
531 | /* Request IRQ */ | |
532 | ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx); | |
533 | if (ret) { | |
534 | dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq); | |
309c18d2 | 535 | goto fail4; |
aa11e38c DA |
536 | } |
537 | ||
538 | /* Init queue */ | |
539 | init_waitqueue_head(&i2c_imx->queue); | |
540 | ||
541 | /* Set up adapter data */ | |
542 | i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); | |
543 | ||
544 | /* Set up clock divider */ | |
545 | if (pdata && pdata->bitrate) | |
546 | i2c_imx_set_clk(i2c_imx, pdata->bitrate); | |
547 | else | |
548 | i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE); | |
549 | ||
550 | /* Set up chip registers to defaults */ | |
551 | writeb(0, i2c_imx->base + IMX_I2C_I2CR); | |
552 | writeb(0, i2c_imx->base + IMX_I2C_I2SR); | |
553 | ||
554 | /* Add I2C adapter */ | |
555 | ret = i2c_add_numbered_adapter(&i2c_imx->adapter); | |
556 | if (ret < 0) { | |
557 | dev_err(&pdev->dev, "registration failed\n"); | |
309c18d2 | 558 | goto fail5; |
aa11e38c DA |
559 | } |
560 | ||
561 | /* Set up platform driver data */ | |
562 | platform_set_drvdata(pdev, i2c_imx); | |
563 | ||
564 | dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq); | |
565 | dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", | |
566 | i2c_imx->res->start, i2c_imx->res->end); | |
567 | dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n", | |
568 | res_size, i2c_imx->res->start); | |
569 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", | |
570 | i2c_imx->adapter.name); | |
571 | dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); | |
572 | ||
573 | return 0; /* Return OK */ | |
574 | ||
309c18d2 | 575 | fail5: |
aa11e38c | 576 | free_irq(i2c_imx->irq, i2c_imx); |
309c18d2 | 577 | fail4: |
aa11e38c DA |
578 | clk_disable(i2c_imx->clk); |
579 | clk_put(i2c_imx->clk); | |
309c18d2 DA |
580 | fail3: |
581 | release_mem_region(i2c_imx->res->start, resource_size(res)); | |
aa11e38c DA |
582 | fail2: |
583 | kfree(i2c_imx); | |
584 | fail1: | |
585 | iounmap(base); | |
586 | fail0: | |
587 | if (pdata && pdata->exit) | |
588 | pdata->exit(&pdev->dev); | |
589 | return ret; /* Return error number */ | |
590 | } | |
591 | ||
592 | static int __exit i2c_imx_remove(struct platform_device *pdev) | |
593 | { | |
594 | struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); | |
595 | struct imxi2c_platform_data *pdata = pdev->dev.platform_data; | |
596 | ||
597 | /* remove adapter */ | |
598 | dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); | |
599 | i2c_del_adapter(&i2c_imx->adapter); | |
600 | platform_set_drvdata(pdev, NULL); | |
601 | ||
602 | /* free interrupt */ | |
603 | free_irq(i2c_imx->irq, i2c_imx); | |
604 | ||
605 | /* setup chip registers to defaults */ | |
606 | writeb(0, i2c_imx->base + IMX_I2C_IADR); | |
607 | writeb(0, i2c_imx->base + IMX_I2C_IFDR); | |
608 | writeb(0, i2c_imx->base + IMX_I2C_I2CR); | |
609 | writeb(0, i2c_imx->base + IMX_I2C_I2SR); | |
610 | ||
611 | /* Shut down hardware */ | |
612 | if (pdata && pdata->exit) | |
613 | pdata->exit(&pdev->dev); | |
614 | ||
615 | /* Disable I2C clock */ | |
616 | clk_disable(i2c_imx->clk); | |
617 | clk_put(i2c_imx->clk); | |
618 | ||
309c18d2 | 619 | release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res)); |
aa11e38c DA |
620 | iounmap(i2c_imx->base); |
621 | kfree(i2c_imx); | |
622 | return 0; | |
623 | } | |
624 | ||
625 | static struct platform_driver i2c_imx_driver = { | |
626 | .probe = i2c_imx_probe, | |
627 | .remove = __exit_p(i2c_imx_remove), | |
628 | .driver = { | |
629 | .name = DRIVER_NAME, | |
630 | .owner = THIS_MODULE, | |
631 | } | |
632 | }; | |
633 | ||
634 | static int __init i2c_adap_imx_init(void) | |
635 | { | |
636 | return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe); | |
637 | } | |
5d3f3331 | 638 | subsys_initcall(i2c_adap_imx_init); |
aa11e38c DA |
639 | |
640 | static void __exit i2c_adap_imx_exit(void) | |
641 | { | |
642 | platform_driver_unregister(&i2c_imx_driver); | |
643 | } | |
aa11e38c DA |
644 | module_exit(i2c_adap_imx_exit); |
645 | ||
646 | MODULE_LICENSE("GPL"); | |
647 | MODULE_AUTHOR("Darius Augulis"); | |
648 | MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); | |
649 | MODULE_ALIAS("platform:" DRIVER_NAME); |