[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-imx.c

/*
 *	Copyright (C) 2002 Motorola GSG-China
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version 2
 *	of the License, or (at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307,
 *	USA.
 *
 * Author:
 *	Darius Augulis, Teltonika Inc.
 *
 * Desc.:
 *	Implementation of I2C Adapter/Algorithm Driver
 *	for I2C Bus integrated in Freescale i.MX/MXC processors
 *
 *	Derived from Motorola GSG China I2C example driver
 *
 *	Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
 *	Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
 *	Copyright (C) 2007 RightHand Technologies, Inc.
 *	Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
 *
 */

/** Includes *******************************************************************
*******************************************************************************/

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_i2c.h>
#include <linux/pinctrl/consumer.h>

#include <mach/hardware.h>
#include <linux/platform_data/i2c-imx.h>

/** Defines ********************************************************************
*******************************************************************************/

/* This will be the driver name the kernel reports */
#define DRIVER_NAME "imx-i2c"

/* Default value */
#define IMX_I2C_BIT_RATE	100000	/* 100kHz */

/* IMX I2C registers */
#define IMX_I2C_IADR	0x00	/* i2c slave address */
#define IMX_I2C_IFDR	0x04	/* i2c frequency divider */
#define IMX_I2C_I2CR	0x08	/* i2c control */
#define IMX_I2C_I2SR	0x0C	/* i2c status */
#define IMX_I2C_I2DR	0x10	/* i2c transfer data */

/* Bits of IMX I2C registers */
#define I2SR_RXAK	0x01
#define I2SR_IIF	0x02
#define I2SR_SRW	0x04
#define I2SR_IAL	0x10
#define I2SR_IBB	0x20
#define I2SR_IAAS	0x40
#define I2SR_ICF	0x80
#define I2CR_RSTA	0x04
#define I2CR_TXAK	0x08
#define I2CR_MTX	0x10
#define I2CR_MSTA	0x20
#define I2CR_IIEN	0x40
#define I2CR_IEN	0x80

/** Variables ******************************************************************
*******************************************************************************/

/*
 * sorted list of clock divider, register value pairs
 * taken from table 26-5, p.26-9, Freescale i.MX
 * Integrated Portable System Processor Reference Manual
 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 *
 * Duplicated divider values removed from list
 */

static u16 __initdata i2c_clk_div[50][2] = {
	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
	{ 42,	0x03 }, { 44,	0x27 },	{ 48,	0x28 }, { 52,	0x05 },
	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A },	{ 72,	0x2B },
	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
	{ 192,	0x31 },	{ 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
	{ 288,	0x10 }, { 320,	0x34 },	{ 384,	0x35 }, { 448,	0x36 },
	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 },	{ 640,	0x38 },
	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
	{ 3072,	0x1E }, { 3840,	0x1F }
};

struct imx_i2c_struct {
	struct i2c_adapter	adapter;
	struct clk		*clk;
	void __iomem		*base;
	wait_queue_head_t	queue;
	unsigned long		i2csr;
	unsigned int 		disable_delay;
	int			stopped;
	unsigned int		ifdr; /* IMX_I2C_IFDR */
};

static const struct of_device_id i2c_imx_dt_ids[] = {
	{ .compatible = "fsl,imx1-i2c", },
	{ /* sentinel */ }
};

/** Functions for IMX I2C adapter driver ***************************************
*******************************************************************************/

static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
{
	unsigned long orig_jiffies = jiffies;
	unsigned int temp;

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	while (1) {
		temp = readb(i2c_imx->base + IMX_I2C_I2SR);
		if (for_busy && (temp & I2SR_IBB))
			break;
		if (!for_busy && !(temp & I2SR_IBB))
			break;
		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> I2C bus is busy\n", __func__);
			return -ETIMEDOUT;
		}
		schedule();
	}

	return 0;
}

static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
{
	wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);

	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
		dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
		return -ETIMEDOUT;
	}
	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
	i2c_imx->i2csr = 0;
	return 0;
}

static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
{
	if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
		dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
		return -EIO;  /* No ACK */
	}

	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
	return 0;
}

static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
{
	unsigned int temp = 0;
	int result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	clk_prepare_enable(i2c_imx->clk);
	writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
	/* Enable I2C controller */
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);

	/* Wait controller to be stable */
	udelay(50);

	/* Start I2C transaction */
	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	temp |= I2CR_MSTA;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	result = i2c_imx_bus_busy(i2c_imx, 1);
	if (result)
		return result;
	i2c_imx->stopped = 0;

	temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	return result;
}

static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
{
	unsigned int temp = 0;

	if (!i2c_imx->stopped) {
		/* Stop I2C transaction */
		dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
		temp = readb(i2c_imx->base + IMX_I2C_I2CR);
		temp &= ~(I2CR_MSTA | I2CR_MTX);
		writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	}
	if (cpu_is_mx1()) {
		/*
		 * This delay caused by an i.MXL hardware bug.
		 * If no (or too short) delay, no "STOP" bit will be generated.
		 */
		udelay(i2c_imx->disable_delay);
	}

	if (!i2c_imx->stopped) {
		i2c_imx_bus_busy(i2c_imx, 0);
		i2c_imx->stopped = 1;
	}

	/* Disable I2C controller */
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	clk_disable_unprepare(i2c_imx->clk);
}

static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
							unsigned int rate)
{
	unsigned int i2c_clk_rate;
	unsigned int div;
	int i;

	/* Divider value calculation */
	i2c_clk_rate = clk_get_rate(i2c_imx->clk);
	div = (i2c_clk_rate + rate - 1) / rate;
	if (div < i2c_clk_div[0][0])
		i = 0;
	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
		i = ARRAY_SIZE(i2c_clk_div) - 1;
	else
		for (i = 0; i2c_clk_div[i][0] < div; i++);

	/* Store divider value */
	i2c_imx->ifdr = i2c_clk_div[i][1];

	/*
	 * There dummy delay is calculated.
	 * It should be about one I2C clock period long.
	 * This delay is used in I2C bus disable function
	 * to fix chip hardware bug.
	 */
	i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
		+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);

	/* dev_dbg() can't be used, because adapter is not yet registered */
#ifdef CONFIG_I2C_DEBUG_BUS
	dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
		__func__, i2c_clk_rate, div);
	dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
		__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
#endif
}

static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
{
	struct imx_i2c_struct *i2c_imx = dev_id;
	unsigned int temp;

	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	if (temp & I2SR_IIF) {
		/* save status register */
		i2c_imx->i2csr = temp;
		temp &= ~I2SR_IIF;
		writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
		wake_up(&i2c_imx->queue);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
{
	int i, result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
		__func__, msgs->addr << 1);

	/* write slave address */
	writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
	result = i2c_imx_trx_complete(i2c_imx);
	if (result)
		return result;
	result = i2c_imx_acked(i2c_imx);
	if (result)
		return result;
	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);

	/* write data */
	for (i = 0; i < msgs->len; i++) {
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> write byte: B%d=0x%X\n",
			__func__, i, msgs->buf[i]);
		writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
		result = i2c_imx_trx_complete(i2c_imx);
		if (result)
			return result;
		result = i2c_imx_acked(i2c_imx);
		if (result)
			return result;
	}
	return 0;
}

static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
{
	int i, result;
	unsigned int temp;

	dev_dbg(&i2c_imx->adapter.dev,
		"<%s> write slave address: addr=0x%x\n",
		__func__, (msgs->addr << 1) | 0x01);

	/* write slave address */
	writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
	result = i2c_imx_trx_complete(i2c_imx);
	if (result)
		return result;
	result = i2c_imx_acked(i2c_imx);
	if (result)
		return result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);

	/* setup bus to read data */
	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	temp &= ~I2CR_MTX;
	if (msgs->len - 1)
		temp &= ~I2CR_TXAK;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */

	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);

	/* read data */
	for (i = 0; i < msgs->len; i++) {
		result = i2c_imx_trx_complete(i2c_imx);
		if (result)
			return result;
		if (i == (msgs->len - 1)) {
			/* It must generate STOP before read I2DR to prevent
			   controller from generating another clock cycle */
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> clear MSTA\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp &= ~(I2CR_MSTA | I2CR_MTX);
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
			i2c_imx_bus_busy(i2c_imx, 0);
			i2c_imx->stopped = 1;
		} else if (i == (msgs->len - 2)) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> set TXAK\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp |= I2CR_TXAK;
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
		}
		msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> read byte: B%d=0x%X\n",
			__func__, i, msgs->buf[i]);
	}
	return 0;
}

static int i2c_imx_xfer(struct i2c_adapter *adapter,
						struct i2c_msg *msgs, int num)
{
	unsigned int i, temp;
	int result;
	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	/* Start I2C transfer */
	result = i2c_imx_start(i2c_imx);
	if (result)
		goto fail0;

	/* read/write data */
	for (i = 0; i < num; i++) {
		if (i) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> repeated start\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp |= I2CR_RSTA;
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
			result =  i2c_imx_bus_busy(i2c_imx, 1);
			if (result)
				goto fail0;
		}
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> transfer message: %d\n", __func__, i);
		/* write/read data */
#ifdef CONFIG_I2C_DEBUG_BUS
		temp = readb(i2c_imx->base + IMX_I2C_I2CR);
		dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
			"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
			(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
			(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
			(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
		temp = readb(i2c_imx->base + IMX_I2C_I2SR);
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
			"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
			(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
			(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
			(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
			(temp & I2SR_RXAK ? 1 : 0));
#endif
		if (msgs[i].flags & I2C_M_RD)
			result = i2c_imx_read(i2c_imx, &msgs[i]);
		else
			result = i2c_imx_write(i2c_imx, &msgs[i]);
		if (result)
			goto fail0;
	}

fail0:
	/* Stop I2C transfer */
	i2c_imx_stop(i2c_imx);

	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
		(result < 0) ? "error" : "success msg",
			(result < 0) ? result : num);
	return (result < 0) ? result : num;
}

static u32 i2c_imx_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm i2c_imx_algo = {
	.master_xfer	= i2c_imx_xfer,
	.functionality	= i2c_imx_func,
};

static int __init i2c_imx_probe(struct platform_device *pdev)
{
	struct imx_i2c_struct *i2c_imx;
	struct resource *res;
	struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
	struct pinctrl *pinctrl;
	void __iomem *base;
	int irq, ret;
	u32 bitrate;

	dev_dbg(&pdev->dev, "<%s>\n", __func__);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "can't get device resources\n");
		return -ENOENT;
	}
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "can't get irq number\n");
		return -ENOENT;
	}

	base = devm_request_and_ioremap(&pdev->dev, res);
	if (!base)
		return -EBUSY;

	i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
				GFP_KERNEL);
	if (!i2c_imx) {
		dev_err(&pdev->dev, "can't allocate interface\n");
		return -ENOMEM;
	}

	/* Setup i2c_imx driver structure */
	strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
	i2c_imx->adapter.owner		= THIS_MODULE;
	i2c_imx->adapter.algo		= &i2c_imx_algo;
	i2c_imx->adapter.dev.parent	= &pdev->dev;
	i2c_imx->adapter.nr 		= pdev->id;
	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
	i2c_imx->base			= base;

	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	if (IS_ERR(pinctrl)) {
		dev_err(&pdev->dev, "can't get/select pinctrl\n");
		return PTR_ERR(pinctrl);
	}

	/* Get I2C clock */
	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2c_imx->clk)) {
		dev_err(&pdev->dev, "can't get I2C clock\n");
		return PTR_ERR(i2c_imx->clk);
	}

	/* Request IRQ */
	ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
				pdev->name, i2c_imx);
	if (ret) {
		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
		return ret;
	}

	/* Init queue */
	init_waitqueue_head(&i2c_imx->queue);

	/* Set up adapter data */
	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);

	/* Set up clock divider */
	bitrate = IMX_I2C_BIT_RATE;
	ret = of_property_read_u32(pdev->dev.of_node,
				   "clock-frequency", &bitrate);
	if (ret < 0 && pdata && pdata->bitrate)
		bitrate = pdata->bitrate;
	i2c_imx_set_clk(i2c_imx, bitrate);

	/* Set up chip registers to defaults */
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);

	/* Add I2C adapter */
	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
	if (ret < 0) {
		dev_err(&pdev->dev, "registration failed\n");
		return ret;
	}

	of_i2c_register_devices(&i2c_imx->adapter);

	/* Set up platform driver data */
	platform_set_drvdata(pdev, i2c_imx);

	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
	dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
		res->start, res->end);
	dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
		resource_size(res), res->start);
	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
		i2c_imx->adapter.name);
	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");

	return 0;   /* Return OK */
}

static int __exit i2c_imx_remove(struct platform_device *pdev)
{
	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);

	/* remove adapter */
	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
	i2c_del_adapter(&i2c_imx->adapter);
	platform_set_drvdata(pdev, NULL);

	/* setup chip registers to defaults */
	writeb(0, i2c_imx->base + IMX_I2C_IADR);
	writeb(0, i2c_imx->base + IMX_I2C_IFDR);
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);

	return 0;
}

static struct platform_driver i2c_imx_driver = {
	.remove		= __exit_p(i2c_imx_remove),
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = i2c_imx_dt_ids,
	}
};

static int __init i2c_adap_imx_init(void)
{
	return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
}
subsys_initcall(i2c_adap_imx_init);

static void __exit i2c_adap_imx_exit(void)
{
	platform_driver_unregister(&i2c_imx_driver);
}
module_exit(i2c_adap_imx_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Darius Augulis");
MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
aa11e38c DA	1	/*
	2	* Copyright (C) 2002 Motorola GSG-China
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
	17	* USA.
	18	*
	19	* Author:
	20	* Darius Augulis, Teltonika Inc.
	21	*
	22	* Desc.:
	23	* Implementation of I2C Adapter/Algorithm Driver
	24	* for I2C Bus integrated in Freescale i.MX/MXC processors
	25	*
	26	* Derived from Motorola GSG China I2C example driver
	27	*
	28	* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
	29	* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
	30	* Copyright (C) 2007 RightHand Technologies, Inc.
	31	* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
	32	*
	33	*/
	34
	35	/ Includes *****************************************************************
	36	*******************************************************************************/
	37
	38	#include <linux/init.h>
	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/errno.h>
	42	#include <linux/err.h>
	43	#include <linux/interrupt.h>
	44	#include <linux/delay.h>
	45	#include <linux/i2c.h>
	46	#include <linux/io.h>
	47	#include <linux/sched.h>
	48	#include <linux/platform_device.h>
	49	#include <linux/clk.h>
5a0e3ad6	50	#include <linux/slab.h>
dfcd04b1 SG	51	#include <linux/of.h>
	52	#include <linux/of_device.h>
	53	#include <linux/of_i2c.h>
15afbc68	54	#include <linux/pinctrl/consumer.h>
aa11e38c	55
aa11e38c	56	#include <mach/hardware.h>
82906b13	57	#include <linux/platform_data/i2c-imx.h>
aa11e38c DA	58
	59	/ Defines ******************************************************************
	60	*******************************************************************************/
	61
	62	/* This will be the driver name the kernel reports */
	63	#define DRIVER_NAME "imx-i2c"
	64
	65	/* Default value */
	66	#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
	67
	68	/* IMX I2C registers */
	69	#define IMX_I2C_IADR 0x00 /* i2c slave address */
	70	#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
	71	#define IMX_I2C_I2CR 0x08 /* i2c control */
	72	#define IMX_I2C_I2SR 0x0C /* i2c status */
	73	#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
	74
	75	/* Bits of IMX I2C registers */
	76	#define I2SR_RXAK 0x01
	77	#define I2SR_IIF 0x02
	78	#define I2SR_SRW 0x04
	79	#define I2SR_IAL 0x10
	80	#define I2SR_IBB 0x20
	81	#define I2SR_IAAS 0x40
	82	#define I2SR_ICF 0x80
	83	#define I2CR_RSTA 0x04
	84	#define I2CR_TXAK 0x08
	85	#define I2CR_MTX 0x10
	86	#define I2CR_MSTA 0x20
	87	#define I2CR_IIEN 0x40
	88	#define I2CR_IEN 0x80
	89
	90	/ Variables ****************************************************************
	91	*******************************************************************************/
	92
aa11e38c DA	93	/*
	94	* sorted list of clock divider, register value pairs
	95	* taken from table 26-5, p.26-9, Freescale i.MX
	96	* Integrated Portable System Processor Reference Manual
	97	* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
	98	*
	99	* Duplicated divider values removed from list
	100	*/
	101
	102	static u16 __initdata i2c_clk_div[50][2] = {
	103	{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
	104	{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
	105	{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
	106	{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
	107	{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
	108	{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
	109	{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
	110	{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
	111	{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
	112	{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
	113	{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
	114	{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
	115	{ 3072, 0x1E }, { 3840, 0x1F }
	116	};
	117
	118	struct imx_i2c_struct {
	119	struct i2c_adapter adapter;
aa11e38c DA	120	struct clk *clk;
aa11e38c DA	121	void __iomem *base;
aa11e38c DA	122	wait_queue_head_t queue;
aa11e38c DA	123	unsigned long i2csr;
65de394d	124	unsigned int disable_delay;
43309f3b	125	int stopped;
db3a3d4e	126	unsigned int ifdr; /* IMX_I2C_IFDR */
aa11e38c DA	127	};
aa11e38c DA	128
dfcd04b1 SG	129	static const struct of_device_id i2c_imx_dt_ids[] = {
	130	{ .compatible = "fsl,imx1-i2c", },
	131	{ /* sentinel */ }
	132	};
	133
aa11e38c DA	134	/ Functions for IMX I2C adapter driver *************************************
	135	*******************************************************************************/
	136
43309f3b	137	static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
aa11e38c DA	138	{
aa11e38c DA	139	unsigned long orig_jiffies = jiffies;
43309f3b	140	unsigned int temp;
aa11e38c DA	141
	142	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	143
43309f3b RZ	144	while (1) {
	145	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	146	if (for_busy && (temp & I2SR_IBB))
	147	break;
	148	if (!for_busy && !(temp & I2SR_IBB))
	149	break;
da9c99fc	150	if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
aa11e38c DA	151	dev_dbg(&i2c_imx->adapter.dev,
aa11e38c DA	152	"<%s> I2C bus is busy\n", __func__);
da9c99fc	153	return -ETIMEDOUT;
aa11e38c DA	154	}
	155	schedule();
	156	}
	157
	158	return 0;
	159	}
	160
	161	static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
	162	{
e39428d5	163	wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
aa11e38c	164
e39428d5	165	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
aa11e38c DA	166	dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
	167	return -ETIMEDOUT;
	168	}
	169	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
	170	i2c_imx->i2csr = 0;
	171	return 0;
	172	}
	173
	174	static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
	175	{
	176	if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
	177	dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
	178	return -EIO; /* No ACK */
	179	}
	180
	181	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
	182	return 0;
	183	}
	184
43309f3b	185	static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
aa11e38c DA	186	{
aa11e38c DA	187	unsigned int temp = 0;
43309f3b	188	int result;
aa11e38c DA	189
	190	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	191
83914337	192	clk_prepare_enable(i2c_imx->clk);
db3a3d4e	193	writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
aa11e38c	194	/* Enable I2C controller */
43309f3b	195	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
aa11e38c	196	writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	197
	198	/* Wait controller to be stable */
	199	udelay(50);
	200
aa11e38c DA	201	/* Start I2C transaction */
	202	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	203	temp \|= I2CR_MSTA;
	204	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	205	result = i2c_imx_bus_busy(i2c_imx, 1);
	206	if (result)
	207	return result;
	208	i2c_imx->stopped = 0;
	209
aa11e38c DA	210	temp \|= I2CR_IIEN \| I2CR_MTX \| I2CR_TXAK;
aa11e38c DA	211	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b	212	return result;
aa11e38c DA	213	}
	214
	215	static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
	216	{
	217	unsigned int temp = 0;
	218
43309f3b RZ	219	if (!i2c_imx->stopped) {
	220	/* Stop I2C transaction */
	221	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	222	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	223	temp &= ~(I2CR_MSTA \| I2CR_MTX);
	224	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b	225	}
a4094a76 RZ	226	if (cpu_is_mx1()) {
	227	/*
	228	* This delay caused by an i.MXL hardware bug.
	229	* If no (or too short) delay, no "STOP" bit will be generated.
	230	*/
	231	udelay(i2c_imx->disable_delay);
	232	}
43309f3b	233
a1ee06b7	234	if (!i2c_imx->stopped) {
43309f3b	235	i2c_imx_bus_busy(i2c_imx, 0);
a1ee06b7 VL	236	i2c_imx->stopped = 1;
a1ee06b7 VL	237	}
43309f3b	238
aa11e38c DA	239	/* Disable I2C controller */
aa11e38c DA	240	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
83914337	241	clk_disable_unprepare(i2c_imx->clk);
aa11e38c DA	242	}
	243
	244	static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
	245	unsigned int rate)
	246	{
	247	unsigned int i2c_clk_rate;
	248	unsigned int div;
	249	int i;
	250
	251	/* Divider value calculation */
	252	i2c_clk_rate = clk_get_rate(i2c_imx->clk);
	253	div = (i2c_clk_rate + rate - 1) / rate;
	254	if (div < i2c_clk_div[0][0])
	255	i = 0;
	256	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
	257	i = ARRAY_SIZE(i2c_clk_div) - 1;
	258	else
	259	for (i = 0; i2c_clk_div[i][0] < div; i++);
	260
db3a3d4e RZ	261	/* Store divider value */
db3a3d4e RZ	262	i2c_imx->ifdr = i2c_clk_div[i][1];
aa11e38c DA	263
	264	/*
	265	* There dummy delay is calculated.
	266	* It should be about one I2C clock period long.
	267	* This delay is used in I2C bus disable function
	268	* to fix chip hardware bug.
	269	*/
65de394d	270	i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
aa11e38c DA	271	+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
	272
	273	/* dev_dbg() can't be used, because adapter is not yet registered */
	274	#ifdef CONFIG_I2C_DEBUG_BUS
002f002d	275	dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
aa11e38c	276	__func__, i2c_clk_rate, div);
002f002d	277	dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
aa11e38c DA	278	__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
	279	#endif
	280	}
	281
	282	static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
	283	{
	284	struct imx_i2c_struct *i2c_imx = dev_id;
	285	unsigned int temp;
	286
	287	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	288	if (temp & I2SR_IIF) {
	289	/* save status register */
	290	i2c_imx->i2csr = temp;
	291	temp &= ~I2SR_IIF;
	292	writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
e39428d5	293	wake_up(&i2c_imx->queue);
aa11e38c DA	294	return IRQ_HANDLED;
	295	}
	296
	297	return IRQ_NONE;
	298	}
	299
	300	static int i2c_imx_write(struct imx_i2c_struct i2c_imx, struct i2c_msg msgs)
	301	{
	302	int i, result;
	303
	304	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
	305	__func__, msgs->addr << 1);
	306
	307	/* write slave address */
	308	writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
	309	result = i2c_imx_trx_complete(i2c_imx);
	310	if (result)
	311	return result;
	312	result = i2c_imx_acked(i2c_imx);
	313	if (result)
	314	return result;
	315	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
	316
	317	/* write data */
	318	for (i = 0; i < msgs->len; i++) {
	319	dev_dbg(&i2c_imx->adapter.dev,
	320	"<%s> write byte: B%d=0x%X\n",
	321	__func__, i, msgs->buf[i]);
	322	writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
	323	result = i2c_imx_trx_complete(i2c_imx);
	324	if (result)
	325	return result;
	326	result = i2c_imx_acked(i2c_imx);
	327	if (result)
	328	return result;
	329	}
	330	return 0;
	331	}
	332
	333	static int i2c_imx_read(struct imx_i2c_struct i2c_imx, struct i2c_msg msgs)
	334	{
	335	int i, result;
	336	unsigned int temp;
	337
	338	dev_dbg(&i2c_imx->adapter.dev,
	339	"<%s> write slave address: addr=0x%x\n",
	340	__func__, (msgs->addr << 1) \| 0x01);
	341
	342	/* write slave address */
	343	writeb((msgs->addr << 1) \| 0x01, i2c_imx->base + IMX_I2C_I2DR);
	344	result = i2c_imx_trx_complete(i2c_imx);
	345	if (result)
	346	return result;
	347	result = i2c_imx_acked(i2c_imx);
	348	if (result)
	349	return result;
	350
	351	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
	352
	353	/* setup bus to read data */
	354	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	355	temp &= ~I2CR_MTX;
	356	if (msgs->len - 1)
	357	temp &= ~I2CR_TXAK;
358	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
359	readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
360
361	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
362
363	/* read data */
364	for (i = 0; i < msgs->len; i++) {
365	result = i2c_imx_trx_complete(i2c_imx);
366	if (result)
367	return result;
368	if (i == (msgs->len - 1)) {
43309f3b RZ	369	/* It must generate STOP before read I2DR to prevent
43309f3b RZ	370	controller from generating another clock cycle */
aa11e38c DA	371	dev_dbg(&i2c_imx->adapter.dev,
	372	"<%s> clear MSTA\n", __func__);
	373	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
43309f3b	374	temp &= ~(I2CR_MSTA \| I2CR_MTX);
aa11e38c	375	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	376	i2c_imx_bus_busy(i2c_imx, 0);
43309f3b RZ	377	i2c_imx->stopped = 1;
aa11e38c DA	378	} else if (i == (msgs->len - 2)) {
	379	dev_dbg(&i2c_imx->adapter.dev,
	380	"<%s> set TXAK\n", __func__);
	381	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	382	temp \|= I2CR_TXAK;
	383	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	384	}
	385	msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
	386	dev_dbg(&i2c_imx->adapter.dev,
	387	"<%s> read byte: B%d=0x%X\n",
	388	__func__, i, msgs->buf[i]);
	389	}
	390	return 0;
	391	}
	392
	393	static int i2c_imx_xfer(struct i2c_adapter *adapter,
	394	struct i2c_msg *msgs, int num)
	395	{
	396	unsigned int i, temp;
	397	int result;
	398	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
	399
	400	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	401
43309f3b RZ	402	/* Start I2C transfer */
43309f3b RZ	403	result = i2c_imx_start(i2c_imx);
aa11e38c DA	404	if (result)
	405	goto fail0;
	406
aa11e38c DA	407	/* read/write data */
	408	for (i = 0; i < num; i++) {
	409	if (i) {
	410	dev_dbg(&i2c_imx->adapter.dev,
	411	"<%s> repeated start\n", __func__);
	412	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	413	temp \|= I2CR_RSTA;
	414	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	415	result = i2c_imx_bus_busy(i2c_imx, 1);
	416	if (result)
	417	goto fail0;
aa11e38c DA	418	}
	419	dev_dbg(&i2c_imx->adapter.dev,
	420	"<%s> transfer message: %d\n", __func__, i);
	421	/* write/read data */
	422	#ifdef CONFIG_I2C_DEBUG_BUS
	423	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	424	dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
	425	"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
	426	(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
	427	(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
	428	(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
	429	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	430	dev_dbg(&i2c_imx->adapter.dev,
	431	"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
	432	"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
	433	(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
	434	(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
	435	(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
	436	(temp & I2SR_RXAK ? 1 : 0));
	437	#endif
	438	if (msgs[i].flags & I2C_M_RD)
	439	result = i2c_imx_read(i2c_imx, &msgs[i]);
	440	else
	441	result = i2c_imx_write(i2c_imx, &msgs[i]);
da9c99fc AP	442	if (result)
da9c99fc AP	443	goto fail0;
aa11e38c DA	444	}
	445
	446	fail0:
	447	/* Stop I2C transfer */
	448	i2c_imx_stop(i2c_imx);
	449
	450	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
	451	(result < 0) ? "error" : "success msg",
	452	(result < 0) ? result : num);
	453	return (result < 0) ? result : num;
	454	}
	455
	456	static u32 i2c_imx_func(struct i2c_adapter *adapter)
	457	{
	458	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	459	}
	460
	461	static struct i2c_algorithm i2c_imx_algo = {
	462	.master_xfer = i2c_imx_xfer,
	463	.functionality = i2c_imx_func,
	464	};
	465
	466	static int __init i2c_imx_probe(struct platform_device *pdev)
	467	{
	468	struct imx_i2c_struct *i2c_imx;
	469	struct resource *res;
593702c7	470	struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
15afbc68	471	struct pinctrl *pinctrl;
aa11e38c	472	void __iomem *base;
8c88ab04 WS	473	int irq, ret;
8c88ab04 WS	474	u32 bitrate;
aa11e38c DA	475
	476	dev_dbg(&pdev->dev, "<%s>\n", __func__);
	477
	478	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	479	if (!res) {
	480	dev_err(&pdev->dev, "can't get device resources\n");
	481	return -ENOENT;
	482	}
	483	irq = platform_get_irq(pdev, 0);
	484	if (irq < 0) {
	485	dev_err(&pdev->dev, "can't get irq number\n");
	486	return -ENOENT;
	487	}
	488
9f8a3e7f RZ	489	base = devm_request_and_ioremap(&pdev->dev, res);
9f8a3e7f RZ	490	if (!base)
593702c7	491	return -EBUSY;
aa11e38c	492
9f8a3e7f RZ	493	i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
9f8a3e7f RZ	494	GFP_KERNEL);
aa11e38c DA	495	if (!i2c_imx) {
aa11e38c DA	496	dev_err(&pdev->dev, "can't allocate interface\n");
9f8a3e7f	497	return -ENOMEM;
309c18d2 DA	498	}
309c18d2 DA	499
aa11e38c	500	/* Setup i2c_imx driver structure */
973c5ed4	501	strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
aa11e38c DA	502	i2c_imx->adapter.owner = THIS_MODULE;
	503	i2c_imx->adapter.algo = &i2c_imx_algo;
	504	i2c_imx->adapter.dev.parent = &pdev->dev;
	505	i2c_imx->adapter.nr = pdev->id;
dfcd04b1	506	i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
aa11e38c	507	i2c_imx->base = base;
aa11e38c	508
15afbc68 SG	509	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
15afbc68 SG	510	if (IS_ERR(pinctrl)) {
9f8a3e7f RZ	511	dev_err(&pdev->dev, "can't get/select pinctrl\n");
9f8a3e7f RZ	512	return PTR_ERR(pinctrl);
15afbc68 SG	513	}
15afbc68 SG	514
aa11e38c	515	/* Get I2C clock */
1f09c672	516	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
aa11e38c	517	if (IS_ERR(i2c_imx->clk)) {
aa11e38c	518	dev_err(&pdev->dev, "can't get I2C clock\n");
9f8a3e7f	519	return PTR_ERR(i2c_imx->clk);
aa11e38c	520	}
aa11e38c DA	521
aa11e38c DA	522	/* Request IRQ */
9f8a3e7f RZ	523	ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
9f8a3e7f RZ	524	pdev->name, i2c_imx);
aa11e38c	525	if (ret) {
9f8a3e7f RZ	526	dev_err(&pdev->dev, "can't claim irq %d\n", irq);
9f8a3e7f RZ	527	return ret;
aa11e38c DA	528	}
	529
	530	/* Init queue */
	531	init_waitqueue_head(&i2c_imx->queue);
	532
	533	/* Set up adapter data */
	534	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
	535
	536	/* Set up clock divider */
dfcd04b1 SG	537	bitrate = IMX_I2C_BIT_RATE;
	538	ret = of_property_read_u32(pdev->dev.of_node,
	539	"clock-frequency", &bitrate);
	540	if (ret < 0 && pdata && pdata->bitrate)
	541	bitrate = pdata->bitrate;
	542	i2c_imx_set_clk(i2c_imx, bitrate);
aa11e38c DA	543
	544	/* Set up chip registers to defaults */
	545	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	546	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	547
	548	/* Add I2C adapter */
	549	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
	550	if (ret < 0) {
	551	dev_err(&pdev->dev, "registration failed\n");
9f8a3e7f	552	return ret;
aa11e38c DA	553	}
aa11e38c DA	554
dfcd04b1 SG	555	of_i2c_register_devices(&i2c_imx->adapter);
dfcd04b1 SG	556
aa11e38c DA	557	/* Set up platform driver data */
	558	platform_set_drvdata(pdev, i2c_imx);
	559
9f8a3e7f	560	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
aa11e38c	561	dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
9f8a3e7f RZ	562	res->start, res->end);
	563	dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
	564	resource_size(res), res->start);
aa11e38c DA	565	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
aa11e38c DA	566	i2c_imx->adapter.name);
06d141e9	567	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
aa11e38c DA	568
aa11e38c DA	569	return 0; /* Return OK */
aa11e38c DA	570	}
	571
	572	static int __exit i2c_imx_remove(struct platform_device *pdev)
	573	{
	574	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
aa11e38c DA	575
	576	/* remove adapter */
	577	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
	578	i2c_del_adapter(&i2c_imx->adapter);
	579	platform_set_drvdata(pdev, NULL);
	580
aa11e38c DA	581	/* setup chip registers to defaults */
	582	writeb(0, i2c_imx->base + IMX_I2C_IADR);
	583	writeb(0, i2c_imx->base + IMX_I2C_IFDR);
	584	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	585	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	586
aa11e38c DA	587	return 0;
	588	}
	589
	590	static struct platform_driver i2c_imx_driver = {
aa11e38c DA	591	.remove = __exit_p(i2c_imx_remove),
	592	.driver = {
	593	.name = DRIVER_NAME,
	594	.owner = THIS_MODULE,
dfcd04b1	595	.of_match_table = i2c_imx_dt_ids,
aa11e38c DA	596	}
	597	};
	598
	599	static int __init i2c_adap_imx_init(void)
	600	{
	601	return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
	602	}
5d3f3331	603	subsys_initcall(i2c_adap_imx_init);
aa11e38c DA	604
	605	static void __exit i2c_adap_imx_exit(void)
	606	{
	607	platform_driver_unregister(&i2c_imx_driver);
	608	}
aa11e38c DA	609	module_exit(i2c_adap_imx_exit);
	610
	611	MODULE_LICENSE("GPL");
	612	MODULE_AUTHOR("Darius Augulis");
	613	MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
	614	MODULE_ALIAS("platform:" DRIVER_NAME);