[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-imx.c

/*
 *	Copyright (C) 2002 Motorola GSG-China
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version 2
 *	of the License, or (at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307,
 *	USA.
 *
 * Author:
 *	Darius Augulis, Teltonika Inc.
 *
 * Desc.:
 *	Implementation of I2C Adapter/Algorithm Driver
 *	for I2C Bus integrated in Freescale i.MX/MXC processors
 *
 *	Derived from Motorola GSG China I2C example driver
 *
 *	Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
 *	Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
 *	Copyright (C) 2007 RightHand Technologies, Inc.
 *	Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
 *
 */

/** Includes *******************************************************************
*******************************************************************************/

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_i2c.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/i2c.h>

/** Defines ********************************************************************
*******************************************************************************/

/* This will be the driver name the kernel reports */
#define DRIVER_NAME "imx-i2c"

/* Default value */
#define IMX_I2C_BIT_RATE	100000	/* 100kHz */

/* IMX I2C registers */
#define IMX_I2C_IADR	0x00	/* i2c slave address */
#define IMX_I2C_IFDR	0x04	/* i2c frequency divider */
#define IMX_I2C_I2CR	0x08	/* i2c control */
#define IMX_I2C_I2SR	0x0C	/* i2c status */
#define IMX_I2C_I2DR	0x10	/* i2c transfer data */

/* Bits of IMX I2C registers */
#define I2SR_RXAK	0x01
#define I2SR_IIF	0x02
#define I2SR_SRW	0x04
#define I2SR_IAL	0x10
#define I2SR_IBB	0x20
#define I2SR_IAAS	0x40
#define I2SR_ICF	0x80
#define I2CR_RSTA	0x04
#define I2CR_TXAK	0x08
#define I2CR_MTX	0x10
#define I2CR_MSTA	0x20
#define I2CR_IIEN	0x40
#define I2CR_IEN	0x80

/** Variables ******************************************************************
*******************************************************************************/

/*
 * sorted list of clock divider, register value pairs
 * taken from table 26-5, p.26-9, Freescale i.MX
 * Integrated Portable System Processor Reference Manual
 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 *
 * Duplicated divider values removed from list
 */

static u16 __initdata i2c_clk_div[50][2] = {
	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
	{ 42,	0x03 }, { 44,	0x27 },	{ 48,	0x28 }, { 52,	0x05 },
	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A },	{ 72,	0x2B },
	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
	{ 192,	0x31 },	{ 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
	{ 288,	0x10 }, { 320,	0x34 },	{ 384,	0x35 }, { 448,	0x36 },
	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 },	{ 640,	0x38 },
	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
	{ 3072,	0x1E }, { 3840,	0x1F }
};

struct imx_i2c_struct {
	struct i2c_adapter	adapter;
	struct resource		*res;
	struct clk		*clk;
	void __iomem		*base;
	int			irq;
	wait_queue_head_t	queue;
	unsigned long		i2csr;
	unsigned int 		disable_delay;
	int			stopped;
	unsigned int		ifdr; /* IMX_I2C_IFDR */
};

static const struct of_device_id i2c_imx_dt_ids[] = {
	{ .compatible = "fsl,imx1-i2c", },
	{ /* sentinel */ }
};

/** Functions for IMX I2C adapter driver ***************************************
*******************************************************************************/

static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
{
	unsigned long orig_jiffies = jiffies;
	unsigned int temp;

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	while (1) {
		temp = readb(i2c_imx->base + IMX_I2C_I2SR);
		if (for_busy && (temp & I2SR_IBB))
			break;
		if (!for_busy && !(temp & I2SR_IBB))
			break;
		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> I2C bus is busy\n", __func__);
			return -ETIMEDOUT;
		}
		schedule();
	}

	return 0;
}

static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
{
	wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);

	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
		dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
		return -ETIMEDOUT;
	}
	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
	i2c_imx->i2csr = 0;
	return 0;
}

static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
{
	if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
		dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
		return -EIO;  /* No ACK */
	}

	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
	return 0;
}

static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
{
	unsigned int temp = 0;
	int result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	clk_prepare_enable(i2c_imx->clk);
	writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
	/* Enable I2C controller */
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);

	/* Wait controller to be stable */
	udelay(50);

	/* Start I2C transaction */
	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	temp |= I2CR_MSTA;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	result = i2c_imx_bus_busy(i2c_imx, 1);
	if (result)
		return result;
	i2c_imx->stopped = 0;

	temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	return result;
}

static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
{
	unsigned int temp = 0;

	if (!i2c_imx->stopped) {
		/* Stop I2C transaction */
		dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
		temp = readb(i2c_imx->base + IMX_I2C_I2CR);
		temp &= ~(I2CR_MSTA | I2CR_MTX);
		writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	}
	if (cpu_is_mx1()) {
		/*
		 * This delay caused by an i.MXL hardware bug.
		 * If no (or too short) delay, no "STOP" bit will be generated.
		 */
		udelay(i2c_imx->disable_delay);
	}

	if (!i2c_imx->stopped) {
		i2c_imx_bus_busy(i2c_imx, 0);
		i2c_imx->stopped = 1;
	}

	/* Disable I2C controller */
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	clk_disable_unprepare(i2c_imx->clk);
}

static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
							unsigned int rate)
{
	unsigned int i2c_clk_rate;
	unsigned int div;
	int i;

	/* Divider value calculation */
	i2c_clk_rate = clk_get_rate(i2c_imx->clk);
	div = (i2c_clk_rate + rate - 1) / rate;
	if (div < i2c_clk_div[0][0])
		i = 0;
	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
		i = ARRAY_SIZE(i2c_clk_div) - 1;
	else
		for (i = 0; i2c_clk_div[i][0] < div; i++);

	/* Store divider value */
	i2c_imx->ifdr = i2c_clk_div[i][1];

	/*
	 * There dummy delay is calculated.
	 * It should be about one I2C clock period long.
	 * This delay is used in I2C bus disable function
	 * to fix chip hardware bug.
	 */
	i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
		+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);

	/* dev_dbg() can't be used, because adapter is not yet registered */
#ifdef CONFIG_I2C_DEBUG_BUS
	printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
		__func__, i2c_clk_rate, div);
	printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
		__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
#endif
}

static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
{
	struct imx_i2c_struct *i2c_imx = dev_id;
	unsigned int temp;

	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	if (temp & I2SR_IIF) {
		/* save status register */
		i2c_imx->i2csr = temp;
		temp &= ~I2SR_IIF;
		writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
		wake_up(&i2c_imx->queue);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
{
	int i, result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
		__func__, msgs->addr << 1);

	/* write slave address */
	writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
	result = i2c_imx_trx_complete(i2c_imx);
	if (result)
		return result;
	result = i2c_imx_acked(i2c_imx);
	if (result)
		return result;
	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);

	/* write data */
	for (i = 0; i < msgs->len; i++) {
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> write byte: B%d=0x%X\n",
			__func__, i, msgs->buf[i]);
		writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
		result = i2c_imx_trx_complete(i2c_imx);
		if (result)
			return result;
		result = i2c_imx_acked(i2c_imx);
		if (result)
			return result;
	}
	return 0;
}

static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
{
	int i, result;
	unsigned int temp;

	dev_dbg(&i2c_imx->adapter.dev,
		"<%s> write slave address: addr=0x%x\n",
		__func__, (msgs->addr << 1) | 0x01);

	/* write slave address */
	writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
	result = i2c_imx_trx_complete(i2c_imx);
	if (result)
		return result;
	result = i2c_imx_acked(i2c_imx);
	if (result)
		return result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);

	/* setup bus to read data */
	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	temp &= ~I2CR_MTX;
	if (msgs->len - 1)
		temp &= ~I2CR_TXAK;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */

	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);

	/* read data */
	for (i = 0; i < msgs->len; i++) {
		result = i2c_imx_trx_complete(i2c_imx);
		if (result)
			return result;
		if (i == (msgs->len - 1)) {
			/* It must generate STOP before read I2DR to prevent
			   controller from generating another clock cycle */
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> clear MSTA\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp &= ~(I2CR_MSTA | I2CR_MTX);
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
			i2c_imx_bus_busy(i2c_imx, 0);
			i2c_imx->stopped = 1;
		} else if (i == (msgs->len - 2)) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> set TXAK\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp |= I2CR_TXAK;
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
		}
		msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> read byte: B%d=0x%X\n",
			__func__, i, msgs->buf[i]);
	}
	return 0;
}

static int i2c_imx_xfer(struct i2c_adapter *adapter,
						struct i2c_msg *msgs, int num)
{
	unsigned int i, temp;
	int result;
	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	/* Start I2C transfer */
	result = i2c_imx_start(i2c_imx);
	if (result)
		goto fail0;

	/* read/write data */
	for (i = 0; i < num; i++) {
		if (i) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> repeated start\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp |= I2CR_RSTA;
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
			result =  i2c_imx_bus_busy(i2c_imx, 1);
			if (result)
				goto fail0;
		}
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> transfer message: %d\n", __func__, i);
		/* write/read data */
#ifdef CONFIG_I2C_DEBUG_BUS
		temp = readb(i2c_imx->base + IMX_I2C_I2CR);
		dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
			"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
			(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
			(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
			(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
		temp = readb(i2c_imx->base + IMX_I2C_I2SR);
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
			"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
			(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
			(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
			(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
			(temp & I2SR_RXAK ? 1 : 0));
#endif
		if (msgs[i].flags & I2C_M_RD)
			result = i2c_imx_read(i2c_imx, &msgs[i]);
		else
			result = i2c_imx_write(i2c_imx, &msgs[i]);
		if (result)
			goto fail0;
	}

fail0:
	/* Stop I2C transfer */
	i2c_imx_stop(i2c_imx);

	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
		(result < 0) ? "error" : "success msg",
			(result < 0) ? result : num);
	return (result < 0) ? result : num;
}

static u32 i2c_imx_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm i2c_imx_algo = {
	.master_xfer	= i2c_imx_xfer,
	.functionality	= i2c_imx_func,
};

static int __init i2c_imx_probe(struct platform_device *pdev)
{
	struct imx_i2c_struct *i2c_imx;
	struct resource *res;
	struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
	void __iomem *base;
	resource_size_t res_size;
	int irq, bitrate;
	int ret;

	dev_dbg(&pdev->dev, "<%s>\n", __func__);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "can't get device resources\n");
		return -ENOENT;
	}
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "can't get irq number\n");
		return -ENOENT;
	}

	res_size = resource_size(res);

	if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
		dev_err(&pdev->dev, "request_mem_region failed\n");
		return -EBUSY;
	}

	base = ioremap(res->start, res_size);
	if (!base) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -EIO;
		goto fail1;
	}

	i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
	if (!i2c_imx) {
		dev_err(&pdev->dev, "can't allocate interface\n");
		ret = -ENOMEM;
		goto fail2;
	}

	/* Setup i2c_imx driver structure */
	strcpy(i2c_imx->adapter.name, pdev->name);
	i2c_imx->adapter.owner		= THIS_MODULE;
	i2c_imx->adapter.algo		= &i2c_imx_algo;
	i2c_imx->adapter.dev.parent	= &pdev->dev;
	i2c_imx->adapter.nr 		= pdev->id;
	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
	i2c_imx->irq			= irq;
	i2c_imx->base			= base;
	i2c_imx->res			= res;

	/* Get I2C clock */
	i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
	if (IS_ERR(i2c_imx->clk)) {
		ret = PTR_ERR(i2c_imx->clk);
		dev_err(&pdev->dev, "can't get I2C clock\n");
		goto fail3;
	}

	/* Request IRQ */
	ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
	if (ret) {
		dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
		goto fail4;
	}

	/* Init queue */
	init_waitqueue_head(&i2c_imx->queue);

	/* Set up adapter data */
	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);

	/* Set up clock divider */
	bitrate = IMX_I2C_BIT_RATE;
	ret = of_property_read_u32(pdev->dev.of_node,
				   "clock-frequency", &bitrate);
	if (ret < 0 && pdata && pdata->bitrate)
		bitrate = pdata->bitrate;
	i2c_imx_set_clk(i2c_imx, bitrate);

	/* Set up chip registers to defaults */
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);

	/* Add I2C adapter */
	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
	if (ret < 0) {
		dev_err(&pdev->dev, "registration failed\n");
		goto fail5;
	}

	of_i2c_register_devices(&i2c_imx->adapter);

	/* Set up platform driver data */
	platform_set_drvdata(pdev, i2c_imx);

	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
	dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
		i2c_imx->res->start, i2c_imx->res->end);
	dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
		res_size, i2c_imx->res->start);
	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
		i2c_imx->adapter.name);
	dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");

	return 0;   /* Return OK */

fail5:
	free_irq(i2c_imx->irq, i2c_imx);
fail4:
	clk_put(i2c_imx->clk);
fail3:
	kfree(i2c_imx);
fail2:
	iounmap(base);
fail1:
	release_mem_region(res->start, resource_size(res));
	return ret; /* Return error number */
}

static int __exit i2c_imx_remove(struct platform_device *pdev)
{
	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);

	/* remove adapter */
	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
	i2c_del_adapter(&i2c_imx->adapter);
	platform_set_drvdata(pdev, NULL);

	/* free interrupt */
	free_irq(i2c_imx->irq, i2c_imx);

	/* setup chip registers to defaults */
	writeb(0, i2c_imx->base + IMX_I2C_IADR);
	writeb(0, i2c_imx->base + IMX_I2C_IFDR);
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);

	clk_put(i2c_imx->clk);

	iounmap(i2c_imx->base);
	release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
	kfree(i2c_imx);
	return 0;
}

static struct platform_driver i2c_imx_driver = {
	.remove		= __exit_p(i2c_imx_remove),
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = i2c_imx_dt_ids,
	}
};

static int __init i2c_adap_imx_init(void)
{
	return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
}
subsys_initcall(i2c_adap_imx_init);

static void __exit i2c_adap_imx_exit(void)
{
	platform_driver_unregister(&i2c_imx_driver);
}
module_exit(i2c_adap_imx_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Darius Augulis");
MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
aa11e38c DA	1	/*
	2	* Copyright (C) 2002 Motorola GSG-China
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
	17	* USA.
	18	*
	19	* Author:
	20	* Darius Augulis, Teltonika Inc.
	21	*
	22	* Desc.:
	23	* Implementation of I2C Adapter/Algorithm Driver
	24	* for I2C Bus integrated in Freescale i.MX/MXC processors
	25	*
	26	* Derived from Motorola GSG China I2C example driver
	27	*
	28	* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
	29	* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
	30	* Copyright (C) 2007 RightHand Technologies, Inc.
	31	* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
	32	*
	33	*/
	34
	35	/ Includes *****************************************************************
	36	*******************************************************************************/
	37
	38	#include <linux/init.h>
	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/errno.h>
	42	#include <linux/err.h>
	43	#include <linux/interrupt.h>
	44	#include <linux/delay.h>
	45	#include <linux/i2c.h>
	46	#include <linux/io.h>
	47	#include <linux/sched.h>
	48	#include <linux/platform_device.h>
	49	#include <linux/clk.h>
5a0e3ad6	50	#include <linux/slab.h>
dfcd04b1 SG	51	#include <linux/of.h>
	52	#include <linux/of_device.h>
	53	#include <linux/of_i2c.h>
aa11e38c DA	54
	55	#include <mach/irqs.h>
	56	#include <mach/hardware.h>
	57	#include <mach/i2c.h>
	58
	59	/ Defines ******************************************************************
	60	*******************************************************************************/
	61
	62	/* This will be the driver name the kernel reports */
	63	#define DRIVER_NAME "imx-i2c"
	64
	65	/* Default value */
	66	#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
	67
	68	/* IMX I2C registers */
	69	#define IMX_I2C_IADR 0x00 /* i2c slave address */
	70	#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
	71	#define IMX_I2C_I2CR 0x08 /* i2c control */
	72	#define IMX_I2C_I2SR 0x0C /* i2c status */
	73	#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
	74
	75	/* Bits of IMX I2C registers */
	76	#define I2SR_RXAK 0x01
	77	#define I2SR_IIF 0x02
	78	#define I2SR_SRW 0x04
	79	#define I2SR_IAL 0x10
	80	#define I2SR_IBB 0x20
	81	#define I2SR_IAAS 0x40
	82	#define I2SR_ICF 0x80
	83	#define I2CR_RSTA 0x04
	84	#define I2CR_TXAK 0x08
	85	#define I2CR_MTX 0x10
	86	#define I2CR_MSTA 0x20
	87	#define I2CR_IIEN 0x40
	88	#define I2CR_IEN 0x80
	89
	90	/ Variables ****************************************************************
	91	*******************************************************************************/
	92
aa11e38c DA	93	/*
	94	* sorted list of clock divider, register value pairs
	95	* taken from table 26-5, p.26-9, Freescale i.MX
	96	* Integrated Portable System Processor Reference Manual
	97	* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
	98	*
	99	* Duplicated divider values removed from list
	100	*/
	101
	102	static u16 __initdata i2c_clk_div[50][2] = {
	103	{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
	104	{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
	105	{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
	106	{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
	107	{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
	108	{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
	109	{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
	110	{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
	111	{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
	112	{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
	113	{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
	114	{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
	115	{ 3072, 0x1E }, { 3840, 0x1F }
	116	};
	117
	118	struct imx_i2c_struct {
	119	struct i2c_adapter adapter;
	120	struct resource *res;
	121	struct clk *clk;
	122	void __iomem *base;
	123	int irq;
	124	wait_queue_head_t queue;
	125	unsigned long i2csr;
65de394d	126	unsigned int disable_delay;
43309f3b	127	int stopped;
db3a3d4e	128	unsigned int ifdr; /* IMX_I2C_IFDR */
aa11e38c DA	129	};
aa11e38c DA	130
dfcd04b1 SG	131	static const struct of_device_id i2c_imx_dt_ids[] = {
	132	{ .compatible = "fsl,imx1-i2c", },
	133	{ /* sentinel */ }
	134	};
	135
aa11e38c DA	136	/ Functions for IMX I2C adapter driver *************************************
	137	*******************************************************************************/
	138
43309f3b	139	static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
aa11e38c DA	140	{
aa11e38c DA	141	unsigned long orig_jiffies = jiffies;
43309f3b	142	unsigned int temp;
aa11e38c DA	143
	144	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	145
43309f3b RZ	146	while (1) {
	147	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	148	if (for_busy && (temp & I2SR_IBB))
	149	break;
	150	if (!for_busy && !(temp & I2SR_IBB))
	151	break;
da9c99fc	152	if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
aa11e38c DA	153	dev_dbg(&i2c_imx->adapter.dev,
aa11e38c DA	154	"<%s> I2C bus is busy\n", __func__);
da9c99fc	155	return -ETIMEDOUT;
aa11e38c DA	156	}
	157	schedule();
	158	}
	159
	160	return 0;
	161	}
	162
	163	static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
	164	{
e39428d5	165	wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
aa11e38c	166
e39428d5	167	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
aa11e38c DA	168	dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
	169	return -ETIMEDOUT;
	170	}
	171	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
	172	i2c_imx->i2csr = 0;
	173	return 0;
	174	}
	175
	176	static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
	177	{
	178	if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
	179	dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
	180	return -EIO; /* No ACK */
	181	}
	182
	183	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
	184	return 0;
	185	}
	186
43309f3b	187	static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
aa11e38c DA	188	{
aa11e38c DA	189	unsigned int temp = 0;
43309f3b	190	int result;
aa11e38c DA	191
	192	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	193
83914337	194	clk_prepare_enable(i2c_imx->clk);
db3a3d4e	195	writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
aa11e38c	196	/* Enable I2C controller */
43309f3b	197	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
aa11e38c	198	writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	199
	200	/* Wait controller to be stable */
	201	udelay(50);
	202
aa11e38c DA	203	/* Start I2C transaction */
	204	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	205	temp \|= I2CR_MSTA;
	206	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	207	result = i2c_imx_bus_busy(i2c_imx, 1);
	208	if (result)
	209	return result;
	210	i2c_imx->stopped = 0;
	211
aa11e38c DA	212	temp \|= I2CR_IIEN \| I2CR_MTX \| I2CR_TXAK;
aa11e38c DA	213	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b	214	return result;
aa11e38c DA	215	}
	216
	217	static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
	218	{
	219	unsigned int temp = 0;
	220
43309f3b RZ	221	if (!i2c_imx->stopped) {
	222	/* Stop I2C transaction */
	223	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	224	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	225	temp &= ~(I2CR_MSTA \| I2CR_MTX);
	226	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b	227	}
a4094a76 RZ	228	if (cpu_is_mx1()) {
	229	/*
	230	* This delay caused by an i.MXL hardware bug.
	231	* If no (or too short) delay, no "STOP" bit will be generated.
	232	*/
	233	udelay(i2c_imx->disable_delay);
	234	}
43309f3b	235
a1ee06b7	236	if (!i2c_imx->stopped) {
43309f3b	237	i2c_imx_bus_busy(i2c_imx, 0);
a1ee06b7 VL	238	i2c_imx->stopped = 1;
a1ee06b7 VL	239	}
43309f3b	240
aa11e38c DA	241	/* Disable I2C controller */
aa11e38c DA	242	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
83914337	243	clk_disable_unprepare(i2c_imx->clk);
aa11e38c DA	244	}
	245
	246	static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
	247	unsigned int rate)
	248	{
	249	unsigned int i2c_clk_rate;
	250	unsigned int div;
	251	int i;
	252
	253	/* Divider value calculation */
	254	i2c_clk_rate = clk_get_rate(i2c_imx->clk);
	255	div = (i2c_clk_rate + rate - 1) / rate;
	256	if (div < i2c_clk_div[0][0])
	257	i = 0;
	258	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
	259	i = ARRAY_SIZE(i2c_clk_div) - 1;
	260	else
	261	for (i = 0; i2c_clk_div[i][0] < div; i++);
	262
db3a3d4e RZ	263	/* Store divider value */
db3a3d4e RZ	264	i2c_imx->ifdr = i2c_clk_div[i][1];
aa11e38c DA	265
	266	/*
	267	* There dummy delay is calculated.
	268	* It should be about one I2C clock period long.
	269	* This delay is used in I2C bus disable function
	270	* to fix chip hardware bug.
	271	*/
65de394d	272	i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
aa11e38c DA	273	+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
	274
	275	/* dev_dbg() can't be used, because adapter is not yet registered */
	276	#ifdef CONFIG_I2C_DEBUG_BUS
	277	printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
	278	__func__, i2c_clk_rate, div);
	279	printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
	280	__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
	281	#endif
	282	}
	283
	284	static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
	285	{
	286	struct imx_i2c_struct *i2c_imx = dev_id;
	287	unsigned int temp;
	288
	289	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	290	if (temp & I2SR_IIF) {
	291	/* save status register */
	292	i2c_imx->i2csr = temp;
	293	temp &= ~I2SR_IIF;
	294	writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
e39428d5	295	wake_up(&i2c_imx->queue);
aa11e38c DA	296	return IRQ_HANDLED;
	297	}
	298
	299	return IRQ_NONE;
	300	}
	301
	302	static int i2c_imx_write(struct imx_i2c_struct i2c_imx, struct i2c_msg msgs)
	303	{
	304	int i, result;
	305
	306	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
	307	__func__, msgs->addr << 1);
	308
	309	/* write slave address */
	310	writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
	311	result = i2c_imx_trx_complete(i2c_imx);
	312	if (result)
	313	return result;
	314	result = i2c_imx_acked(i2c_imx);
	315	if (result)
	316	return result;
	317	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
	318
	319	/* write data */
	320	for (i = 0; i < msgs->len; i++) {
	321	dev_dbg(&i2c_imx->adapter.dev,
	322	"<%s> write byte: B%d=0x%X\n",
	323	__func__, i, msgs->buf[i]);
	324	writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
	325	result = i2c_imx_trx_complete(i2c_imx);
	326	if (result)
	327	return result;
	328	result = i2c_imx_acked(i2c_imx);
	329	if (result)
	330	return result;
	331	}
	332	return 0;
	333	}
	334
	335	static int i2c_imx_read(struct imx_i2c_struct i2c_imx, struct i2c_msg msgs)
	336	{
	337	int i, result;
	338	unsigned int temp;
	339
	340	dev_dbg(&i2c_imx->adapter.dev,
	341	"<%s> write slave address: addr=0x%x\n",
	342	__func__, (msgs->addr << 1) \| 0x01);
	343
	344	/* write slave address */
	345	writeb((msgs->addr << 1) \| 0x01, i2c_imx->base + IMX_I2C_I2DR);
	346	result = i2c_imx_trx_complete(i2c_imx);
	347	if (result)
	348	return result;
	349	result = i2c_imx_acked(i2c_imx);
	350	if (result)
	351	return result;
	352
	353	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
	354
	355	/* setup bus to read data */
	356	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	357	temp &= ~I2CR_MTX;
	358	if (msgs->len - 1)
	359	temp &= ~I2CR_TXAK;
360	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
361	readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
362
363	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
364
365	/* read data */
366	for (i = 0; i < msgs->len; i++) {
367	result = i2c_imx_trx_complete(i2c_imx);
368	if (result)
369	return result;
370	if (i == (msgs->len - 1)) {
43309f3b RZ	371	/* It must generate STOP before read I2DR to prevent
43309f3b RZ	372	controller from generating another clock cycle */
aa11e38c DA	373	dev_dbg(&i2c_imx->adapter.dev,
	374	"<%s> clear MSTA\n", __func__);
	375	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
43309f3b	376	temp &= ~(I2CR_MSTA \| I2CR_MTX);
aa11e38c	377	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	378	i2c_imx_bus_busy(i2c_imx, 0);
43309f3b RZ	379	i2c_imx->stopped = 1;
aa11e38c DA	380	} else if (i == (msgs->len - 2)) {
	381	dev_dbg(&i2c_imx->adapter.dev,
	382	"<%s> set TXAK\n", __func__);
	383	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	384	temp \|= I2CR_TXAK;
	385	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	386	}
	387	msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
	388	dev_dbg(&i2c_imx->adapter.dev,
	389	"<%s> read byte: B%d=0x%X\n",
	390	__func__, i, msgs->buf[i]);
	391	}
	392	return 0;
	393	}
	394
	395	static int i2c_imx_xfer(struct i2c_adapter *adapter,
	396	struct i2c_msg *msgs, int num)
	397	{
	398	unsigned int i, temp;
	399	int result;
	400	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
	401
	402	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	403
43309f3b RZ	404	/* Start I2C transfer */
43309f3b RZ	405	result = i2c_imx_start(i2c_imx);
aa11e38c DA	406	if (result)
	407	goto fail0;
	408
aa11e38c DA	409	/* read/write data */
	410	for (i = 0; i < num; i++) {
	411	if (i) {
	412	dev_dbg(&i2c_imx->adapter.dev,
	413	"<%s> repeated start\n", __func__);
	414	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	415	temp \|= I2CR_RSTA;
	416	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	417	result = i2c_imx_bus_busy(i2c_imx, 1);
	418	if (result)
	419	goto fail0;
aa11e38c DA	420	}
	421	dev_dbg(&i2c_imx->adapter.dev,
	422	"<%s> transfer message: %d\n", __func__, i);
	423	/* write/read data */
	424	#ifdef CONFIG_I2C_DEBUG_BUS
	425	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	426	dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
	427	"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
	428	(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
	429	(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
	430	(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
	431	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	432	dev_dbg(&i2c_imx->adapter.dev,
	433	"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
	434	"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
	435	(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
	436	(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
	437	(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
	438	(temp & I2SR_RXAK ? 1 : 0));
	439	#endif
	440	if (msgs[i].flags & I2C_M_RD)
	441	result = i2c_imx_read(i2c_imx, &msgs[i]);
	442	else
	443	result = i2c_imx_write(i2c_imx, &msgs[i]);
da9c99fc AP	444	if (result)
da9c99fc AP	445	goto fail0;
aa11e38c DA	446	}
	447
	448	fail0:
	449	/* Stop I2C transfer */
	450	i2c_imx_stop(i2c_imx);
	451
	452	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
	453	(result < 0) ? "error" : "success msg",
	454	(result < 0) ? result : num);
	455	return (result < 0) ? result : num;
	456	}
	457
	458	static u32 i2c_imx_func(struct i2c_adapter *adapter)
	459	{
	460	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	461	}
	462
	463	static struct i2c_algorithm i2c_imx_algo = {
	464	.master_xfer = i2c_imx_xfer,
	465	.functionality = i2c_imx_func,
	466	};
	467
	468	static int __init i2c_imx_probe(struct platform_device *pdev)
	469	{
	470	struct imx_i2c_struct *i2c_imx;
	471	struct resource *res;
593702c7	472	struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
aa11e38c DA	473	void __iomem *base;
aa11e38c DA	474	resource_size_t res_size;
dfcd04b1	475	int irq, bitrate;
aa11e38c DA	476	int ret;
	477
	478	dev_dbg(&pdev->dev, "<%s>\n", __func__);
	479
	480	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	481	if (!res) {
	482	dev_err(&pdev->dev, "can't get device resources\n");
	483	return -ENOENT;
	484	}
	485	irq = platform_get_irq(pdev, 0);
	486	if (irq < 0) {
	487	dev_err(&pdev->dev, "can't get irq number\n");
	488	return -ENOENT;
	489	}
	490
aa11e38c	491	res_size = resource_size(res);
4927fbf1 UKK	492
4927fbf1 UKK	493	if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
593702c7 SG	494	dev_err(&pdev->dev, "request_mem_region failed\n");
593702c7 SG	495	return -EBUSY;
4927fbf1 UKK	496	}
4927fbf1 UKK	497
aa11e38c DA	498	base = ioremap(res->start, res_size);
	499	if (!base) {
	500	dev_err(&pdev->dev, "ioremap failed\n");
	501	ret = -EIO;
4927fbf1	502	goto fail1;
aa11e38c DA	503	}
	504
	505	i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
	506	if (!i2c_imx) {
	507	dev_err(&pdev->dev, "can't allocate interface\n");
	508	ret = -ENOMEM;
309c18d2 DA	509	goto fail2;
	510	}
	511
aa11e38c DA	512	/* Setup i2c_imx driver structure */
	513	strcpy(i2c_imx->adapter.name, pdev->name);
	514	i2c_imx->adapter.owner = THIS_MODULE;
	515	i2c_imx->adapter.algo = &i2c_imx_algo;
	516	i2c_imx->adapter.dev.parent = &pdev->dev;
	517	i2c_imx->adapter.nr = pdev->id;
dfcd04b1	518	i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
aa11e38c DA	519	i2c_imx->irq = irq;
	520	i2c_imx->base = base;
	521	i2c_imx->res = res;
	522
	523	/* Get I2C clock */
	524	i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
	525	if (IS_ERR(i2c_imx->clk)) {
	526	ret = PTR_ERR(i2c_imx->clk);
	527	dev_err(&pdev->dev, "can't get I2C clock\n");
309c18d2	528	goto fail3;
aa11e38c	529	}
aa11e38c DA	530
	531	/* Request IRQ */
	532	ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
	533	if (ret) {
	534	dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
309c18d2	535	goto fail4;
aa11e38c DA	536	}
	537
	538	/* Init queue */
	539	init_waitqueue_head(&i2c_imx->queue);
	540
	541	/* Set up adapter data */
	542	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
	543
	544	/* Set up clock divider */
dfcd04b1 SG	545	bitrate = IMX_I2C_BIT_RATE;
	546	ret = of_property_read_u32(pdev->dev.of_node,
	547	"clock-frequency", &bitrate);
	548	if (ret < 0 && pdata && pdata->bitrate)
	549	bitrate = pdata->bitrate;
	550	i2c_imx_set_clk(i2c_imx, bitrate);
aa11e38c DA	551
	552	/* Set up chip registers to defaults */
	553	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	554	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	555
	556	/* Add I2C adapter */
	557	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
	558	if (ret < 0) {
	559	dev_err(&pdev->dev, "registration failed\n");
309c18d2	560	goto fail5;
aa11e38c DA	561	}
aa11e38c DA	562
dfcd04b1 SG	563	of_i2c_register_devices(&i2c_imx->adapter);
dfcd04b1 SG	564
aa11e38c DA	565	/* Set up platform driver data */
	566	platform_set_drvdata(pdev, i2c_imx);
	567
	568	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
	569	dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
	570	i2c_imx->res->start, i2c_imx->res->end);
	571	dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
	572	res_size, i2c_imx->res->start);
	573	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
	574	i2c_imx->adapter.name);
	575	dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
	576
	577	return 0; /* Return OK */
	578
309c18d2	579	fail5:
aa11e38c	580	free_irq(i2c_imx->irq, i2c_imx);
309c18d2	581	fail4:
aa11e38c	582	clk_put(i2c_imx->clk);
309c18d2	583	fail3:
aa11e38c	584	kfree(i2c_imx);
4927fbf1	585	fail2:
aa11e38c	586	iounmap(base);
4927fbf1 UKK	587	fail1:
4927fbf1 UKK	588	release_mem_region(res->start, resource_size(res));
aa11e38c DA	589	return ret; /* Return error number */
	590	}
	591
	592	static int __exit i2c_imx_remove(struct platform_device *pdev)
	593	{
	594	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
aa11e38c DA	595
	596	/* remove adapter */
	597	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
	598	i2c_del_adapter(&i2c_imx->adapter);
	599	platform_set_drvdata(pdev, NULL);
	600
	601	/* free interrupt */
	602	free_irq(i2c_imx->irq, i2c_imx);
	603
	604	/* setup chip registers to defaults */
	605	writeb(0, i2c_imx->base + IMX_I2C_IADR);
	606	writeb(0, i2c_imx->base + IMX_I2C_IFDR);
	607	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	608	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	609
aa11e38c DA	610	clk_put(i2c_imx->clk);
	611
	612	iounmap(i2c_imx->base);
4927fbf1	613	release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
aa11e38c DA	614	kfree(i2c_imx);
	615	return 0;
	616	}
	617
	618	static struct platform_driver i2c_imx_driver = {
aa11e38c DA	619	.remove = __exit_p(i2c_imx_remove),
	620	.driver = {
	621	.name = DRIVER_NAME,
	622	.owner = THIS_MODULE,
dfcd04b1	623	.of_match_table = i2c_imx_dt_ids,
aa11e38c DA	624	}
	625	};
	626
	627	static int __init i2c_adap_imx_init(void)
	628	{
	629	return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
	630	}
5d3f3331	631	subsys_initcall(i2c_adap_imx_init);
aa11e38c DA	632
	633	static void __exit i2c_adap_imx_exit(void)
	634	{
	635	platform_driver_unregister(&i2c_imx_driver);
	636	}
aa11e38c DA	637	module_exit(i2c_adap_imx_exit);
	638
	639	MODULE_LICENSE("GPL");
	640	MODULE_AUTHOR("Darius Augulis");
	641	MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
	642	MODULE_ALIAS("platform:" DRIVER_NAME);