]>
Commit | Line | Data |
---|---|---|
13f35ac1 NH |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * Copyright(c) 2012 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * GPL LICENSE SUMMARY | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
13f35ac1 NH |
17 | * The full GNU General Public License is included in this distribution |
18 | * in the file called LICENSE.GPL. | |
19 | * | |
20 | * BSD LICENSE | |
21 | * | |
22 | * Redistribution and use in source and binary forms, with or without | |
23 | * modification, are permitted provided that the following conditions | |
24 | * are met: | |
25 | * | |
26 | * * Redistributions of source code must retain the above copyright | |
27 | * notice, this list of conditions and the following disclaimer. | |
28 | * * Redistributions in binary form must reproduce the above copyright | |
29 | * notice, this list of conditions and the following disclaimer in | |
30 | * the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * * Neither the name of Intel Corporation nor the names of its | |
33 | * contributors may be used to endorse or promote products derived | |
34 | * from this software without specific prior written permission. | |
35 | * | |
36 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
37 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
38 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
39 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
40 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
41 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
42 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
43 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
44 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
45 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
46 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
47 | */ | |
48 | ||
49 | /* | |
50 | * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor | |
51 | * S12xx Product Family. | |
52 | * | |
53 | * Features supported by this driver: | |
54 | * Hardware PEC yes | |
55 | * Block buffer yes | |
56 | * Block process call transaction no | |
57 | * Slave mode no | |
58 | */ | |
59 | ||
60 | #include <linux/module.h> | |
13f35ac1 NH |
61 | #include <linux/pci.h> |
62 | #include <linux/kernel.h> | |
63 | #include <linux/stddef.h> | |
64 | #include <linux/completion.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/i2c.h> | |
67 | #include <linux/acpi.h> | |
68 | #include <linux/interrupt.h> | |
69 | ||
2f8e2c87 | 70 | #include <linux/io-64-nonatomic-lo-hi.h> |
13f35ac1 NH |
71 | |
72 | /* PCI Address Constants */ | |
73 | #define SMBBAR 0 | |
74 | ||
75 | /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ | |
76 | #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 | |
77 | #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a | |
abaa7b0c | 78 | #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac |
488b9269 | 79 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 |
13f35ac1 | 80 | |
8b57cebe | 81 | #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ |
13f35ac1 NH |
82 | #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ |
83 | ||
84 | /* Hardware Descriptor Constants - Control Field */ | |
85 | #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ | |
86 | #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ | |
87 | #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ | |
88 | #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ | |
89 | #define ISMT_DESC_I2C 0x20 /* I2C Enable */ | |
90 | #define ISMT_DESC_INT 0x40 /* Interrupt */ | |
91 | #define ISMT_DESC_SOE 0x80 /* Stop On Error */ | |
92 | ||
93 | /* Hardware Descriptor Constants - Status Field */ | |
94 | #define ISMT_DESC_SCS 0x01 /* Success */ | |
95 | #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ | |
96 | #define ISMT_DESC_NAK 0x08 /* NAK Received */ | |
97 | #define ISMT_DESC_CRC 0x10 /* CRC Error */ | |
98 | #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ | |
99 | #define ISMT_DESC_COL 0x40 /* Collisions */ | |
100 | #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ | |
101 | ||
102 | /* Macros */ | |
103 | #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) | |
104 | ||
105 | /* iSMT General Register address offsets (SMBBAR + <addr>) */ | |
106 | #define ISMT_GR_GCTRL 0x000 /* General Control */ | |
107 | #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ | |
108 | #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ | |
109 | #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ | |
110 | #define ISMT_GR_ERRSTS 0x018 /* Error Status */ | |
111 | #define ISMT_GR_ERRINFO 0x01c /* Error Information */ | |
112 | ||
113 | /* iSMT Master Registers */ | |
114 | #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ | |
115 | #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ | |
116 | #define ISMT_MSTR_MSTS 0x10c /* Master Status */ | |
117 | #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ | |
118 | #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ | |
119 | ||
120 | /* iSMT Miscellaneous Registers */ | |
121 | #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ | |
122 | ||
123 | /* General Control Register (GCTRL) bit definitions */ | |
124 | #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ | |
125 | #define ISMT_GCTRL_KILL 0x08 /* Kill */ | |
126 | #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ | |
127 | ||
128 | /* Master Control Register (MCTRL) bit definitions */ | |
129 | #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ | |
130 | #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ | |
131 | #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ | |
132 | ||
133 | /* Master Status Register (MSTS) bit definitions */ | |
134 | #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ | |
135 | #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ | |
136 | #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ | |
137 | #define ISMT_MSTS_IP 0x01 /* In Progress */ | |
138 | ||
139 | /* Master Descriptor Size (MDS) bit definitions */ | |
140 | #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ | |
141 | ||
142 | /* SMBus PHY Global Timing Register (SPGT) bit definitions */ | |
143 | #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ | |
144 | #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ | |
145 | #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ | |
146 | #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ | |
147 | #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ | |
148 | ||
149 | ||
150 | /* MSI Control Register (MSICTL) bit definitions */ | |
151 | #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ | |
152 | ||
153 | /* iSMT Hardware Descriptor */ | |
154 | struct ismt_desc { | |
155 | u8 tgtaddr_rw; /* target address & r/w bit */ | |
156 | u8 wr_len_cmd; /* write length in bytes or a command */ | |
157 | u8 rd_len; /* read length */ | |
158 | u8 control; /* control bits */ | |
159 | u8 status; /* status bits */ | |
160 | u8 retry; /* collision retry and retry count */ | |
161 | u8 rxbytes; /* received bytes */ | |
162 | u8 txbytes; /* transmitted bytes */ | |
163 | u32 dptr_low; /* lower 32 bit of the data pointer */ | |
164 | u32 dptr_high; /* upper 32 bit of the data pointer */ | |
165 | } __packed; | |
166 | ||
167 | struct ismt_priv { | |
168 | struct i2c_adapter adapter; | |
6109dbd6 | 169 | void __iomem *smba; /* PCI BAR */ |
13f35ac1 NH |
170 | struct pci_dev *pci_dev; |
171 | struct ismt_desc *hw; /* descriptor virt base addr */ | |
172 | dma_addr_t io_rng_dma; /* descriptor HW base addr */ | |
173 | u8 head; /* ring buffer head pointer */ | |
174 | struct completion cmp; /* interrupt completion */ | |
175 | u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */ | |
13f35ac1 NH |
176 | }; |
177 | ||
178 | /** | |
179 | * ismt_ids - PCI device IDs supported by this driver | |
180 | */ | |
392debf1 | 181 | static const struct pci_device_id ismt_ids[] = { |
13f35ac1 NH |
182 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, |
183 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, | |
abaa7b0c | 184 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) }, |
488b9269 | 185 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, |
13f35ac1 NH |
186 | { 0, } |
187 | }; | |
188 | ||
189 | MODULE_DEVICE_TABLE(pci, ismt_ids); | |
190 | ||
191 | /* Bus speed control bits for slow debuggers - refer to the docs for usage */ | |
192 | static unsigned int bus_speed; | |
193 | module_param(bus_speed, uint, S_IRUGO); | |
194 | MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); | |
195 | ||
196 | /** | |
197 | * __ismt_desc_dump() - dump the contents of a specific descriptor | |
198 | */ | |
199 | static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) | |
200 | { | |
201 | ||
202 | dev_dbg(dev, "Descriptor struct: %p\n", desc); | |
203 | dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); | |
204 | dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); | |
205 | dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); | |
206 | dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); | |
207 | dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); | |
208 | dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); | |
209 | dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); | |
210 | dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); | |
211 | dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); | |
212 | dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); | |
213 | } | |
214 | /** | |
215 | * ismt_desc_dump() - dump the contents of a descriptor for debug purposes | |
216 | * @priv: iSMT private data | |
217 | */ | |
218 | static void ismt_desc_dump(struct ismt_priv *priv) | |
219 | { | |
220 | struct device *dev = &priv->pci_dev->dev; | |
221 | struct ismt_desc *desc = &priv->hw[priv->head]; | |
222 | ||
223 | dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); | |
224 | __ismt_desc_dump(dev, desc); | |
225 | } | |
226 | ||
227 | /** | |
228 | * ismt_gen_reg_dump() - dump the iSMT General Registers | |
229 | * @priv: iSMT private data | |
230 | */ | |
231 | static void ismt_gen_reg_dump(struct ismt_priv *priv) | |
232 | { | |
233 | struct device *dev = &priv->pci_dev->dev; | |
234 | ||
235 | dev_dbg(dev, "Dump of the iSMT General Registers\n"); | |
236 | dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", | |
237 | priv->smba + ISMT_GR_GCTRL, | |
238 | readl(priv->smba + ISMT_GR_GCTRL)); | |
239 | dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", | |
240 | priv->smba + ISMT_GR_SMTICL, | |
241 | (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); | |
242 | dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", | |
243 | priv->smba + ISMT_GR_ERRINTMSK, | |
244 | readl(priv->smba + ISMT_GR_ERRINTMSK)); | |
245 | dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", | |
246 | priv->smba + ISMT_GR_ERRAERMSK, | |
247 | readl(priv->smba + ISMT_GR_ERRAERMSK)); | |
248 | dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", | |
249 | priv->smba + ISMT_GR_ERRSTS, | |
250 | readl(priv->smba + ISMT_GR_ERRSTS)); | |
251 | dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", | |
252 | priv->smba + ISMT_GR_ERRINFO, | |
253 | readl(priv->smba + ISMT_GR_ERRINFO)); | |
254 | } | |
255 | ||
256 | /** | |
257 | * ismt_mstr_reg_dump() - dump the iSMT Master Registers | |
258 | * @priv: iSMT private data | |
259 | */ | |
260 | static void ismt_mstr_reg_dump(struct ismt_priv *priv) | |
261 | { | |
262 | struct device *dev = &priv->pci_dev->dev; | |
263 | ||
264 | dev_dbg(dev, "Dump of the iSMT Master Registers\n"); | |
265 | dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", | |
266 | priv->smba + ISMT_MSTR_MDBA, | |
267 | (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); | |
268 | dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", | |
269 | priv->smba + ISMT_MSTR_MCTRL, | |
270 | readl(priv->smba + ISMT_MSTR_MCTRL)); | |
271 | dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", | |
272 | priv->smba + ISMT_MSTR_MSTS, | |
273 | readl(priv->smba + ISMT_MSTR_MSTS)); | |
274 | dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", | |
275 | priv->smba + ISMT_MSTR_MDS, | |
276 | readl(priv->smba + ISMT_MSTR_MDS)); | |
277 | dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", | |
278 | priv->smba + ISMT_MSTR_RPOLICY, | |
279 | readl(priv->smba + ISMT_MSTR_RPOLICY)); | |
280 | dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", | |
281 | priv->smba + ISMT_SPGT, | |
282 | readl(priv->smba + ISMT_SPGT)); | |
283 | } | |
284 | ||
285 | /** | |
286 | * ismt_submit_desc() - add a descriptor to the ring | |
287 | * @priv: iSMT private data | |
288 | */ | |
289 | static void ismt_submit_desc(struct ismt_priv *priv) | |
290 | { | |
291 | uint fmhp; | |
292 | uint val; | |
293 | ||
294 | ismt_desc_dump(priv); | |
295 | ismt_gen_reg_dump(priv); | |
296 | ismt_mstr_reg_dump(priv); | |
297 | ||
298 | /* Set the FMHP (Firmware Master Head Pointer)*/ | |
299 | fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; | |
300 | val = readl(priv->smba + ISMT_MSTR_MCTRL); | |
301 | writel((val & ~ISMT_MCTRL_FMHP) | fmhp, | |
302 | priv->smba + ISMT_MSTR_MCTRL); | |
303 | ||
304 | /* Set the start bit */ | |
305 | val = readl(priv->smba + ISMT_MSTR_MCTRL); | |
306 | writel(val | ISMT_MCTRL_SS, | |
307 | priv->smba + ISMT_MSTR_MCTRL); | |
308 | } | |
309 | ||
310 | /** | |
311 | * ismt_process_desc() - handle the completion of the descriptor | |
312 | * @desc: the iSMT hardware descriptor | |
313 | * @data: data buffer from the upper layer | |
314 | * @priv: ismt_priv struct holding our dma buffer | |
315 | * @size: SMBus transaction type | |
316 | * @read_write: flag to indicate if this is a read or write | |
317 | */ | |
318 | static int ismt_process_desc(const struct ismt_desc *desc, | |
319 | union i2c_smbus_data *data, | |
320 | struct ismt_priv *priv, int size, | |
321 | char read_write) | |
322 | { | |
323 | u8 *dma_buffer = priv->dma_buffer; | |
324 | ||
325 | dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); | |
326 | __ismt_desc_dump(&priv->pci_dev->dev, desc); | |
327 | ||
328 | if (desc->status & ISMT_DESC_SCS) { | |
329 | if (read_write == I2C_SMBUS_WRITE && | |
330 | size != I2C_SMBUS_PROC_CALL) | |
331 | return 0; | |
332 | ||
333 | switch (size) { | |
334 | case I2C_SMBUS_BYTE: | |
335 | case I2C_SMBUS_BYTE_DATA: | |
336 | data->byte = dma_buffer[0]; | |
337 | break; | |
338 | case I2C_SMBUS_WORD_DATA: | |
339 | case I2C_SMBUS_PROC_CALL: | |
340 | data->word = dma_buffer[0] | (dma_buffer[1] << 8); | |
341 | break; | |
342 | case I2C_SMBUS_BLOCK_DATA: | |
001cebf0 | 343 | case I2C_SMBUS_I2C_BLOCK_DATA: |
13f35ac1 NH |
344 | memcpy(&data->block[1], dma_buffer, desc->rxbytes); |
345 | data->block[0] = desc->rxbytes; | |
346 | break; | |
347 | } | |
348 | return 0; | |
349 | } | |
350 | ||
351 | if (likely(desc->status & ISMT_DESC_NAK)) | |
352 | return -ENXIO; | |
353 | ||
354 | if (desc->status & ISMT_DESC_CRC) | |
355 | return -EBADMSG; | |
356 | ||
357 | if (desc->status & ISMT_DESC_COL) | |
358 | return -EAGAIN; | |
359 | ||
360 | if (desc->status & ISMT_DESC_LPR) | |
361 | return -EPROTO; | |
362 | ||
363 | if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) | |
364 | return -ETIMEDOUT; | |
365 | ||
366 | return -EIO; | |
367 | } | |
368 | ||
369 | /** | |
370 | * ismt_access() - process an SMBus command | |
371 | * @adap: the i2c host adapter | |
372 | * @addr: address of the i2c/SMBus target | |
373 | * @flags: command options | |
374 | * @read_write: read from or write to device | |
375 | * @command: the i2c/SMBus command to issue | |
376 | * @size: SMBus transaction type | |
377 | * @data: read/write data buffer | |
378 | */ | |
379 | static int ismt_access(struct i2c_adapter *adap, u16 addr, | |
380 | unsigned short flags, char read_write, u8 command, | |
381 | int size, union i2c_smbus_data *data) | |
382 | { | |
383 | int ret; | |
1abdd5d9 | 384 | unsigned long time_left; |
13f35ac1 NH |
385 | dma_addr_t dma_addr = 0; /* address of the data buffer */ |
386 | u8 dma_size = 0; | |
387 | enum dma_data_direction dma_direction = 0; | |
388 | struct ismt_desc *desc; | |
389 | struct ismt_priv *priv = i2c_get_adapdata(adap); | |
390 | struct device *dev = &priv->pci_dev->dev; | |
391 | ||
392 | desc = &priv->hw[priv->head]; | |
bf416910 JR |
393 | |
394 | /* Initialize the DMA buffer */ | |
395 | memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer)); | |
13f35ac1 NH |
396 | |
397 | /* Initialize the descriptor */ | |
398 | memset(desc, 0, sizeof(struct ismt_desc)); | |
399 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); | |
400 | ||
401 | /* Initialize common control bits */ | |
f92d155d | 402 | if (likely(pci_dev_msi_enabled(priv->pci_dev))) |
13f35ac1 NH |
403 | desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; |
404 | else | |
405 | desc->control = ISMT_DESC_FAIR; | |
406 | ||
407 | if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) | |
408 | && (size != I2C_SMBUS_I2C_BLOCK_DATA)) | |
409 | desc->control |= ISMT_DESC_PEC; | |
410 | ||
411 | switch (size) { | |
412 | case I2C_SMBUS_QUICK: | |
413 | dev_dbg(dev, "I2C_SMBUS_QUICK\n"); | |
414 | break; | |
415 | ||
416 | case I2C_SMBUS_BYTE: | |
417 | if (read_write == I2C_SMBUS_WRITE) { | |
418 | /* | |
419 | * Send Byte | |
420 | * The command field contains the write data | |
421 | */ | |
422 | dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); | |
423 | desc->control |= ISMT_DESC_CWRL; | |
424 | desc->wr_len_cmd = command; | |
425 | } else { | |
426 | /* Receive Byte */ | |
427 | dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); | |
428 | dma_size = 1; | |
429 | dma_direction = DMA_FROM_DEVICE; | |
430 | desc->rd_len = 1; | |
431 | } | |
432 | break; | |
433 | ||
434 | case I2C_SMBUS_BYTE_DATA: | |
435 | if (read_write == I2C_SMBUS_WRITE) { | |
436 | /* | |
437 | * Write Byte | |
438 | * Command plus 1 data byte | |
439 | */ | |
440 | dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); | |
441 | desc->wr_len_cmd = 2; | |
442 | dma_size = 2; | |
443 | dma_direction = DMA_TO_DEVICE; | |
444 | priv->dma_buffer[0] = command; | |
445 | priv->dma_buffer[1] = data->byte; | |
446 | } else { | |
447 | /* Read Byte */ | |
448 | dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); | |
449 | desc->control |= ISMT_DESC_CWRL; | |
450 | desc->wr_len_cmd = command; | |
451 | desc->rd_len = 1; | |
452 | dma_size = 1; | |
453 | dma_direction = DMA_FROM_DEVICE; | |
454 | } | |
455 | break; | |
456 | ||
457 | case I2C_SMBUS_WORD_DATA: | |
458 | if (read_write == I2C_SMBUS_WRITE) { | |
459 | /* Write Word */ | |
460 | dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); | |
461 | desc->wr_len_cmd = 3; | |
462 | dma_size = 3; | |
463 | dma_direction = DMA_TO_DEVICE; | |
464 | priv->dma_buffer[0] = command; | |
465 | priv->dma_buffer[1] = data->word & 0xff; | |
466 | priv->dma_buffer[2] = data->word >> 8; | |
467 | } else { | |
468 | /* Read Word */ | |
469 | dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); | |
470 | desc->wr_len_cmd = command; | |
471 | desc->control |= ISMT_DESC_CWRL; | |
472 | desc->rd_len = 2; | |
473 | dma_size = 2; | |
474 | dma_direction = DMA_FROM_DEVICE; | |
475 | } | |
476 | break; | |
477 | ||
478 | case I2C_SMBUS_PROC_CALL: | |
479 | dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); | |
480 | desc->wr_len_cmd = 3; | |
481 | desc->rd_len = 2; | |
482 | dma_size = 3; | |
483 | dma_direction = DMA_BIDIRECTIONAL; | |
484 | priv->dma_buffer[0] = command; | |
485 | priv->dma_buffer[1] = data->word & 0xff; | |
486 | priv->dma_buffer[2] = data->word >> 8; | |
487 | break; | |
488 | ||
489 | case I2C_SMBUS_BLOCK_DATA: | |
490 | if (read_write == I2C_SMBUS_WRITE) { | |
491 | /* Block Write */ | |
492 | dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); | |
493 | dma_size = data->block[0] + 1; | |
494 | dma_direction = DMA_TO_DEVICE; | |
495 | desc->wr_len_cmd = dma_size; | |
496 | desc->control |= ISMT_DESC_BLK; | |
497 | priv->dma_buffer[0] = command; | |
979bbf7b | 498 | memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1); |
13f35ac1 NH |
499 | } else { |
500 | /* Block Read */ | |
501 | dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); | |
502 | dma_size = I2C_SMBUS_BLOCK_MAX; | |
503 | dma_direction = DMA_FROM_DEVICE; | |
504 | desc->rd_len = dma_size; | |
505 | desc->wr_len_cmd = command; | |
506 | desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); | |
507 | } | |
508 | break; | |
509 | ||
001cebf0 | 510 | case I2C_SMBUS_I2C_BLOCK_DATA: |
511 | /* Make sure the length is valid */ | |
512 | if (data->block[0] < 1) | |
513 | data->block[0] = 1; | |
514 | ||
515 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
516 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
517 | ||
518 | if (read_write == I2C_SMBUS_WRITE) { | |
519 | /* i2c Block Write */ | |
520 | dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n"); | |
521 | dma_size = data->block[0] + 1; | |
522 | dma_direction = DMA_TO_DEVICE; | |
523 | desc->wr_len_cmd = dma_size; | |
524 | desc->control |= ISMT_DESC_I2C; | |
525 | priv->dma_buffer[0] = command; | |
979bbf7b | 526 | memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1); |
001cebf0 | 527 | } else { |
528 | /* i2c Block Read */ | |
529 | dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n"); | |
530 | dma_size = data->block[0]; | |
531 | dma_direction = DMA_FROM_DEVICE; | |
532 | desc->rd_len = dma_size; | |
533 | desc->wr_len_cmd = command; | |
534 | desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL); | |
535 | /* | |
536 | * Per the "Table 15-15. I2C Commands", | |
537 | * in the External Design Specification (EDS), | |
538 | * (Document Number: 508084, Revision: 2.0), | |
539 | * the _rw bit must be 0 | |
540 | */ | |
541 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0); | |
542 | } | |
543 | break; | |
544 | ||
13f35ac1 NH |
545 | default: |
546 | dev_err(dev, "Unsupported transaction %d\n", | |
547 | size); | |
548 | return -EOPNOTSUPP; | |
549 | } | |
550 | ||
551 | /* map the data buffer */ | |
552 | if (dma_size != 0) { | |
553 | dev_dbg(dev, " dev=%p\n", dev); | |
554 | dev_dbg(dev, " data=%p\n", data); | |
555 | dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer); | |
556 | dev_dbg(dev, " dma_size=%d\n", dma_size); | |
557 | dev_dbg(dev, " dma_direction=%d\n", dma_direction); | |
558 | ||
559 | dma_addr = dma_map_single(dev, | |
560 | priv->dma_buffer, | |
561 | dma_size, | |
562 | dma_direction); | |
563 | ||
564 | if (dma_mapping_error(dev, dma_addr)) { | |
565 | dev_err(dev, "Error in mapping dma buffer %p\n", | |
566 | priv->dma_buffer); | |
567 | return -EIO; | |
568 | } | |
569 | ||
570 | dev_dbg(dev, " dma_addr = 0x%016llX\n", | |
724d5eda | 571 | (unsigned long long)dma_addr); |
13f35ac1 NH |
572 | |
573 | desc->dptr_low = lower_32_bits(dma_addr); | |
574 | desc->dptr_high = upper_32_bits(dma_addr); | |
575 | } | |
576 | ||
16735d02 | 577 | reinit_completion(&priv->cmp); |
13f35ac1 NH |
578 | |
579 | /* Add the descriptor */ | |
580 | ismt_submit_desc(priv); | |
581 | ||
582 | /* Now we wait for interrupt completion, 1s */ | |
1abdd5d9 | 583 | time_left = wait_for_completion_timeout(&priv->cmp, HZ*1); |
13f35ac1 NH |
584 | |
585 | /* unmap the data buffer */ | |
586 | if (dma_size != 0) | |
587 | dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction); | |
588 | ||
1abdd5d9 | 589 | if (unlikely(!time_left)) { |
13f35ac1 NH |
590 | dev_err(dev, "completion wait timed out\n"); |
591 | ret = -ETIMEDOUT; | |
592 | goto out; | |
593 | } | |
594 | ||
595 | /* do any post processing of the descriptor here */ | |
596 | ret = ismt_process_desc(desc, data, priv, size, read_write); | |
597 | ||
598 | out: | |
599 | /* Update the ring pointer */ | |
600 | priv->head++; | |
601 | priv->head %= ISMT_DESC_ENTRIES; | |
602 | ||
603 | return ret; | |
604 | } | |
605 | ||
606 | /** | |
607 | * ismt_func() - report which i2c commands are supported by this adapter | |
608 | * @adap: the i2c host adapter | |
609 | */ | |
610 | static u32 ismt_func(struct i2c_adapter *adap) | |
611 | { | |
612 | return I2C_FUNC_SMBUS_QUICK | | |
613 | I2C_FUNC_SMBUS_BYTE | | |
614 | I2C_FUNC_SMBUS_BYTE_DATA | | |
615 | I2C_FUNC_SMBUS_WORD_DATA | | |
616 | I2C_FUNC_SMBUS_PROC_CALL | | |
617 | I2C_FUNC_SMBUS_BLOCK_DATA | | |
001cebf0 | 618 | I2C_FUNC_SMBUS_I2C_BLOCK | |
13f35ac1 NH |
619 | I2C_FUNC_SMBUS_PEC; |
620 | } | |
621 | ||
622 | /** | |
623 | * smbus_algorithm - the adapter algorithm and supported functionality | |
624 | * @smbus_xfer: the adapter algorithm | |
625 | * @functionality: functionality supported by the adapter | |
626 | */ | |
627 | static const struct i2c_algorithm smbus_algorithm = { | |
628 | .smbus_xfer = ismt_access, | |
629 | .functionality = ismt_func, | |
630 | }; | |
631 | ||
632 | /** | |
633 | * ismt_handle_isr() - interrupt handler bottom half | |
634 | * @priv: iSMT private data | |
635 | */ | |
636 | static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) | |
637 | { | |
638 | complete(&priv->cmp); | |
639 | ||
640 | return IRQ_HANDLED; | |
641 | } | |
642 | ||
643 | ||
644 | /** | |
645 | * ismt_do_interrupt() - IRQ interrupt handler | |
646 | * @vec: interrupt vector | |
647 | * @data: iSMT private data | |
648 | */ | |
649 | static irqreturn_t ismt_do_interrupt(int vec, void *data) | |
650 | { | |
651 | u32 val; | |
652 | struct ismt_priv *priv = data; | |
653 | ||
654 | /* | |
655 | * check to see it's our interrupt, return IRQ_NONE if not ours | |
656 | * since we are sharing interrupt | |
657 | */ | |
658 | val = readl(priv->smba + ISMT_MSTR_MSTS); | |
659 | ||
660 | if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) | |
661 | return IRQ_NONE; | |
662 | else | |
663 | writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, | |
664 | priv->smba + ISMT_MSTR_MSTS); | |
665 | ||
666 | return ismt_handle_isr(priv); | |
667 | } | |
668 | ||
669 | /** | |
670 | * ismt_do_msi_interrupt() - MSI interrupt handler | |
671 | * @vec: interrupt vector | |
672 | * @data: iSMT private data | |
673 | */ | |
674 | static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) | |
675 | { | |
676 | return ismt_handle_isr(data); | |
677 | } | |
678 | ||
679 | /** | |
680 | * ismt_hw_init() - initialize the iSMT hardware | |
681 | * @priv: iSMT private data | |
682 | */ | |
683 | static void ismt_hw_init(struct ismt_priv *priv) | |
684 | { | |
685 | u32 val; | |
686 | struct device *dev = &priv->pci_dev->dev; | |
687 | ||
688 | /* initialize the Master Descriptor Base Address (MDBA) */ | |
689 | writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); | |
690 | ||
691 | /* initialize the Master Control Register (MCTRL) */ | |
692 | writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); | |
693 | ||
694 | /* initialize the Master Status Register (MSTS) */ | |
695 | writel(0, priv->smba + ISMT_MSTR_MSTS); | |
696 | ||
697 | /* initialize the Master Descriptor Size (MDS) */ | |
698 | val = readl(priv->smba + ISMT_MSTR_MDS); | |
699 | writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), | |
700 | priv->smba + ISMT_MSTR_MDS); | |
701 | ||
702 | /* | |
703 | * Set the SMBus speed (could use this for slow HW debuggers) | |
704 | */ | |
705 | ||
706 | val = readl(priv->smba + ISMT_SPGT); | |
707 | ||
708 | switch (bus_speed) { | |
709 | case 0: | |
710 | break; | |
711 | ||
712 | case 80: | |
713 | dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); | |
714 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), | |
715 | priv->smba + ISMT_SPGT); | |
716 | break; | |
717 | ||
718 | case 100: | |
719 | dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); | |
720 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), | |
721 | priv->smba + ISMT_SPGT); | |
722 | break; | |
723 | ||
724 | case 400: | |
725 | dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); | |
726 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), | |
727 | priv->smba + ISMT_SPGT); | |
728 | break; | |
729 | ||
730 | case 1000: | |
731 | dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); | |
732 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), | |
733 | priv->smba + ISMT_SPGT); | |
734 | break; | |
735 | ||
736 | default: | |
737 | dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); | |
738 | break; | |
739 | } | |
740 | ||
741 | val = readl(priv->smba + ISMT_SPGT); | |
742 | ||
743 | switch (val & ISMT_SPGT_SPD_MASK) { | |
744 | case ISMT_SPGT_SPD_80K: | |
745 | bus_speed = 80; | |
746 | break; | |
747 | case ISMT_SPGT_SPD_100K: | |
748 | bus_speed = 100; | |
749 | break; | |
750 | case ISMT_SPGT_SPD_400K: | |
751 | bus_speed = 400; | |
752 | break; | |
753 | case ISMT_SPGT_SPD_1M: | |
754 | bus_speed = 1000; | |
755 | break; | |
756 | } | |
757 | dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); | |
758 | } | |
759 | ||
760 | /** | |
761 | * ismt_dev_init() - initialize the iSMT data structures | |
762 | * @priv: iSMT private data | |
763 | */ | |
764 | static int ismt_dev_init(struct ismt_priv *priv) | |
765 | { | |
766 | /* allocate memory for the descriptor */ | |
767 | priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, | |
768 | (ISMT_DESC_ENTRIES | |
769 | * sizeof(struct ismt_desc)), | |
770 | &priv->io_rng_dma, | |
771 | GFP_KERNEL); | |
772 | if (!priv->hw) | |
773 | return -ENOMEM; | |
774 | ||
775 | memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc))); | |
776 | ||
777 | priv->head = 0; | |
778 | init_completion(&priv->cmp); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | /** | |
784 | * ismt_int_init() - initialize interrupts | |
785 | * @priv: iSMT private data | |
786 | */ | |
787 | static int ismt_int_init(struct ismt_priv *priv) | |
788 | { | |
789 | int err; | |
790 | ||
791 | /* Try using MSI interrupts */ | |
792 | err = pci_enable_msi(priv->pci_dev); | |
064181b0 | 793 | if (err) |
13f35ac1 | 794 | goto intx; |
13f35ac1 NH |
795 | |
796 | err = devm_request_irq(&priv->pci_dev->dev, | |
797 | priv->pci_dev->irq, | |
798 | ismt_do_msi_interrupt, | |
799 | 0, | |
800 | "ismt-msi", | |
801 | priv); | |
802 | if (err) { | |
803 | pci_disable_msi(priv->pci_dev); | |
804 | goto intx; | |
805 | } | |
806 | ||
064181b0 | 807 | return 0; |
13f35ac1 NH |
808 | |
809 | /* Try using legacy interrupts */ | |
810 | intx: | |
064181b0 AS |
811 | dev_warn(&priv->pci_dev->dev, |
812 | "Unable to use MSI interrupts, falling back to legacy\n"); | |
813 | ||
13f35ac1 NH |
814 | err = devm_request_irq(&priv->pci_dev->dev, |
815 | priv->pci_dev->irq, | |
816 | ismt_do_interrupt, | |
817 | IRQF_SHARED, | |
818 | "ismt-intx", | |
819 | priv); | |
820 | if (err) { | |
821 | dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); | |
6befa6dd | 822 | return err; |
13f35ac1 NH |
823 | } |
824 | ||
13f35ac1 NH |
825 | return 0; |
826 | } | |
827 | ||
828 | static struct pci_driver ismt_driver; | |
829 | ||
830 | /** | |
831 | * ismt_probe() - probe for iSMT devices | |
832 | * @pdev: PCI-Express device | |
833 | * @id: PCI-Express device ID | |
834 | */ | |
835 | static int | |
836 | ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
837 | { | |
838 | int err; | |
839 | struct ismt_priv *priv; | |
840 | unsigned long start, len; | |
841 | ||
842 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
843 | if (!priv) | |
844 | return -ENOMEM; | |
845 | ||
846 | pci_set_drvdata(pdev, priv); | |
8eb5c87a | 847 | |
13f35ac1 NH |
848 | i2c_set_adapdata(&priv->adapter, priv); |
849 | priv->adapter.owner = THIS_MODULE; | |
13f35ac1 | 850 | priv->adapter.class = I2C_CLASS_HWMON; |
13f35ac1 | 851 | priv->adapter.algo = &smbus_algorithm; |
13f35ac1 | 852 | priv->adapter.dev.parent = &pdev->dev; |
8eb5c87a | 853 | ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); |
13f35ac1 NH |
854 | priv->adapter.retries = ISMT_MAX_RETRIES; |
855 | ||
856 | priv->pci_dev = pdev; | |
857 | ||
858 | err = pcim_enable_device(pdev); | |
859 | if (err) { | |
860 | dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
861 | err); | |
862 | return err; | |
863 | } | |
864 | ||
865 | /* enable bus mastering */ | |
866 | pci_set_master(pdev); | |
867 | ||
868 | /* Determine the address of the SMBus area */ | |
869 | start = pci_resource_start(pdev, SMBBAR); | |
870 | len = pci_resource_len(pdev, SMBBAR); | |
871 | if (!start || !len) { | |
872 | dev_err(&pdev->dev, | |
873 | "SMBus base address uninitialized, upgrade BIOS\n"); | |
874 | return -ENODEV; | |
875 | } | |
876 | ||
877 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), | |
878 | "SMBus iSMT adapter at %lx", start); | |
879 | ||
880 | dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); | |
881 | dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); | |
882 | ||
883 | err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); | |
884 | if (err) { | |
885 | dev_err(&pdev->dev, "ACPI resource conflict!\n"); | |
886 | return err; | |
887 | } | |
888 | ||
889 | err = pci_request_region(pdev, SMBBAR, ismt_driver.name); | |
890 | if (err) { | |
891 | dev_err(&pdev->dev, | |
892 | "Failed to request SMBus region 0x%lx-0x%lx\n", | |
893 | start, start + len); | |
894 | return err; | |
895 | } | |
896 | ||
897 | priv->smba = pcim_iomap(pdev, SMBBAR, len); | |
898 | if (!priv->smba) { | |
899 | dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); | |
600ca080 | 900 | return -ENODEV; |
13f35ac1 NH |
901 | } |
902 | ||
903 | if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || | |
904 | (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { | |
905 | if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || | |
906 | (pci_set_consistent_dma_mask(pdev, | |
907 | DMA_BIT_MASK(32)) != 0)) { | |
908 | dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", | |
909 | pdev); | |
600ca080 | 910 | return -ENODEV; |
13f35ac1 NH |
911 | } |
912 | } | |
913 | ||
914 | err = ismt_dev_init(priv); | |
915 | if (err) | |
600ca080 | 916 | return err; |
13f35ac1 NH |
917 | |
918 | ismt_hw_init(priv); | |
919 | ||
920 | err = ismt_int_init(priv); | |
921 | if (err) | |
600ca080 | 922 | return err; |
13f35ac1 NH |
923 | |
924 | err = i2c_add_adapter(&priv->adapter); | |
925 | if (err) { | |
926 | dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n"); | |
600ca080 | 927 | return -ENODEV; |
13f35ac1 NH |
928 | } |
929 | return 0; | |
13f35ac1 NH |
930 | } |
931 | ||
932 | /** | |
933 | * ismt_remove() - release driver resources | |
934 | * @pdev: PCI-Express device | |
935 | */ | |
936 | static void ismt_remove(struct pci_dev *pdev) | |
937 | { | |
938 | struct ismt_priv *priv = pci_get_drvdata(pdev); | |
939 | ||
940 | i2c_del_adapter(&priv->adapter); | |
13f35ac1 NH |
941 | } |
942 | ||
13f35ac1 NH |
943 | static struct pci_driver ismt_driver = { |
944 | .name = "ismt_smbus", | |
945 | .id_table = ismt_ids, | |
946 | .probe = ismt_probe, | |
947 | .remove = ismt_remove, | |
13f35ac1 NH |
948 | }; |
949 | ||
950 | module_pci_driver(ismt_driver); | |
951 | ||
952 | MODULE_LICENSE("Dual BSD/GPL"); | |
953 | MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); | |
954 | MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); |