[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-mpc.c

/*
 * (C) Copyright 2003-2004
 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.

 * This is a combined i2c adapter and algorithm driver for the
 * MPC107/Tsi107 PowerPC northbridge and processors that include
 * the same I2C unit (8240, 8245, 85xx).
 *
 * Release 0.8
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <linux/fsl_devices.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/delay.h>

#define MPC_I2C_ADDR  0x00
#define MPC_I2C_FDR 	0x04
#define MPC_I2C_CR	0x08
#define MPC_I2C_SR	0x0c
#define MPC_I2C_DR	0x10
#define MPC_I2C_DFSRR 0x14
#define MPC_I2C_REGION 0x20

#define CCR_MEN  0x80
#define CCR_MIEN 0x40
#define CCR_MSTA 0x20
#define CCR_MTX  0x10
#define CCR_TXAK 0x08
#define CCR_RSTA 0x04

#define CSR_MCF  0x80
#define CSR_MAAS 0x40
#define CSR_MBB  0x20
#define CSR_MAL  0x10
#define CSR_SRW  0x04
#define CSR_MIF  0x02
#define CSR_RXAK 0x01

struct mpc_i2c {
	void __iomem *base;
	u32 interrupt;
	wait_queue_head_t queue;
	struct i2c_adapter adap;
	int irq;
	u32 flags;
};

static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
{
	writeb(x, i2c->base + MPC_I2C_CR);
}

static irqreturn_t mpc_i2c_isr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct mpc_i2c *i2c = dev_id;
	if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
		/* Read again to allow register to stabilise */
		i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
		writeb(0, i2c->base + MPC_I2C_SR);
		wake_up_interruptible(&i2c->queue);
	}
	return IRQ_HANDLED;
}

static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
{
	unsigned long orig_jiffies = jiffies;
	u32 x;
	int result = 0;

	if (i2c->irq == 0)
	{
		while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
			schedule();
			if (time_after(jiffies, orig_jiffies + timeout)) {
				pr_debug("I2C: timeout\n");
				result = -EIO;
				break;
			}
		}
		x = readb(i2c->base + MPC_I2C_SR);
		writeb(0, i2c->base + MPC_I2C_SR);
	} else {
		/* Interrupt mode */
		result = wait_event_interruptible_timeout(i2c->queue,
			(i2c->interrupt & CSR_MIF), timeout * HZ);

		if (unlikely(result < 0))
			pr_debug("I2C: wait interrupted\n");
		else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
			pr_debug("I2C: wait timeout\n");
			result = -ETIMEDOUT;
		}

		x = i2c->interrupt;
		i2c->interrupt = 0;
	}

	if (result < 0)
		return result;

	if (!(x & CSR_MCF)) {
		pr_debug("I2C: unfinished\n");
		return -EIO;
	}

	if (x & CSR_MAL) {
		pr_debug("I2C: MAL\n");
		return -EIO;
	}

	if (writing && (x & CSR_RXAK)) {
		pr_debug("I2C: No RXAK\n");
		/* generate stop */
		writeccr(i2c, CCR_MEN);
		return -EIO;
	}
	return 0;
}

static void mpc_i2c_setclock(struct mpc_i2c *i2c)
{
	/* Set clock and filters */
	if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
		writeb(0x31, i2c->base + MPC_I2C_FDR);
		writeb(0x10, i2c->base + MPC_I2C_DFSRR);
	} else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
		writeb(0x3f, i2c->base + MPC_I2C_FDR);
	else
		writel(0x1031, i2c->base + MPC_I2C_FDR);
}

static void mpc_i2c_start(struct mpc_i2c *i2c)
{
	/* Clear arbitration */
	writeb(0, i2c->base + MPC_I2C_SR);
	/* Start with MEN */
	writeccr(i2c, CCR_MEN);
}

static void mpc_i2c_stop(struct mpc_i2c *i2c)
{
	writeccr(i2c, CCR_MEN);
}

static int mpc_write(struct mpc_i2c *i2c, int target,
		     const u8 * data, int length, int restart)
{
	int i;
	unsigned timeout = i2c->adap.timeout;
	u32 flags = restart ? CCR_RSTA : 0;

	/* Start with MEN */
	if (!restart)
		writeccr(i2c, CCR_MEN);
	/* Start as master */
	writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
	/* Write target byte */
	writeb((target << 1), i2c->base + MPC_I2C_DR);

	if (i2c_wait(i2c, timeout, 1) < 0)
		return -1;

	for (i = 0; i < length; i++) {
		/* Write data byte */
		writeb(data[i], i2c->base + MPC_I2C_DR);

		if (i2c_wait(i2c, timeout, 1) < 0)
			return -1;
	}

	return 0;
}

static int mpc_read(struct mpc_i2c *i2c, int target,
		    u8 * data, int length, int restart)
{
	unsigned timeout = i2c->adap.timeout;
	int i;
	u32 flags = restart ? CCR_RSTA : 0;

	/* Start with MEN */
	if (!restart)
		writeccr(i2c, CCR_MEN);
	/* Switch to read - restart */
	writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
	/* Write target address byte - this time with the read flag set */
	writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);

	if (i2c_wait(i2c, timeout, 1) < 0)
		return -1;

	if (length) {
		if (length == 1)
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
		else
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
		/* Dummy read */
		readb(i2c->base + MPC_I2C_DR);
	}

	for (i = 0; i < length; i++) {
		if (i2c_wait(i2c, timeout, 0) < 0)
			return -1;

		/* Generate txack on next to last byte */
		if (i == length - 2)
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
		/* Generate stop on last byte */
		if (i == length - 1)
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
		data[i] = readb(i2c->base + MPC_I2C_DR);
	}

	return length;
}

static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct i2c_msg *pmsg;
	int i;
	int ret = 0;
	unsigned long orig_jiffies = jiffies;
	struct mpc_i2c *i2c = i2c_get_adapdata(adap);

	mpc_i2c_start(i2c);

	/* Allow bus up to 1s to become not busy */
	while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
		if (signal_pending(current)) {
			pr_debug("I2C: Interrupted\n");
			return -EINTR;
		}
		if (time_after(jiffies, orig_jiffies + HZ)) {
			pr_debug("I2C: timeout\n");
			return -EIO;
		}
		schedule();
	}

	for (i = 0; ret >= 0 && i < num; i++) {
		pmsg = &msgs[i];
		pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
			 pmsg->flags & I2C_M_RD ? "read" : "write",
			 pmsg->len, pmsg->addr, i + 1, num);
		if (pmsg->flags & I2C_M_RD)
			ret =
			    mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
		else
			ret =
			    mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
	}
	mpc_i2c_stop(i2c);
	return (ret < 0) ? ret : num;
}

static u32 mpc_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm mpc_algo = {
	.master_xfer = mpc_xfer,
	.functionality = mpc_functionality,
};

static struct i2c_adapter mpc_ops = {
	.owner = THIS_MODULE,
	.name = "MPC adapter",
	.id = I2C_ALGO_MPC107 | I2C_HW_MPC107,
	.algo = &mpc_algo,
	.class = I2C_CLASS_HWMON,
	.timeout = 1,
	.retries = 1
};

static int fsl_i2c_probe(struct device *device)
{
	int result = 0;
	struct mpc_i2c *i2c;
	struct platform_device *pdev = to_platform_device(device);
	struct fsl_i2c_platform_data *pdata;
	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;

	if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
		return -ENOMEM;
	}
	memset(i2c, 0, sizeof(*i2c));

	i2c->irq = platform_get_irq(pdev, 0);
	i2c->flags = pdata->device_flags;
	init_waitqueue_head(&i2c->queue);

	i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);

	if (!i2c->base) {
		printk(KERN_ERR "i2c-mpc - failed to map controller\n");
		result = -ENOMEM;
		goto fail_map;
	}

	if (i2c->irq != 0)
		if ((result = request_irq(i2c->irq, mpc_i2c_isr,
					  SA_SHIRQ, "i2c-mpc", i2c)) < 0) {
			printk(KERN_ERR
			       "i2c-mpc - failed to attach interrupt\n");
			goto fail_irq;
		}

	mpc_i2c_setclock(i2c);
	dev_set_drvdata(device, i2c);

	i2c->adap = mpc_ops;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
	if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
		printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
		goto fail_add;
	}

	return result;

      fail_add:
	if (i2c->irq != 0)
		free_irq(i2c->irq, NULL);
      fail_irq:
	iounmap(i2c->base);
      fail_map:
	kfree(i2c);
	return result;
};

static int fsl_i2c_remove(struct device *device)
{
	struct mpc_i2c *i2c = dev_get_drvdata(device);

	i2c_del_adapter(&i2c->adap);
	dev_set_drvdata(device, NULL);

	if (i2c->irq != 0)
		free_irq(i2c->irq, i2c);

	iounmap(i2c->base);
	kfree(i2c);
	return 0;
};

/* Structure for a device driver */
static struct device_driver fsl_i2c_driver = {
	.name = "fsl-i2c",
	.bus = &platform_bus_type,
	.probe = fsl_i2c_probe,
	.remove = fsl_i2c_remove,
};

static int __init fsl_i2c_init(void)
{
	return driver_register(&fsl_i2c_driver);
}

static void __exit fsl_i2c_exit(void)
{
	driver_unregister(&fsl_i2c_driver);
}

module_init(fsl_i2c_init);
module_exit(fsl_i2c_exit);

MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
MODULE_DESCRIPTION
    ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) Copyright 2003-2004
	3	* Humboldt Solutions Ltd, adrian@humboldt.co.uk.
	4
	5	* This is a combined i2c adapter and algorithm driver for the
	6	* MPC107/Tsi107 PowerPC northbridge and processors that include
	7	* the same I2C unit (8240, 8245, 85xx).
	8	*
	9	* Release 0.8
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/config.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/sched.h>
	20	#include <linux/init.h>
	21	#include <linux/pci.h>
	22	#include <asm/io.h>
1da177e4	23	#include <linux/fsl_devices.h>
1da177e4 LT	24	#include <linux/i2c.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/delay.h>
	27
	28	#define MPC_I2C_ADDR 0x00
	29	#define MPC_I2C_FDR 0x04
	30	#define MPC_I2C_CR 0x08
	31	#define MPC_I2C_SR 0x0c
	32	#define MPC_I2C_DR 0x10
	33	#define MPC_I2C_DFSRR 0x14
	34	#define MPC_I2C_REGION 0x20
	35
	36	#define CCR_MEN 0x80
	37	#define CCR_MIEN 0x40
	38	#define CCR_MSTA 0x20
	39	#define CCR_MTX 0x10
	40	#define CCR_TXAK 0x08
	41	#define CCR_RSTA 0x04
	42
	43	#define CSR_MCF 0x80
	44	#define CSR_MAAS 0x40
	45	#define CSR_MBB 0x20
	46	#define CSR_MAL 0x10
	47	#define CSR_SRW 0x04
	48	#define CSR_MIF 0x02
	49	#define CSR_RXAK 0x01
	50
	51	struct mpc_i2c {
7366d36c	52	void __iomem *base;
1da177e4 LT	53	u32 interrupt;
	54	wait_queue_head_t queue;
	55	struct i2c_adapter adap;
	56	int irq;
	57	u32 flags;
	58	};
	59
	60	static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
	61	{
	62	writeb(x, i2c->base + MPC_I2C_CR);
	63	}
	64
	65	static irqreturn_t mpc_i2c_isr(int irq, void dev_id, struct pt_regs regs)
	66	{
	67	struct mpc_i2c *i2c = dev_id;
	68	if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
	69	/* Read again to allow register to stabilise */
	70	i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
	71	writeb(0, i2c->base + MPC_I2C_SR);
	72	wake_up_interruptible(&i2c->queue);
	73	}
	74	return IRQ_HANDLED;
	75	}
	76
	77	static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
	78	{
	79	unsigned long orig_jiffies = jiffies;
	80	u32 x;
	81	int result = 0;
	82
	83	if (i2c->irq == 0)
	84	{
	85	while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
	86	schedule();
	87	if (time_after(jiffies, orig_jiffies + timeout)) {
	88	pr_debug("I2C: timeout\n");
	89	result = -EIO;
	90	break;
	91	}
	92	}
	93	x = readb(i2c->base + MPC_I2C_SR);
	94	writeb(0, i2c->base + MPC_I2C_SR);
	95	} else {
	96	/* Interrupt mode */
	97	result = wait_event_interruptible_timeout(i2c->queue,
	98	(i2c->interrupt & CSR_MIF), timeout * HZ);
	99
	100	if (unlikely(result < 0))
	101	pr_debug("I2C: wait interrupted\n");
	102	else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
	103	pr_debug("I2C: wait timeout\n");
	104	result = -ETIMEDOUT;
	105	}
	106
	107	x = i2c->interrupt;
	108	i2c->interrupt = 0;
	109	}
	110
	111	if (result < 0)
	112	return result;
	113
	114	if (!(x & CSR_MCF)) {
	115	pr_debug("I2C: unfinished\n");
	116	return -EIO;
117	}
118
119	if (x & CSR_MAL) {
120	pr_debug("I2C: MAL\n");
121	return -EIO;
122	}
123
124	if (writing && (x & CSR_RXAK)) {
125	pr_debug("I2C: No RXAK\n");
126	/* generate stop */
127	writeccr(i2c, CCR_MEN);
128	return -EIO;
129	}
130	return 0;
131	}
132
133	static void mpc_i2c_setclock(struct mpc_i2c *i2c)
134	{
135	/* Set clock and filters */
136	if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
137	writeb(0x31, i2c->base + MPC_I2C_FDR);
138	writeb(0x10, i2c->base + MPC_I2C_DFSRR);
139	} else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
140	writeb(0x3f, i2c->base + MPC_I2C_FDR);
141	else
142	writel(0x1031, i2c->base + MPC_I2C_FDR);
143	}
144
145	static void mpc_i2c_start(struct mpc_i2c *i2c)
146	{
147	/* Clear arbitration */
148	writeb(0, i2c->base + MPC_I2C_SR);
149	/* Start with MEN */
150	writeccr(i2c, CCR_MEN);
151	}
152
153	static void mpc_i2c_stop(struct mpc_i2c *i2c)
154	{
155	writeccr(i2c, CCR_MEN);
156	}
157
158	static int mpc_write(struct mpc_i2c *i2c, int target,
159	const u8 * data, int length, int restart)
160	{
161	int i;
162	unsigned timeout = i2c->adap.timeout;
163	u32 flags = restart ? CCR_RSTA : 0;
164
165	/* Start with MEN */
166	if (!restart)
167	writeccr(i2c, CCR_MEN);
168	/* Start as master */
169	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_MTX \| flags);
170	/* Write target byte */
171	writeb((target << 1), i2c->base + MPC_I2C_DR);
172
173	if (i2c_wait(i2c, timeout, 1) < 0)
174	return -1;
175
176	for (i = 0; i < length; i++) {
177	/* Write data byte */
178	writeb(data[i], i2c->base + MPC_I2C_DR);
179
180	if (i2c_wait(i2c, timeout, 1) < 0)
181	return -1;
182	}
183
184	return 0;
185	}
186
187	static int mpc_read(struct mpc_i2c *i2c, int target,
188	u8 * data, int length, int restart)
189	{
190	unsigned timeout = i2c->adap.timeout;
191	int i;
192	u32 flags = restart ? CCR_RSTA : 0;
193
194	/* Start with MEN */
195	if (!restart)
196	writeccr(i2c, CCR_MEN);
197	/* Switch to read - restart */
198	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_MTX \| flags);
199	/* Write target address byte - this time with the read flag set */
200	writeb((target << 1) \| 1, i2c->base + MPC_I2C_DR);
201
202	if (i2c_wait(i2c, timeout, 1) < 0)
203	return -1;
204
205	if (length) {
206	if (length == 1)
207	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_TXAK);
208	else
209	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA);
210	/* Dummy read */
211	readb(i2c->base + MPC_I2C_DR);
212	}
213
214	for (i = 0; i < length; i++) {
215	if (i2c_wait(i2c, timeout, 0) < 0)
216	return -1;
217
218	/* Generate txack on next to last byte */
219	if (i == length - 2)
220	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_TXAK);
221	/* Generate stop on last byte */
222	if (i == length - 1)
223	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_TXAK);
224	data[i] = readb(i2c->base + MPC_I2C_DR);
225	}
226
227	return length;
228	}
229
230	static int mpc_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
231	{
232	struct i2c_msg *pmsg;
233	int i;
234	int ret = 0;
235	unsigned long orig_jiffies = jiffies;
236	struct mpc_i2c *i2c = i2c_get_adapdata(adap);
237
238	mpc_i2c_start(i2c);
239
240	/* Allow bus up to 1s to become not busy */
241	while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
242	if (signal_pending(current)) {
243	pr_debug("I2C: Interrupted\n");
244	return -EINTR;
245	}
246	if (time_after(jiffies, orig_jiffies + HZ)) {
247	pr_debug("I2C: timeout\n");
248	return -EIO;
249	}
250	schedule();
251	}
252
253	for (i = 0; ret >= 0 && i < num; i++) {
254	pmsg = &msgs[i];
255	pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
256	pmsg->flags & I2C_M_RD ? "read" : "write",
257	pmsg->len, pmsg->addr, i + 1, num);
258	if (pmsg->flags & I2C_M_RD)
259	ret =
260	mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
261	else
262	ret =
263	mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
264	}
265	mpc_i2c_stop(i2c);
266	return (ret < 0) ? ret : num;
267	}
268
269	static u32 mpc_functionality(struct i2c_adapter *adap)
270	{
271	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
272	}
273
274	static struct i2c_algorithm mpc_algo = {
1da177e4 LT	275	.master_xfer = mpc_xfer,
	276	.functionality = mpc_functionality,
	277	};
	278
	279	static struct i2c_adapter mpc_ops = {
	280	.owner = THIS_MODULE,
	281	.name = "MPC adapter",
	282	.id = I2C_ALGO_MPC107 \| I2C_HW_MPC107,
	283	.algo = &mpc_algo,
	284	.class = I2C_CLASS_HWMON,
	285	.timeout = 1,
	286	.retries = 1
	287	};
	288
8c86cb12 KG	289	static int fsl_i2c_probe(struct device *device)
	290	{
	291	int result = 0;
	292	struct mpc_i2c *i2c;
	293	struct platform_device *pdev = to_platform_device(device);
	294	struct fsl_i2c_platform_data *pdata;
	295	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	296
	297	pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
	298
	299	if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
	300	return -ENOMEM;
	301	}
	302	memset(i2c, 0, sizeof(*i2c));
	303
	304	i2c->irq = platform_get_irq(pdev, 0);
	305	i2c->flags = pdata->device_flags;
	306	init_waitqueue_head(&i2c->queue);
	307
	308	i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
	309
	310	if (!i2c->base) {
	311	printk(KERN_ERR "i2c-mpc - failed to map controller\n");
	312	result = -ENOMEM;
	313	goto fail_map;
	314	}
	315
	316	if (i2c->irq != 0)
	317	if ((result = request_irq(i2c->irq, mpc_i2c_isr,
	318	SA_SHIRQ, "i2c-mpc", i2c)) < 0) {
	319	printk(KERN_ERR
	320	"i2c-mpc - failed to attach interrupt\n");
	321	goto fail_irq;
	322	}
	323
	324	mpc_i2c_setclock(i2c);
	325	dev_set_drvdata(device, i2c);
	326
	327	i2c->adap = mpc_ops;
	328	i2c_set_adapdata(&i2c->adap, i2c);
	329	i2c->adap.dev.parent = &pdev->dev;
	330	if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
	331	printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
	332	goto fail_add;
	333	}
	334
	335	return result;
	336
	337	fail_add:
	338	if (i2c->irq != 0)
	339	free_irq(i2c->irq, NULL);
	340	fail_irq:
	341	iounmap(i2c->base);
	342	fail_map:
	343	kfree(i2c);
	344	return result;
	345	};
	346
	347	static int fsl_i2c_remove(struct device *device)
	348	{
	349	struct mpc_i2c *i2c = dev_get_drvdata(device);
	350
	351	i2c_del_adapter(&i2c->adap);
	352	dev_set_drvdata(device, NULL);
353
354	if (i2c->irq != 0)
355	free_irq(i2c->irq, i2c);
356
357	iounmap(i2c->base);
358	kfree(i2c);
359	return 0;
360	};
361
362	/* Structure for a device driver */
363	static struct device_driver fsl_i2c_driver = {
364	.name = "fsl-i2c",
365	.bus = &platform_bus_type,
366	.probe = fsl_i2c_probe,
367	.remove = fsl_i2c_remove,
368	};
369
370	static int __init fsl_i2c_init(void)
371	{
372	return driver_register(&fsl_i2c_driver);
373	}
374
375	static void __exit fsl_i2c_exit(void)
376	{
377	driver_unregister(&fsl_i2c_driver);
378	}
379
380	module_init(fsl_i2c_init);
381	module_exit(fsl_i2c_exit);
382
1da177e4 LT	383	MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
	384	MODULE_DESCRIPTION
	385	("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
	386	MODULE_LICENSE("GPL");