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Commit | Line | Data |
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1da177e4 | 1 | /* |
a0832798 TP |
2 | * Driver for the i2c controller on the Marvell line of host bridges |
3 | * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). | |
1da177e4 LT |
4 | * |
5 | * Author: Mark A. Greer <mgreer@mvista.com> | |
6 | * | |
7 | * 2005 (c) MontaVista, Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/i2c.h> | |
17 | #include <linux/interrupt.h> | |
a0832798 | 18 | #include <linux/mv643xx_i2c.h> |
d052d1be RK |
19 | #include <linux/platform_device.h> |
20 | ||
1da177e4 LT |
21 | #include <asm/io.h> |
22 | ||
23 | /* Register defines */ | |
24 | #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 | |
25 | #define MV64XXX_I2C_REG_DATA 0x04 | |
26 | #define MV64XXX_I2C_REG_CONTROL 0x08 | |
27 | #define MV64XXX_I2C_REG_STATUS 0x0c | |
28 | #define MV64XXX_I2C_REG_BAUD 0x0c | |
29 | #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 | |
30 | #define MV64XXX_I2C_REG_SOFT_RESET 0x1c | |
31 | ||
32 | #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 | |
33 | #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 | |
34 | #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 | |
35 | #define MV64XXX_I2C_REG_CONTROL_START 0x00000020 | |
36 | #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 | |
37 | #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 | |
38 | ||
39 | /* Ctlr status values */ | |
40 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 | |
41 | #define MV64XXX_I2C_STATUS_MAST_START 0x08 | |
42 | #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 | |
43 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 | |
44 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 | |
45 | #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 | |
46 | #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 | |
47 | #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 | |
48 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 | |
49 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 | |
50 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 | |
51 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 | |
52 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 | |
53 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 | |
54 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 | |
55 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 | |
56 | #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 | |
57 | ||
58 | /* Driver states */ | |
59 | enum { | |
60 | MV64XXX_I2C_STATE_INVALID, | |
61 | MV64XXX_I2C_STATE_IDLE, | |
62 | MV64XXX_I2C_STATE_WAITING_FOR_START_COND, | |
63 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, | |
64 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, | |
65 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, | |
66 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, | |
1da177e4 LT |
67 | }; |
68 | ||
69 | /* Driver actions */ | |
70 | enum { | |
71 | MV64XXX_I2C_ACTION_INVALID, | |
72 | MV64XXX_I2C_ACTION_CONTINUE, | |
73 | MV64XXX_I2C_ACTION_SEND_START, | |
74 | MV64XXX_I2C_ACTION_SEND_ADDR_1, | |
75 | MV64XXX_I2C_ACTION_SEND_ADDR_2, | |
76 | MV64XXX_I2C_ACTION_SEND_DATA, | |
77 | MV64XXX_I2C_ACTION_RCV_DATA, | |
78 | MV64XXX_I2C_ACTION_RCV_DATA_STOP, | |
79 | MV64XXX_I2C_ACTION_SEND_STOP, | |
80 | }; | |
81 | ||
82 | struct mv64xxx_i2c_data { | |
83 | int irq; | |
84 | u32 state; | |
85 | u32 action; | |
e91c021c | 86 | u32 aborting; |
1da177e4 LT |
87 | u32 cntl_bits; |
88 | void __iomem *reg_base; | |
89 | u32 reg_base_p; | |
a0832798 | 90 | u32 reg_size; |
1da177e4 LT |
91 | u32 addr1; |
92 | u32 addr2; | |
93 | u32 bytes_left; | |
94 | u32 byte_posn; | |
95 | u32 block; | |
96 | int rc; | |
97 | u32 freq_m; | |
98 | u32 freq_n; | |
99 | wait_queue_head_t waitq; | |
100 | spinlock_t lock; | |
101 | struct i2c_msg *msg; | |
102 | struct i2c_adapter adapter; | |
103 | }; | |
104 | ||
105 | /* | |
106 | ***************************************************************************** | |
107 | * | |
108 | * Finite State Machine & Interrupt Routines | |
109 | * | |
110 | ***************************************************************************** | |
111 | */ | |
a07ad1cc DF |
112 | |
113 | /* Reset hardware and initialize FSM */ | |
114 | static void | |
115 | mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) | |
116 | { | |
117 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); | |
118 | writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), | |
119 | drv_data->reg_base + MV64XXX_I2C_REG_BAUD); | |
120 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); | |
121 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); | |
122 | writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, | |
123 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
124 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
125 | } | |
126 | ||
1da177e4 LT |
127 | static void |
128 | mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) | |
129 | { | |
130 | /* | |
131 | * If state is idle, then this is likely the remnants of an old | |
132 | * operation that driver has given up on or the user has killed. | |
133 | * If so, issue the stop condition and go to idle. | |
134 | */ | |
135 | if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { | |
136 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
137 | return; | |
138 | } | |
139 | ||
1da177e4 LT |
140 | /* The status from the ctlr [mostly] tells us what to do next */ |
141 | switch (status) { | |
142 | /* Start condition interrupt */ | |
143 | case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ | |
144 | case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ | |
145 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; | |
146 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; | |
147 | break; | |
148 | ||
149 | /* Performing a write */ | |
150 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ | |
151 | if (drv_data->msg->flags & I2C_M_TEN) { | |
152 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
153 | drv_data->state = | |
154 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
155 | break; | |
156 | } | |
157 | /* FALLTHRU */ | |
158 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ | |
159 | case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ | |
e91c021c MG |
160 | if ((drv_data->bytes_left == 0) |
161 | || (drv_data->aborting | |
162 | && (drv_data->byte_posn != 0))) { | |
163 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
164 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
165 | } else { | |
1da177e4 LT |
166 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; |
167 | drv_data->state = | |
168 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
169 | drv_data->bytes_left--; | |
1da177e4 LT |
170 | } |
171 | break; | |
172 | ||
173 | /* Performing a read */ | |
174 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ | |
175 | if (drv_data->msg->flags & I2C_M_TEN) { | |
176 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
177 | drv_data->state = | |
178 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
179 | break; | |
180 | } | |
181 | /* FALLTHRU */ | |
182 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ | |
183 | if (drv_data->bytes_left == 0) { | |
184 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
185 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
186 | break; | |
187 | } | |
188 | /* FALLTHRU */ | |
189 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ | |
190 | if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) | |
191 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
192 | else { | |
193 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; | |
194 | drv_data->bytes_left--; | |
195 | } | |
196 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
197 | ||
e91c021c | 198 | if ((drv_data->bytes_left == 1) || drv_data->aborting) |
1da177e4 LT |
199 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; |
200 | break; | |
201 | ||
202 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ | |
203 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; | |
204 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
205 | break; | |
206 | ||
207 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ | |
208 | case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ | |
209 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ | |
210 | /* Doesn't seem to be a device at other end */ | |
211 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
212 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
213 | drv_data->rc = -ENODEV; | |
214 | break; | |
215 | ||
216 | default: | |
217 | dev_err(&drv_data->adapter.dev, | |
218 | "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " | |
219 | "status: 0x%x, addr: 0x%x, flags: 0x%x\n", | |
220 | drv_data->state, status, drv_data->msg->addr, | |
221 | drv_data->msg->flags); | |
222 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
a07ad1cc | 223 | mv64xxx_i2c_hw_init(drv_data); |
1da177e4 LT |
224 | drv_data->rc = -EIO; |
225 | } | |
226 | } | |
227 | ||
228 | static void | |
229 | mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) | |
230 | { | |
231 | switch(drv_data->action) { | |
232 | case MV64XXX_I2C_ACTION_CONTINUE: | |
233 | writel(drv_data->cntl_bits, | |
234 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
235 | break; | |
236 | ||
237 | case MV64XXX_I2C_ACTION_SEND_START: | |
238 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, | |
239 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
240 | break; | |
241 | ||
242 | case MV64XXX_I2C_ACTION_SEND_ADDR_1: | |
243 | writel(drv_data->addr1, | |
244 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
245 | writel(drv_data->cntl_bits, | |
246 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
247 | break; | |
248 | ||
249 | case MV64XXX_I2C_ACTION_SEND_ADDR_2: | |
250 | writel(drv_data->addr2, | |
251 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
252 | writel(drv_data->cntl_bits, | |
253 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
254 | break; | |
255 | ||
256 | case MV64XXX_I2C_ACTION_SEND_DATA: | |
257 | writel(drv_data->msg->buf[drv_data->byte_posn++], | |
258 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
259 | writel(drv_data->cntl_bits, | |
260 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
261 | break; | |
262 | ||
263 | case MV64XXX_I2C_ACTION_RCV_DATA: | |
264 | drv_data->msg->buf[drv_data->byte_posn++] = | |
265 | readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
266 | writel(drv_data->cntl_bits, | |
267 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
268 | break; | |
269 | ||
270 | case MV64XXX_I2C_ACTION_RCV_DATA_STOP: | |
271 | drv_data->msg->buf[drv_data->byte_posn++] = | |
272 | readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
273 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
274 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
275 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
276 | drv_data->block = 0; | |
277 | wake_up_interruptible(&drv_data->waitq); | |
278 | break; | |
279 | ||
280 | case MV64XXX_I2C_ACTION_INVALID: | |
281 | default: | |
282 | dev_err(&drv_data->adapter.dev, | |
283 | "mv64xxx_i2c_do_action: Invalid action: %d\n", | |
284 | drv_data->action); | |
285 | drv_data->rc = -EIO; | |
286 | /* FALLTHRU */ | |
287 | case MV64XXX_I2C_ACTION_SEND_STOP: | |
288 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
289 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
290 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
291 | drv_data->block = 0; | |
292 | wake_up_interruptible(&drv_data->waitq); | |
293 | break; | |
294 | } | |
295 | } | |
296 | ||
b0999cc5 | 297 | static irqreturn_t |
7d12e780 | 298 | mv64xxx_i2c_intr(int irq, void *dev_id) |
1da177e4 LT |
299 | { |
300 | struct mv64xxx_i2c_data *drv_data = dev_id; | |
301 | unsigned long flags; | |
302 | u32 status; | |
b0999cc5 | 303 | irqreturn_t rc = IRQ_NONE; |
1da177e4 LT |
304 | |
305 | spin_lock_irqsave(&drv_data->lock, flags); | |
306 | while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & | |
307 | MV64XXX_I2C_REG_CONTROL_IFLG) { | |
308 | status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); | |
309 | mv64xxx_i2c_fsm(drv_data, status); | |
310 | mv64xxx_i2c_do_action(drv_data); | |
311 | rc = IRQ_HANDLED; | |
312 | } | |
313 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
314 | ||
315 | return rc; | |
316 | } | |
317 | ||
318 | /* | |
319 | ***************************************************************************** | |
320 | * | |
321 | * I2C Msg Execution Routines | |
322 | * | |
323 | ***************************************************************************** | |
324 | */ | |
325 | static void | |
326 | mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, | |
327 | struct i2c_msg *msg) | |
328 | { | |
329 | u32 dir = 0; | |
330 | ||
331 | drv_data->msg = msg; | |
332 | drv_data->byte_posn = 0; | |
333 | drv_data->bytes_left = msg->len; | |
e91c021c | 334 | drv_data->aborting = 0; |
1da177e4 LT |
335 | drv_data->rc = 0; |
336 | drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | | |
337 | MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; | |
338 | ||
339 | if (msg->flags & I2C_M_RD) | |
340 | dir = 1; | |
341 | ||
1da177e4 LT |
342 | if (msg->flags & I2C_M_TEN) { |
343 | drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; | |
344 | drv_data->addr2 = (u32)msg->addr & 0xff; | |
345 | } else { | |
346 | drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; | |
347 | drv_data->addr2 = 0; | |
348 | } | |
349 | } | |
350 | ||
351 | static void | |
352 | mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) | |
353 | { | |
354 | long time_left; | |
355 | unsigned long flags; | |
356 | char abort = 0; | |
357 | ||
358 | time_left = wait_event_interruptible_timeout(drv_data->waitq, | |
8a52c6b4 | 359 | !drv_data->block, drv_data->adapter.timeout); |
1da177e4 LT |
360 | |
361 | spin_lock_irqsave(&drv_data->lock, flags); | |
362 | if (!time_left) { /* Timed out */ | |
363 | drv_data->rc = -ETIMEDOUT; | |
364 | abort = 1; | |
365 | } else if (time_left < 0) { /* Interrupted/Error */ | |
366 | drv_data->rc = time_left; /* errno value */ | |
367 | abort = 1; | |
368 | } | |
369 | ||
370 | if (abort && drv_data->block) { | |
e91c021c | 371 | drv_data->aborting = 1; |
1da177e4 LT |
372 | spin_unlock_irqrestore(&drv_data->lock, flags); |
373 | ||
374 | time_left = wait_event_timeout(drv_data->waitq, | |
8a52c6b4 | 375 | !drv_data->block, drv_data->adapter.timeout); |
1da177e4 | 376 | |
e91c021c | 377 | if ((time_left <= 0) && drv_data->block) { |
1da177e4 LT |
378 | drv_data->state = MV64XXX_I2C_STATE_IDLE; |
379 | dev_err(&drv_data->adapter.dev, | |
e91c021c MG |
380 | "mv64xxx: I2C bus locked, block: %d, " |
381 | "time_left: %d\n", drv_data->block, | |
382 | (int)time_left); | |
a07ad1cc | 383 | mv64xxx_i2c_hw_init(drv_data); |
1da177e4 LT |
384 | } |
385 | } else | |
386 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
387 | } | |
388 | ||
389 | static int | |
390 | mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg) | |
391 | { | |
392 | unsigned long flags; | |
393 | ||
394 | spin_lock_irqsave(&drv_data->lock, flags); | |
395 | mv64xxx_i2c_prepare_for_io(drv_data, msg); | |
396 | ||
397 | if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ | |
398 | if (drv_data->msg->flags & I2C_M_RD) { | |
399 | /* No action to do, wait for slave to send a byte */ | |
400 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
401 | drv_data->state = | |
402 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
403 | } else { | |
404 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; | |
405 | drv_data->state = | |
406 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
407 | drv_data->bytes_left--; | |
408 | } | |
409 | } else { | |
410 | drv_data->action = MV64XXX_I2C_ACTION_SEND_START; | |
411 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; | |
412 | } | |
413 | ||
414 | drv_data->block = 1; | |
415 | mv64xxx_i2c_do_action(drv_data); | |
416 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
417 | ||
418 | mv64xxx_i2c_wait_for_completion(drv_data); | |
419 | return drv_data->rc; | |
420 | } | |
421 | ||
422 | /* | |
423 | ***************************************************************************** | |
424 | * | |
425 | * I2C Core Support Routines (Interface to higher level I2C code) | |
426 | * | |
427 | ***************************************************************************** | |
428 | */ | |
429 | static u32 | |
430 | mv64xxx_i2c_functionality(struct i2c_adapter *adap) | |
431 | { | |
432 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; | |
433 | } | |
434 | ||
435 | static int | |
436 | mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
437 | { | |
438 | struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); | |
d1b2f0a9 | 439 | int i, rc; |
1da177e4 LT |
440 | |
441 | for (i=0; i<num; i++) | |
d1b2f0a9 JD |
442 | if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0) |
443 | return rc; | |
1da177e4 | 444 | |
d1b2f0a9 | 445 | return num; |
1da177e4 LT |
446 | } |
447 | ||
8f9082c5 | 448 | static const struct i2c_algorithm mv64xxx_i2c_algo = { |
1da177e4 LT |
449 | .master_xfer = mv64xxx_i2c_xfer, |
450 | .functionality = mv64xxx_i2c_functionality, | |
451 | }; | |
452 | ||
453 | /* | |
454 | ***************************************************************************** | |
455 | * | |
456 | * Driver Interface & Early Init Routines | |
457 | * | |
458 | ***************************************************************************** | |
459 | */ | |
1da177e4 LT |
460 | static int __devinit |
461 | mv64xxx_i2c_map_regs(struct platform_device *pd, | |
462 | struct mv64xxx_i2c_data *drv_data) | |
463 | { | |
a0832798 TP |
464 | int size; |
465 | struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0); | |
1da177e4 | 466 | |
a0832798 TP |
467 | if (!r) |
468 | return -ENODEV; | |
1da177e4 | 469 | |
c6ffddea | 470 | size = resource_size(r); |
a0832798 TP |
471 | |
472 | if (!request_mem_region(r->start, size, drv_data->adapter.name)) | |
473 | return -EBUSY; | |
474 | ||
475 | drv_data->reg_base = ioremap(r->start, size); | |
476 | drv_data->reg_base_p = r->start; | |
477 | drv_data->reg_size = size; | |
1da177e4 LT |
478 | |
479 | return 0; | |
480 | } | |
481 | ||
bdf602bd | 482 | static void |
1da177e4 LT |
483 | mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) |
484 | { | |
485 | if (drv_data->reg_base) { | |
486 | iounmap(drv_data->reg_base); | |
a0832798 | 487 | release_mem_region(drv_data->reg_base_p, drv_data->reg_size); |
1da177e4 LT |
488 | } |
489 | ||
490 | drv_data->reg_base = NULL; | |
491 | drv_data->reg_base_p = 0; | |
492 | } | |
493 | ||
494 | static int __devinit | |
3ae5eaec | 495 | mv64xxx_i2c_probe(struct platform_device *pd) |
1da177e4 | 496 | { |
1da177e4 | 497 | struct mv64xxx_i2c_data *drv_data; |
3ae5eaec | 498 | struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; |
1da177e4 LT |
499 | int rc; |
500 | ||
501 | if ((pd->id != 0) || !pdata) | |
502 | return -ENODEV; | |
503 | ||
5263ebb5 | 504 | drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); |
1da177e4 LT |
505 | if (!drv_data) |
506 | return -ENOMEM; | |
507 | ||
1da177e4 LT |
508 | if (mv64xxx_i2c_map_regs(pd, drv_data)) { |
509 | rc = -ENODEV; | |
510 | goto exit_kfree; | |
511 | } | |
512 | ||
e91c021c | 513 | strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", |
2096b956 | 514 | sizeof(drv_data->adapter.name)); |
1da177e4 LT |
515 | |
516 | init_waitqueue_head(&drv_data->waitq); | |
517 | spin_lock_init(&drv_data->lock); | |
518 | ||
519 | drv_data->freq_m = pdata->freq_m; | |
520 | drv_data->freq_n = pdata->freq_n; | |
521 | drv_data->irq = platform_get_irq(pd, 0); | |
48944738 DV |
522 | if (drv_data->irq < 0) { |
523 | rc = -ENXIO; | |
524 | goto exit_unmap_regs; | |
525 | } | |
12a917f6 | 526 | drv_data->adapter.dev.parent = &pd->dev; |
1da177e4 LT |
527 | drv_data->adapter.algo = &mv64xxx_i2c_algo; |
528 | drv_data->adapter.owner = THIS_MODULE; | |
3401b2ff | 529 | drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
8a52c6b4 | 530 | drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); |
65b22ad9 | 531 | drv_data->adapter.nr = pd->id; |
3ae5eaec | 532 | platform_set_drvdata(pd, drv_data); |
1da177e4 LT |
533 | i2c_set_adapdata(&drv_data->adapter, drv_data); |
534 | ||
3269bb63 MB |
535 | mv64xxx_i2c_hw_init(drv_data); |
536 | ||
1da177e4 | 537 | if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, |
dfded4ae MG |
538 | MV64XXX_I2C_CTLR_NAME, drv_data)) { |
539 | dev_err(&drv_data->adapter.dev, | |
540 | "mv64xxx: Can't register intr handler irq: %d\n", | |
541 | drv_data->irq); | |
1da177e4 LT |
542 | rc = -EINVAL; |
543 | goto exit_unmap_regs; | |
65b22ad9 | 544 | } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { |
dfded4ae MG |
545 | dev_err(&drv_data->adapter.dev, |
546 | "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); | |
1da177e4 LT |
547 | goto exit_free_irq; |
548 | } | |
549 | ||
1da177e4 LT |
550 | return 0; |
551 | ||
552 | exit_free_irq: | |
553 | free_irq(drv_data->irq, drv_data); | |
554 | exit_unmap_regs: | |
555 | mv64xxx_i2c_unmap_regs(drv_data); | |
556 | exit_kfree: | |
557 | kfree(drv_data); | |
558 | return rc; | |
559 | } | |
560 | ||
561 | static int __devexit | |
3ae5eaec | 562 | mv64xxx_i2c_remove(struct platform_device *dev) |
1da177e4 | 563 | { |
3ae5eaec | 564 | struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); |
1da177e4 LT |
565 | int rc; |
566 | ||
567 | rc = i2c_del_adapter(&drv_data->adapter); | |
568 | free_irq(drv_data->irq, drv_data); | |
569 | mv64xxx_i2c_unmap_regs(drv_data); | |
570 | kfree(drv_data); | |
571 | ||
572 | return rc; | |
573 | } | |
574 | ||
3ae5eaec | 575 | static struct platform_driver mv64xxx_i2c_driver = { |
1da177e4 | 576 | .probe = mv64xxx_i2c_probe, |
bdf602bd | 577 | .remove = __devexit_p(mv64xxx_i2c_remove), |
3ae5eaec RK |
578 | .driver = { |
579 | .owner = THIS_MODULE, | |
580 | .name = MV64XXX_I2C_CTLR_NAME, | |
581 | }, | |
1da177e4 LT |
582 | }; |
583 | ||
584 | static int __init | |
585 | mv64xxx_i2c_init(void) | |
586 | { | |
3ae5eaec | 587 | return platform_driver_register(&mv64xxx_i2c_driver); |
1da177e4 LT |
588 | } |
589 | ||
590 | static void __exit | |
591 | mv64xxx_i2c_exit(void) | |
592 | { | |
3ae5eaec | 593 | platform_driver_unregister(&mv64xxx_i2c_driver); |
1da177e4 LT |
594 | } |
595 | ||
596 | module_init(mv64xxx_i2c_init); | |
597 | module_exit(mv64xxx_i2c_exit); | |
598 | ||
599 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); | |
600 | MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); | |
601 | MODULE_LICENSE("GPL"); |