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I2C: mv64xxx: move mv64xxx_i2c_prepare_for_io()
[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-mv64xxx.c
CommitLineData
1da177e4 1/*
a0832798
TP		 2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
1da177e4
LT		 4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/kernel.h>
5a0e3ad6 13#include <linux/slab.h>
1da177e4
LT		 14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
a0832798 18#include <linux/mv643xx_i2c.h>
d052d1be 19#include <linux/platform_device.h>
21782180 20#include <linux/io.h>
b61d1575
AL		 21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_i2c.h>
24#include <linux/clk.h>
25#include <linux/err.h>
1da177e4
LT		 26
27/* Register defines */
28#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
29#define MV64XXX_I2C_REG_DATA 0x04
30#define MV64XXX_I2C_REG_CONTROL 0x08
31#define MV64XXX_I2C_REG_STATUS 0x0c
32#define MV64XXX_I2C_REG_BAUD 0x0c
33#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
34#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
35
36#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
37#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
38#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
39#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
40#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
41#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
42
43/* Ctlr status values */
44#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
45#define MV64XXX_I2C_STATUS_MAST_START 0x08
46#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
47#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
48#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
49#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
50#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
51#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
52#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
53#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
54#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
55#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
56#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
57#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
58#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
59#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
60#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
61
62/* Driver states */
63enum {
64 MV64XXX_I2C_STATE_INVALID,
65 MV64XXX_I2C_STATE_IDLE,
66 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
eda6bee6 67 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
1da177e4
LT		 68 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
69 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
70 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
71 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
1da177e4
LT		 72};
73
74/* Driver actions */
75enum {
76 MV64XXX_I2C_ACTION_INVALID,
77 MV64XXX_I2C_ACTION_CONTINUE,
78 MV64XXX_I2C_ACTION_SEND_START,
eda6bee6 79 MV64XXX_I2C_ACTION_SEND_RESTART,
1da177e4
LT		 80 MV64XXX_I2C_ACTION_SEND_ADDR_1,
81 MV64XXX_I2C_ACTION_SEND_ADDR_2,
82 MV64XXX_I2C_ACTION_SEND_DATA,
83 MV64XXX_I2C_ACTION_RCV_DATA,
84 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
85 MV64XXX_I2C_ACTION_SEND_STOP,
86};
87
88struct mv64xxx_i2c_data {
89 int irq;
90 u32 state;
91 u32 action;
e91c021c 92 u32 aborting;
1da177e4
LT		 93 u32 cntl_bits;
94 void __iomem *reg_base;
1da177e4
LT		 95 u32 addr1;
96 u32 addr2;
97 u32 bytes_left;
98 u32 byte_posn;
eda6bee6 99 u32 send_stop;
1da177e4
LT		 100 u32 block;
101 int rc;
102 u32 freq_m;
103 u32 freq_n;
b61d1575
AL		 104#if defined(CONFIG_HAVE_CLK)
105 struct clk *clk;
106#endif
1da177e4
LT		 107 wait_queue_head_t waitq;
108 spinlock_t lock;
109 struct i2c_msg *msg;
110 struct i2c_adapter adapter;
111};
112
3420afbc
RK		 113static void
114mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
115 struct i2c_msg *msg)
116{
117 u32 dir = 0;
118
119 drv_data->msg = msg;
120 drv_data->byte_posn = 0;
121 drv_data->bytes_left = msg->len;
122 drv_data->aborting = 0;
123 drv_data->rc = 0;
124 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
125 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
126
127 if (msg->flags & I2C_M_RD)
128 dir = 1;
129
130 if (msg->flags & I2C_M_TEN) {
131 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
132 drv_data->addr2 = (u32)msg->addr & 0xff;
133 } else {
134 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
135 drv_data->addr2 = 0;
136 }
137}
138
1da177e4
LT		 139/*
140 *****************************************************************************
141 *
142 * Finite State Machine & Interrupt Routines
143 *
144 *****************************************************************************
145 */
a07ad1cc
DF		 146
147/* Reset hardware and initialize FSM */
148static void
149mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
150{
151 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
152 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
153 drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
154 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
155 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
156 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
157 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
158 drv_data->state = MV64XXX_I2C_STATE_IDLE;
159}
160
1da177e4
LT		 161static void
162mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
163{
164 /*
165 * If state is idle, then this is likely the remnants of an old
166 * operation that driver has given up on or the user has killed.
167 * If so, issue the stop condition and go to idle.
168 */
169 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
170 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
171 return;
172 }
173
1da177e4
LT		 174 /* The status from the ctlr [mostly] tells us what to do next */
175 switch (status) {
176 /* Start condition interrupt */
177 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
178 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
179 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
180 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
181 break;
182
183 /* Performing a write */
184 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
185 if (drv_data->msg->flags & I2C_M_TEN) {
186 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
187 drv_data->state =
188 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
189 break;
190 }
191 /* FALLTHRU */
192 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
193 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
e91c021c
MG		 194 if ((drv_data->bytes_left == 0)
195 || (drv_data->aborting
196 && (drv_data->byte_posn != 0))) {
eda6bee6
RG		 197 if (drv_data->send_stop) {
198 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
199 drv_data->state = MV64XXX_I2C_STATE_IDLE;
200 } else {
201 drv_data->action =
202 MV64XXX_I2C_ACTION_SEND_RESTART;
203 drv_data->state =
204 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
205 }
e91c021c 206 } else {
1da177e4
LT		 207 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
208 drv_data->state =
209 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
210 drv_data->bytes_left--;
1da177e4
LT		 211 }
212 break;
213
214 /* Performing a read */
215 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
216 if (drv_data->msg->flags & I2C_M_TEN) {
217 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
218 drv_data->state =
219 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
220 break;
221 }
222 /* FALLTHRU */
223 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
224 if (drv_data->bytes_left == 0) {
225 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
226 drv_data->state = MV64XXX_I2C_STATE_IDLE;
227 break;
228 }
229 /* FALLTHRU */
230 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
231 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
232 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
233 else {
234 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
235 drv_data->bytes_left--;
236 }
237 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
238
e91c021c 239 if ((drv_data->bytes_left == 1) || drv_data->aborting)
1da177e4
LT		 240 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
241 break;
242
243 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
244 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
245 drv_data->state = MV64XXX_I2C_STATE_IDLE;
246 break;
247
248 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
249 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
250 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
251 /* Doesn't seem to be a device at other end */
252 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
253 drv_data->state = MV64XXX_I2C_STATE_IDLE;
254 drv_data->rc = -ENODEV;
255 break;
256
257 default:
258 dev_err(&drv_data->adapter.dev,
259 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
260 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
261 drv_data->state, status, drv_data->msg->addr,
262 drv_data->msg->flags);
263 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
a07ad1cc 264 mv64xxx_i2c_hw_init(drv_data);
1da177e4
LT		 265 drv_data->rc = -EIO;
266 }
267}
268
269static void
270mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
271{
272 switch(drv_data->action) {
eda6bee6
RG		 273 case MV64XXX_I2C_ACTION_SEND_RESTART:
274 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
275 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
276 writel(drv_data->cntl_bits,
277 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
278 drv_data->block = 0;
d295a86e 279 wake_up(&drv_data->waitq);
eda6bee6
RG		 280 break;
281
1da177e4
LT		 282 case MV64XXX_I2C_ACTION_CONTINUE:
283 writel(drv_data->cntl_bits,
284 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
285 break;
286
287 case MV64XXX_I2C_ACTION_SEND_START:
288 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
289 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
290 break;
291
292 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
293 writel(drv_data->addr1,
294 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
295 writel(drv_data->cntl_bits,
296 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
297 break;
298
299 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
300 writel(drv_data->addr2,
301 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
302 writel(drv_data->cntl_bits,
303 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
304 break;
305
306 case MV64XXX_I2C_ACTION_SEND_DATA:
307 writel(drv_data->msg->buf[drv_data->byte_posn++],
308 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
309 writel(drv_data->cntl_bits,
310 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
311 break;
312
313 case MV64XXX_I2C_ACTION_RCV_DATA:
314 drv_data->msg->buf[drv_data->byte_posn++] =
315 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
316 writel(drv_data->cntl_bits,
317 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
318 break;
319
320 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
321 drv_data->msg->buf[drv_data->byte_posn++] =
322 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
323 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
324 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
325 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
326 drv_data->block = 0;
d295a86e 327 wake_up(&drv_data->waitq);
1da177e4
LT		 328 break;
329
330 case MV64XXX_I2C_ACTION_INVALID:
331 default:
332 dev_err(&drv_data->adapter.dev,
333 "mv64xxx_i2c_do_action: Invalid action: %d\n",
334 drv_data->action);
335 drv_data->rc = -EIO;
336 /* FALLTHRU */
337 case MV64XXX_I2C_ACTION_SEND_STOP:
338 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
339 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
340 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
341 drv_data->block = 0;
d295a86e 342 wake_up(&drv_data->waitq);
1da177e4
LT		 343 break;
344 }
345}
346
b0999cc5 347static irqreturn_t
7d12e780 348mv64xxx_i2c_intr(int irq, void *dev_id)
1da177e4
LT		 349{
350 struct mv64xxx_i2c_data *drv_data = dev_id;
351 unsigned long flags;
352 u32 status;
b0999cc5 353 irqreturn_t rc = IRQ_NONE;
1da177e4
LT		 354
355 spin_lock_irqsave(&drv_data->lock, flags);
356 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
357 MV64XXX_I2C_REG_CONTROL_IFLG) {
358 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
359 mv64xxx_i2c_fsm(drv_data, status);
360 mv64xxx_i2c_do_action(drv_data);
361 rc = IRQ_HANDLED;
362 }
363 spin_unlock_irqrestore(&drv_data->lock, flags);
364
365 return rc;
366}
367
368/*
369 *****************************************************************************
370 *
371 * I2C Msg Execution Routines
372 *
373 *****************************************************************************
374 */
1da177e4
LT		 375static void
376mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
377{
378 long time_left;
379 unsigned long flags;
380 char abort = 0;
381
d295a86e 382 time_left = wait_event_timeout(drv_data->waitq,
8a52c6b4 383 !drv_data->block, drv_data->adapter.timeout);
1da177e4
LT		 384
385 spin_lock_irqsave(&drv_data->lock, flags);
386 if (!time_left) { /* Timed out */
387 drv_data->rc = -ETIMEDOUT;
388 abort = 1;
389 } else if (time_left < 0) { /* Interrupted/Error */
390 drv_data->rc = time_left; /* errno value */
391 abort = 1;
392 }
393
394 if (abort && drv_data->block) {
e91c021c 395 drv_data->aborting = 1;
1da177e4
LT		 396 spin_unlock_irqrestore(&drv_data->lock, flags);
397
398 time_left = wait_event_timeout(drv_data->waitq,
8a52c6b4 399 !drv_data->block, drv_data->adapter.timeout);
1da177e4 400
e91c021c 401 if ((time_left <= 0) && drv_data->block) {
1da177e4
LT		 402 drv_data->state = MV64XXX_I2C_STATE_IDLE;
403 dev_err(&drv_data->adapter.dev,
e91c021c
MG		 404 "mv64xxx: I2C bus locked, block: %d, "
405 "time_left: %d\n", drv_data->block,
406 (int)time_left);
a07ad1cc 407 mv64xxx_i2c_hw_init(drv_data);
1da177e4
LT		 408 }
409 } else
410 spin_unlock_irqrestore(&drv_data->lock, flags);
411}
412
413static int
eda6bee6
RG		 414mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
415 int is_first, int is_last)
1da177e4
LT		 416{
417 unsigned long flags;
418
419 spin_lock_irqsave(&drv_data->lock, flags);
420 mv64xxx_i2c_prepare_for_io(drv_data, msg);
421
aa6bce53
RK		 422 if (is_first) {
423 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
424 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
1da177e4 425 } else {
aa6bce53
RK		 426 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
427 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
1da177e4
LT		 428 }
429
eda6bee6 430 drv_data->send_stop = is_last;
1da177e4
LT		 431 drv_data->block = 1;
432 mv64xxx_i2c_do_action(drv_data);
433 spin_unlock_irqrestore(&drv_data->lock, flags);
434
435 mv64xxx_i2c_wait_for_completion(drv_data);
436 return drv_data->rc;
437}
438
439/*
440 *****************************************************************************
441 *
442 * I2C Core Support Routines (Interface to higher level I2C code)
443 *
444 *****************************************************************************
445 */
446static u32
447mv64xxx_i2c_functionality(struct i2c_adapter *adap)
448{
449 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
450}
451
452static int
453mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
454{
455 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
d1b2f0a9 456 int i, rc;
1da177e4 457
eda6bee6
RG		 458 for (i = 0; i < num; i++) {
459 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
460 i == 0, i + 1 == num);
461 if (rc < 0)
d1b2f0a9 462 return rc;
eda6bee6 463 }
1da177e4 464
d1b2f0a9 465 return num;
1da177e4
LT		 466}
467
8f9082c5 468static const struct i2c_algorithm mv64xxx_i2c_algo = {
1da177e4
LT		 469 .master_xfer = mv64xxx_i2c_xfer,
470 .functionality = mv64xxx_i2c_functionality,
471};
472
473/*
474 *****************************************************************************
475 *
476 * Driver Interface & Early Init Routines
477 *
478 *****************************************************************************
479 */
b61d1575 480#ifdef CONFIG_OF
0b255e92 481static int
b61d1575
AL		 482mv64xxx_calc_freq(const int tclk, const int n, const int m)
483{
484 return tclk / (10 * (m + 1) * (2 << n));
485}
486
0b255e92 487static bool
b61d1575
AL		 488mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
489 u32 *best_m)
490{
491 int freq, delta, best_delta = INT_MAX;
492 int m, n;
493
494 for (n = 0; n <= 7; n++)
495 for (m = 0; m <= 15; m++) {
496 freq = mv64xxx_calc_freq(tclk, n, m);
497 delta = req_freq - freq;
498 if (delta >= 0 && delta < best_delta) {
499 *best_m = m;
500 *best_n = n;
501 best_delta = delta;
502 }
503 if (best_delta == 0)
504 return true;
505 }
506 if (best_delta == INT_MAX)
507 return false;
508 return true;
509}
510
0b255e92 511static int
b61d1575
AL		 512mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
513 struct device_node *np)
514{
515 u32 bus_freq, tclk;
516 int rc = 0;
517
518 /* CLK is mandatory when using DT to describe the i2c bus. We
519 * need to know tclk in order to calculate bus clock
520 * factors.
521 */
522#if !defined(CONFIG_HAVE_CLK)
523 /* Have OF but no CLK */
524 return -ENODEV;
525#else
526 if (IS_ERR(drv_data->clk)) {
527 rc = -ENODEV;
528 goto out;
529 }
530 tclk = clk_get_rate(drv_data->clk);
531 of_property_read_u32(np, "clock-frequency", &bus_freq);
532 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
533 &drv_data->freq_n, &drv_data->freq_m)) {
534 rc = -EINVAL;
535 goto out;
536 }
537 drv_data->irq = irq_of_parse_and_map(np, 0);
538
539 /* Its not yet defined how timeouts will be specified in device tree.
540 * So hard code the value to 1 second.
541 */
542 drv_data->adapter.timeout = HZ;
543out:
544 return rc;
545#endif
546}
547#else /* CONFIG_OF */
0b255e92 548static int
b61d1575
AL		 549mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
550 struct device_node *np)
551{
552 return -ENODEV;
553}
554#endif /* CONFIG_OF */
555
0b255e92 556static int
3ae5eaec 557mv64xxx_i2c_probe(struct platform_device *pd)
1da177e4 558{
1da177e4 559 struct mv64xxx_i2c_data *drv_data;
3ae5eaec 560 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
16874b07 561 struct resource *r;
1da177e4
LT		 562 int rc;
563
b61d1575 564 if ((!pdata && !pd->dev.of_node))
1da177e4
LT		 565 return -ENODEV;
566
2c911103
RK		 567 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
568 GFP_KERNEL);
1da177e4
LT		 569 if (!drv_data)
570 return -ENOMEM;
571
16874b07
RK		 572 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
573 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
2c911103
RK		 574 if (IS_ERR(drv_data->reg_base))
575 return PTR_ERR(drv_data->reg_base);
1da177e4 576
e91c021c 577 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
2096b956 578 sizeof(drv_data->adapter.name));
1da177e4
LT		 579
580 init_waitqueue_head(&drv_data->waitq);
581 spin_lock_init(&drv_data->lock);
582
b61d1575
AL		 583#if defined(CONFIG_HAVE_CLK)
584 /* Not all platforms have a clk */
4c5c95f5 585 drv_data->clk = devm_clk_get(&pd->dev, NULL);
b61d1575
AL		 586 if (!IS_ERR(drv_data->clk)) {
587 clk_prepare(drv_data->clk);
588 clk_enable(drv_data->clk);
589 }
590#endif
591 if (pdata) {
592 drv_data->freq_m = pdata->freq_m;
593 drv_data->freq_n = pdata->freq_n;
594 drv_data->irq = platform_get_irq(pd, 0);
595 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
596 } else if (pd->dev.of_node) {
597 rc = mv64xxx_of_config(drv_data, pd->dev.of_node);
598 if (rc)
2c911103 599 goto exit_clk;
b61d1575 600 }
48944738
DV		 601 if (drv_data->irq < 0) {
602 rc = -ENXIO;
2c911103 603 goto exit_clk;
48944738 604 }
b61d1575 605
12a917f6 606 drv_data->adapter.dev.parent = &pd->dev;
1da177e4
LT		 607 drv_data->adapter.algo = &mv64xxx_i2c_algo;
608 drv_data->adapter.owner = THIS_MODULE;
3401b2ff 609 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
65b22ad9 610 drv_data->adapter.nr = pd->id;
b61d1575 611 drv_data->adapter.dev.of_node = pd->dev.of_node;
3ae5eaec 612 platform_set_drvdata(pd, drv_data);
1da177e4
LT		 613 i2c_set_adapdata(&drv_data->adapter, drv_data);
614
3269bb63
MB		 615 mv64xxx_i2c_hw_init(drv_data);
616
0c195afb
RK		 617 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
618 MV64XXX_I2C_CTLR_NAME, drv_data);
619 if (rc) {
dfded4ae 620 dev_err(&drv_data->adapter.dev,
0c195afb
RK		 621 "mv64xxx: Can't register intr handler irq%d: %d\n",
622 drv_data->irq, rc);
2c911103 623 goto exit_clk;
65b22ad9 624 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
dfded4ae
MG		 625 dev_err(&drv_data->adapter.dev,
626 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1da177e4
LT		 627 goto exit_free_irq;
628 }
629
b61d1575
AL		 630 of_i2c_register_devices(&drv_data->adapter);
631
1da177e4
LT		 632 return 0;
633
2c911103
RK		 634exit_free_irq:
635 free_irq(drv_data->irq, drv_data);
636exit_clk:
b61d1575
AL		 637#if defined(CONFIG_HAVE_CLK)
638 /* Not all platforms have a clk */
639 if (!IS_ERR(drv_data->clk)) {
640 clk_disable(drv_data->clk);
641 clk_unprepare(drv_data->clk);
642 }
643#endif
1da177e4
LT		 644 return rc;
645}
646
0b255e92 647static int
3ae5eaec 648mv64xxx_i2c_remove(struct platform_device *dev)
1da177e4 649{
3ae5eaec 650 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
1da177e4 651
bf51a8c5 652 i2c_del_adapter(&drv_data->adapter);
1da177e4 653 free_irq(drv_data->irq, drv_data);
b61d1575
AL		 654#if defined(CONFIG_HAVE_CLK)
655 /* Not all platforms have a clk */
656 if (!IS_ERR(drv_data->clk)) {
657 clk_disable(drv_data->clk);
658 clk_unprepare(drv_data->clk);
659 }
660#endif
1da177e4 661
bf51a8c5 662 return 0;
1da177e4
LT		 663}
664
0b255e92 665static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
b61d1575
AL		 666 { .compatible = "marvell,mv64xxx-i2c", },
667 {}
668};
669MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
670
3ae5eaec 671static struct platform_driver mv64xxx_i2c_driver = {
1da177e4 672 .probe = mv64xxx_i2c_probe,
0b255e92 673 .remove = mv64xxx_i2c_remove,
3ae5eaec
RK		 674 .driver = {
675 .owner = THIS_MODULE,
676 .name = MV64XXX_I2C_CTLR_NAME,
b61d1575 677 .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table),
3ae5eaec 678 },
1da177e4
LT		 679};
680
a3664b51 681module_platform_driver(mv64xxx_i2c_driver);
1da177e4
LT		 682
683MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
684MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
685MODULE_LICENSE("GPL");
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