]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/i2c/busses/i2c-mv64xxx.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
I2C: mv64xxx: use devm_clk_get() to avoid missing clk_put()
[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-mv64xxx.c
CommitLineData
1da177e4 1/*
a0832798
TP		 2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
1da177e4
LT		 4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/kernel.h>
5a0e3ad6 13#include <linux/slab.h>
1da177e4
LT		 14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
a0832798 18#include <linux/mv643xx_i2c.h>
d052d1be 19#include <linux/platform_device.h>
21782180 20#include <linux/io.h>
b61d1575
AL		 21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_i2c.h>
24#include <linux/clk.h>
25#include <linux/err.h>
1da177e4
LT		 26
27/* Register defines */
28#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
29#define MV64XXX_I2C_REG_DATA 0x04
30#define MV64XXX_I2C_REG_CONTROL 0x08
31#define MV64XXX_I2C_REG_STATUS 0x0c
32#define MV64XXX_I2C_REG_BAUD 0x0c
33#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
34#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
35
36#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
37#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
38#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
39#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
40#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
41#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
42
43/* Ctlr status values */
44#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
45#define MV64XXX_I2C_STATUS_MAST_START 0x08
46#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
47#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
48#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
49#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
50#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
51#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
52#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
53#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
54#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
55#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
56#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
57#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
58#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
59#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
60#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
61
62/* Driver states */
63enum {
64 MV64XXX_I2C_STATE_INVALID,
65 MV64XXX_I2C_STATE_IDLE,
66 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
eda6bee6 67 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
1da177e4
LT		 68 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
69 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
70 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
71 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
1da177e4
LT		 72};
73
74/* Driver actions */
75enum {
76 MV64XXX_I2C_ACTION_INVALID,
77 MV64XXX_I2C_ACTION_CONTINUE,
78 MV64XXX_I2C_ACTION_SEND_START,
eda6bee6 79 MV64XXX_I2C_ACTION_SEND_RESTART,
1da177e4
LT		 80 MV64XXX_I2C_ACTION_SEND_ADDR_1,
81 MV64XXX_I2C_ACTION_SEND_ADDR_2,
82 MV64XXX_I2C_ACTION_SEND_DATA,
83 MV64XXX_I2C_ACTION_RCV_DATA,
84 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
85 MV64XXX_I2C_ACTION_SEND_STOP,
86};
87
88struct mv64xxx_i2c_data {
89 int irq;
90 u32 state;
91 u32 action;
e91c021c 92 u32 aborting;
1da177e4
LT		 93 u32 cntl_bits;
94 void __iomem *reg_base;
1da177e4
LT		 95 u32 addr1;
96 u32 addr2;
97 u32 bytes_left;
98 u32 byte_posn;
eda6bee6 99 u32 send_stop;
1da177e4
LT		 100 u32 block;
101 int rc;
102 u32 freq_m;
103 u32 freq_n;
b61d1575
AL		 104#if defined(CONFIG_HAVE_CLK)
105 struct clk *clk;
106#endif
1da177e4
LT		 107 wait_queue_head_t waitq;
108 spinlock_t lock;
109 struct i2c_msg *msg;
110 struct i2c_adapter adapter;
111};
112
113/*
114 *****************************************************************************
115 *
116 * Finite State Machine & Interrupt Routines
117 *
118 *****************************************************************************
119 */
a07ad1cc
DF		 120
121/* Reset hardware and initialize FSM */
122static void
123mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
124{
125 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
126 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
127 drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
128 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
129 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
130 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
131 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
132 drv_data->state = MV64XXX_I2C_STATE_IDLE;
133}
134
1da177e4
LT		 135static void
136mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
137{
138 /*
139 * If state is idle, then this is likely the remnants of an old
140 * operation that driver has given up on or the user has killed.
141 * If so, issue the stop condition and go to idle.
142 */
143 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
144 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
145 return;
146 }
147
1da177e4
LT		 148 /* The status from the ctlr [mostly] tells us what to do next */
149 switch (status) {
150 /* Start condition interrupt */
151 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
152 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
153 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
154 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
155 break;
156
157 /* Performing a write */
158 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
159 if (drv_data->msg->flags & I2C_M_TEN) {
160 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
161 drv_data->state =
162 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
163 break;
164 }
165 /* FALLTHRU */
166 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
167 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
e91c021c
MG		 168 if ((drv_data->bytes_left == 0)
169 || (drv_data->aborting
170 && (drv_data->byte_posn != 0))) {
eda6bee6
RG		 171 if (drv_data->send_stop) {
172 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
173 drv_data->state = MV64XXX_I2C_STATE_IDLE;
174 } else {
175 drv_data->action =
176 MV64XXX_I2C_ACTION_SEND_RESTART;
177 drv_data->state =
178 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
179 }
e91c021c 180 } else {
1da177e4
LT		 181 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
182 drv_data->state =
183 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
184 drv_data->bytes_left--;
1da177e4
LT		 185 }
186 break;
187
188 /* Performing a read */
189 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
190 if (drv_data->msg->flags & I2C_M_TEN) {
191 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
192 drv_data->state =
193 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
194 break;
195 }
196 /* FALLTHRU */
197 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
198 if (drv_data->bytes_left == 0) {
199 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
200 drv_data->state = MV64XXX_I2C_STATE_IDLE;
201 break;
202 }
203 /* FALLTHRU */
204 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
205 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
206 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
207 else {
208 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
209 drv_data->bytes_left--;
210 }
211 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
212
e91c021c 213 if ((drv_data->bytes_left == 1) || drv_data->aborting)
1da177e4
LT		 214 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
215 break;
216
217 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
218 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
219 drv_data->state = MV64XXX_I2C_STATE_IDLE;
220 break;
221
222 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
223 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
224 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
225 /* Doesn't seem to be a device at other end */
226 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
227 drv_data->state = MV64XXX_I2C_STATE_IDLE;
228 drv_data->rc = -ENODEV;
229 break;
230
231 default:
232 dev_err(&drv_data->adapter.dev,
233 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
234 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
235 drv_data->state, status, drv_data->msg->addr,
236 drv_data->msg->flags);
237 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
a07ad1cc 238 mv64xxx_i2c_hw_init(drv_data);
1da177e4
LT		 239 drv_data->rc = -EIO;
240 }
241}
242
243static void
244mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
245{
246 switch(drv_data->action) {
eda6bee6
RG		 247 case MV64XXX_I2C_ACTION_SEND_RESTART:
248 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
249 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
250 writel(drv_data->cntl_bits,
251 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
252 drv_data->block = 0;
d295a86e 253 wake_up(&drv_data->waitq);
eda6bee6
RG		 254 break;
255
1da177e4
LT		 256 case MV64XXX_I2C_ACTION_CONTINUE:
257 writel(drv_data->cntl_bits,
258 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
259 break;
260
261 case MV64XXX_I2C_ACTION_SEND_START:
262 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
263 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
264 break;
265
266 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
267 writel(drv_data->addr1,
268 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
269 writel(drv_data->cntl_bits,
270 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
271 break;
272
273 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
274 writel(drv_data->addr2,
275 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
276 writel(drv_data->cntl_bits,
277 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
278 break;
279
280 case MV64XXX_I2C_ACTION_SEND_DATA:
281 writel(drv_data->msg->buf[drv_data->byte_posn++],
282 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
283 writel(drv_data->cntl_bits,
284 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
285 break;
286
287 case MV64XXX_I2C_ACTION_RCV_DATA:
288 drv_data->msg->buf[drv_data->byte_posn++] =
289 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
290 writel(drv_data->cntl_bits,
291 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
292 break;
293
294 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
295 drv_data->msg->buf[drv_data->byte_posn++] =
296 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
297 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
298 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
299 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
300 drv_data->block = 0;
d295a86e 301 wake_up(&drv_data->waitq);
1da177e4
LT		 302 break;
303
304 case MV64XXX_I2C_ACTION_INVALID:
305 default:
306 dev_err(&drv_data->adapter.dev,
307 "mv64xxx_i2c_do_action: Invalid action: %d\n",
308 drv_data->action);
309 drv_data->rc = -EIO;
310 /* FALLTHRU */
311 case MV64XXX_I2C_ACTION_SEND_STOP:
312 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
313 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
314 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
315 drv_data->block = 0;
d295a86e 316 wake_up(&drv_data->waitq);
1da177e4
LT		 317 break;
318 }
319}
320
b0999cc5 321static irqreturn_t
7d12e780 322mv64xxx_i2c_intr(int irq, void *dev_id)
1da177e4
LT		 323{
324 struct mv64xxx_i2c_data *drv_data = dev_id;
325 unsigned long flags;
326 u32 status;
b0999cc5 327 irqreturn_t rc = IRQ_NONE;
1da177e4
LT		 328
329 spin_lock_irqsave(&drv_data->lock, flags);
330 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
331 MV64XXX_I2C_REG_CONTROL_IFLG) {
332 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
333 mv64xxx_i2c_fsm(drv_data, status);
334 mv64xxx_i2c_do_action(drv_data);
335 rc = IRQ_HANDLED;
336 }
337 spin_unlock_irqrestore(&drv_data->lock, flags);
338
339 return rc;
340}
341
342/*
343 *****************************************************************************
344 *
345 * I2C Msg Execution Routines
346 *
347 *****************************************************************************
348 */
349static void
350mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
351 struct i2c_msg *msg)
352{
353 u32 dir = 0;
354
355 drv_data->msg = msg;
356 drv_data->byte_posn = 0;
357 drv_data->bytes_left = msg->len;
e91c021c 358 drv_data->aborting = 0;
1da177e4
LT		 359 drv_data->rc = 0;
360 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
361 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
362
363 if (msg->flags & I2C_M_RD)
364 dir = 1;
365
1da177e4
LT		 366 if (msg->flags & I2C_M_TEN) {
367 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
368 drv_data->addr2 = (u32)msg->addr & 0xff;
369 } else {
370 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
371 drv_data->addr2 = 0;
372 }
373}
374
375static void
376mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
377{
378 long time_left;
379 unsigned long flags;
380 char abort = 0;
381
d295a86e 382 time_left = wait_event_timeout(drv_data->waitq,
8a52c6b4 383 !drv_data->block, drv_data->adapter.timeout);
1da177e4
LT		 384
385 spin_lock_irqsave(&drv_data->lock, flags);
386 if (!time_left) { /* Timed out */
387 drv_data->rc = -ETIMEDOUT;
388 abort = 1;
389 } else if (time_left < 0) { /* Interrupted/Error */
390 drv_data->rc = time_left; /* errno value */
391 abort = 1;
392 }
393
394 if (abort && drv_data->block) {
e91c021c 395 drv_data->aborting = 1;
1da177e4
LT		 396 spin_unlock_irqrestore(&drv_data->lock, flags);
397
398 time_left = wait_event_timeout(drv_data->waitq,
8a52c6b4 399 !drv_data->block, drv_data->adapter.timeout);
1da177e4 400
e91c021c 401 if ((time_left <= 0) && drv_data->block) {
1da177e4
LT		 402 drv_data->state = MV64XXX_I2C_STATE_IDLE;
403 dev_err(&drv_data->adapter.dev,
e91c021c
MG		 404 "mv64xxx: I2C bus locked, block: %d, "
405 "time_left: %d\n", drv_data->block,
406 (int)time_left);
a07ad1cc 407 mv64xxx_i2c_hw_init(drv_data);
1da177e4
LT		 408 }
409 } else
410 spin_unlock_irqrestore(&drv_data->lock, flags);
411}
412
413static int
eda6bee6
RG		 414mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
415 int is_first, int is_last)
1da177e4
LT		 416{
417 unsigned long flags;
418
419 spin_lock_irqsave(&drv_data->lock, flags);
420 mv64xxx_i2c_prepare_for_io(drv_data, msg);
421
422 if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
423 if (drv_data->msg->flags & I2C_M_RD) {
424 /* No action to do, wait for slave to send a byte */
425 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
426 drv_data->state =
427 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
428 } else {
429 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
430 drv_data->state =
431 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
432 drv_data->bytes_left--;
433 }
434 } else {
eda6bee6
RG		 435 if (is_first) {
436 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
437 drv_data->state =
438 MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
439 } else {
440 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
441 drv_data->state =
442 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
443 }
1da177e4
LT		 444 }
445
eda6bee6 446 drv_data->send_stop = is_last;
1da177e4
LT		 447 drv_data->block = 1;
448 mv64xxx_i2c_do_action(drv_data);
449 spin_unlock_irqrestore(&drv_data->lock, flags);
450
451 mv64xxx_i2c_wait_for_completion(drv_data);
452 return drv_data->rc;
453}
454
455/*
456 *****************************************************************************
457 *
458 * I2C Core Support Routines (Interface to higher level I2C code)
459 *
460 *****************************************************************************
461 */
462static u32
463mv64xxx_i2c_functionality(struct i2c_adapter *adap)
464{
465 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
466}
467
468static int
469mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
470{
471 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
d1b2f0a9 472 int i, rc;
1da177e4 473
eda6bee6
RG		 474 for (i = 0; i < num; i++) {
475 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i],
476 i == 0, i + 1 == num);
477 if (rc < 0)
d1b2f0a9 478 return rc;
eda6bee6 479 }
1da177e4 480
d1b2f0a9 481 return num;
1da177e4
LT		 482}
483
8f9082c5 484static const struct i2c_algorithm mv64xxx_i2c_algo = {
1da177e4
LT		 485 .master_xfer = mv64xxx_i2c_xfer,
486 .functionality = mv64xxx_i2c_functionality,
487};
488
489/*
490 *****************************************************************************
491 *
492 * Driver Interface & Early Init Routines
493 *
494 *****************************************************************************
495 */
b61d1575 496#ifdef CONFIG_OF
0b255e92 497static int
b61d1575
AL		 498mv64xxx_calc_freq(const int tclk, const int n, const int m)
499{
500 return tclk / (10 * (m + 1) * (2 << n));
501}
502
0b255e92 503static bool
b61d1575
AL		 504mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
505 u32 *best_m)
506{
507 int freq, delta, best_delta = INT_MAX;
508 int m, n;
509
510 for (n = 0; n <= 7; n++)
511 for (m = 0; m <= 15; m++) {
512 freq = mv64xxx_calc_freq(tclk, n, m);
513 delta = req_freq - freq;
514 if (delta >= 0 && delta < best_delta) {
515 *best_m = m;
516 *best_n = n;
517 best_delta = delta;
518 }
519 if (best_delta == 0)
520 return true;
521 }
522 if (best_delta == INT_MAX)
523 return false;
524 return true;
525}
526
0b255e92 527static int
b61d1575
AL		 528mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
529 struct device_node *np)
530{
531 u32 bus_freq, tclk;
532 int rc = 0;
533
534 /* CLK is mandatory when using DT to describe the i2c bus. We
535 * need to know tclk in order to calculate bus clock
536 * factors.
537 */
538#if !defined(CONFIG_HAVE_CLK)
539 /* Have OF but no CLK */
540 return -ENODEV;
541#else
542 if (IS_ERR(drv_data->clk)) {
543 rc = -ENODEV;
544 goto out;
545 }
546 tclk = clk_get_rate(drv_data->clk);
547 of_property_read_u32(np, "clock-frequency", &bus_freq);
548 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
549 &drv_data->freq_n, &drv_data->freq_m)) {
550 rc = -EINVAL;
551 goto out;
552 }
553 drv_data->irq = irq_of_parse_and_map(np, 0);
554
555 /* Its not yet defined how timeouts will be specified in device tree.
556 * So hard code the value to 1 second.
557 */
558 drv_data->adapter.timeout = HZ;
559out:
560 return rc;
561#endif
562}
563#else /* CONFIG_OF */
0b255e92 564static int
b61d1575
AL		 565mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
566 struct device_node *np)
567{
568 return -ENODEV;
569}
570#endif /* CONFIG_OF */
571
0b255e92 572static int
3ae5eaec 573mv64xxx_i2c_probe(struct platform_device *pd)
1da177e4 574{
1da177e4 575 struct mv64xxx_i2c_data *drv_data;
3ae5eaec 576 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
16874b07 577 struct resource *r;
1da177e4
LT		 578 int rc;
579
b61d1575 580 if ((!pdata && !pd->dev.of_node))
1da177e4
LT		 581 return -ENODEV;
582
5263ebb5 583 drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
1da177e4
LT		 584 if (!drv_data)
585 return -ENOMEM;
586
16874b07
RK		 587 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
588 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
589 if (IS_ERR(drv_data->reg_base)) {
590 rc = PTR_ERR(drv_data->reg_base);
1da177e4 591 goto exit_kfree;
16874b07 592 }
1da177e4 593
e91c021c 594 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
2096b956 595 sizeof(drv_data->adapter.name));
1da177e4
LT		 596
597 init_waitqueue_head(&drv_data->waitq);
598 spin_lock_init(&drv_data->lock);
599
b61d1575
AL		 600#if defined(CONFIG_HAVE_CLK)
601 /* Not all platforms have a clk */
4c5c95f5 602 drv_data->clk = devm_clk_get(&pd->dev, NULL);
b61d1575
AL		 603 if (!IS_ERR(drv_data->clk)) {
604 clk_prepare(drv_data->clk);
605 clk_enable(drv_data->clk);
606 }
607#endif
608 if (pdata) {
609 drv_data->freq_m = pdata->freq_m;
610 drv_data->freq_n = pdata->freq_n;
611 drv_data->irq = platform_get_irq(pd, 0);
612 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
613 } else if (pd->dev.of_node) {
614 rc = mv64xxx_of_config(drv_data, pd->dev.of_node);
615 if (rc)
616 goto exit_unmap_regs;
617 }
48944738
DV		 618 if (drv_data->irq < 0) {
619 rc = -ENXIO;
620 goto exit_unmap_regs;
621 }
b61d1575 622
12a917f6 623 drv_data->adapter.dev.parent = &pd->dev;
1da177e4
LT		 624 drv_data->adapter.algo = &mv64xxx_i2c_algo;
625 drv_data->adapter.owner = THIS_MODULE;
3401b2ff 626 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
65b22ad9 627 drv_data->adapter.nr = pd->id;
b61d1575 628 drv_data->adapter.dev.of_node = pd->dev.of_node;
3ae5eaec 629 platform_set_drvdata(pd, drv_data);
1da177e4
LT		 630 i2c_set_adapdata(&drv_data->adapter, drv_data);
631
3269bb63
MB		 632 mv64xxx_i2c_hw_init(drv_data);
633
1da177e4 634 if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
dfded4ae
MG		 635 MV64XXX_I2C_CTLR_NAME, drv_data)) {
636 dev_err(&drv_data->adapter.dev,
637 "mv64xxx: Can't register intr handler irq: %d\n",
638 drv_data->irq);
1da177e4
LT		 639 rc = -EINVAL;
640 goto exit_unmap_regs;
65b22ad9 641 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
dfded4ae
MG		 642 dev_err(&drv_data->adapter.dev,
643 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1da177e4
LT		 644 goto exit_free_irq;
645 }
646
b61d1575
AL		 647 of_i2c_register_devices(&drv_data->adapter);
648
1da177e4
LT		 649 return 0;
650
651 exit_free_irq:
652 free_irq(drv_data->irq, drv_data);
653 exit_unmap_regs:
b61d1575
AL		 654#if defined(CONFIG_HAVE_CLK)
655 /* Not all platforms have a clk */
656 if (!IS_ERR(drv_data->clk)) {
657 clk_disable(drv_data->clk);
658 clk_unprepare(drv_data->clk);
659 }
660#endif
1da177e4
LT		 661 exit_kfree:
662 kfree(drv_data);
663 return rc;
664}
665
0b255e92 666static int
3ae5eaec 667mv64xxx_i2c_remove(struct platform_device *dev)
1da177e4 668{
3ae5eaec 669 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
1da177e4 670
bf51a8c5 671 i2c_del_adapter(&drv_data->adapter);
1da177e4 672 free_irq(drv_data->irq, drv_data);
b61d1575
AL		 673#if defined(CONFIG_HAVE_CLK)
674 /* Not all platforms have a clk */
675 if (!IS_ERR(drv_data->clk)) {
676 clk_disable(drv_data->clk);
677 clk_unprepare(drv_data->clk);
678 }
679#endif
1da177e4
LT		 680 kfree(drv_data);
681
bf51a8c5 682 return 0;
1da177e4
LT		 683}
684
0b255e92 685static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
b61d1575
AL		 686 { .compatible = "marvell,mv64xxx-i2c", },
687 {}
688};
689MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
690
3ae5eaec 691static struct platform_driver mv64xxx_i2c_driver = {
1da177e4 692 .probe = mv64xxx_i2c_probe,
0b255e92 693 .remove = mv64xxx_i2c_remove,
3ae5eaec
RK		 694 .driver = {
695 .owner = THIS_MODULE,
696 .name = MV64XXX_I2C_CTLR_NAME,
b61d1575 697 .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table),
3ae5eaec 698 },
1da177e4
LT		 699};
700
a3664b51 701module_platform_driver(mv64xxx_i2c_driver);
1da177e4
LT		 702
703MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
704MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
705MODULE_LICENSE("GPL");
ubuntu-zesty-kernel mirror