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1da177e4 LT |
1 | /* |
2 | * drivers/i2c/busses/i2c-mv64xxx.c | |
3 | * | |
4 | * Driver for the i2c controller on the Marvell line of host bridges for MIPS | |
5 | * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0). | |
6 | * | |
7 | * Author: Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * 2005 (c) MontaVista, Software, Inc. This file is licensed under | |
10 | * the terms of the GNU General Public License version 2. This program | |
11 | * is licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | */ | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/mv643xx.h> | |
d052d1be RK |
20 | #include <linux/platform_device.h> |
21 | ||
1da177e4 LT |
22 | #include <asm/io.h> |
23 | ||
24 | /* Register defines */ | |
25 | #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 | |
26 | #define MV64XXX_I2C_REG_DATA 0x04 | |
27 | #define MV64XXX_I2C_REG_CONTROL 0x08 | |
28 | #define MV64XXX_I2C_REG_STATUS 0x0c | |
29 | #define MV64XXX_I2C_REG_BAUD 0x0c | |
30 | #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 | |
31 | #define MV64XXX_I2C_REG_SOFT_RESET 0x1c | |
32 | ||
33 | #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 | |
34 | #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 | |
35 | #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 | |
36 | #define MV64XXX_I2C_REG_CONTROL_START 0x00000020 | |
37 | #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 | |
38 | #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 | |
39 | ||
40 | /* Ctlr status values */ | |
41 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 | |
42 | #define MV64XXX_I2C_STATUS_MAST_START 0x08 | |
43 | #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 | |
44 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 | |
45 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 | |
46 | #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 | |
47 | #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 | |
48 | #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 | |
49 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 | |
50 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 | |
51 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 | |
52 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 | |
53 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 | |
54 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 | |
55 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 | |
56 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 | |
57 | #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 | |
58 | ||
59 | /* Driver states */ | |
60 | enum { | |
61 | MV64XXX_I2C_STATE_INVALID, | |
62 | MV64XXX_I2C_STATE_IDLE, | |
63 | MV64XXX_I2C_STATE_WAITING_FOR_START_COND, | |
64 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, | |
65 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, | |
66 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, | |
67 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, | |
68 | MV64XXX_I2C_STATE_ABORTING, | |
69 | }; | |
70 | ||
71 | /* Driver actions */ | |
72 | enum { | |
73 | MV64XXX_I2C_ACTION_INVALID, | |
74 | MV64XXX_I2C_ACTION_CONTINUE, | |
75 | MV64XXX_I2C_ACTION_SEND_START, | |
76 | MV64XXX_I2C_ACTION_SEND_ADDR_1, | |
77 | MV64XXX_I2C_ACTION_SEND_ADDR_2, | |
78 | MV64XXX_I2C_ACTION_SEND_DATA, | |
79 | MV64XXX_I2C_ACTION_RCV_DATA, | |
80 | MV64XXX_I2C_ACTION_RCV_DATA_STOP, | |
81 | MV64XXX_I2C_ACTION_SEND_STOP, | |
82 | }; | |
83 | ||
84 | struct mv64xxx_i2c_data { | |
85 | int irq; | |
86 | u32 state; | |
87 | u32 action; | |
88 | u32 cntl_bits; | |
89 | void __iomem *reg_base; | |
90 | u32 reg_base_p; | |
91 | u32 addr1; | |
92 | u32 addr2; | |
93 | u32 bytes_left; | |
94 | u32 byte_posn; | |
95 | u32 block; | |
96 | int rc; | |
97 | u32 freq_m; | |
98 | u32 freq_n; | |
99 | wait_queue_head_t waitq; | |
100 | spinlock_t lock; | |
101 | struct i2c_msg *msg; | |
102 | struct i2c_adapter adapter; | |
103 | }; | |
104 | ||
105 | /* | |
106 | ***************************************************************************** | |
107 | * | |
108 | * Finite State Machine & Interrupt Routines | |
109 | * | |
110 | ***************************************************************************** | |
111 | */ | |
112 | static void | |
113 | mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) | |
114 | { | |
115 | /* | |
116 | * If state is idle, then this is likely the remnants of an old | |
117 | * operation that driver has given up on or the user has killed. | |
118 | * If so, issue the stop condition and go to idle. | |
119 | */ | |
120 | if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { | |
121 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
122 | return; | |
123 | } | |
124 | ||
125 | if (drv_data->state == MV64XXX_I2C_STATE_ABORTING) { | |
126 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
127 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
128 | return; | |
129 | } | |
130 | ||
131 | /* The status from the ctlr [mostly] tells us what to do next */ | |
132 | switch (status) { | |
133 | /* Start condition interrupt */ | |
134 | case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ | |
135 | case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ | |
136 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; | |
137 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; | |
138 | break; | |
139 | ||
140 | /* Performing a write */ | |
141 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ | |
142 | if (drv_data->msg->flags & I2C_M_TEN) { | |
143 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
144 | drv_data->state = | |
145 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
146 | break; | |
147 | } | |
148 | /* FALLTHRU */ | |
149 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ | |
150 | case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ | |
151 | if (drv_data->bytes_left > 0) { | |
152 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; | |
153 | drv_data->state = | |
154 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
155 | drv_data->bytes_left--; | |
156 | } else { | |
157 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
158 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
159 | } | |
160 | break; | |
161 | ||
162 | /* Performing a read */ | |
163 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ | |
164 | if (drv_data->msg->flags & I2C_M_TEN) { | |
165 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
166 | drv_data->state = | |
167 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
168 | break; | |
169 | } | |
170 | /* FALLTHRU */ | |
171 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ | |
172 | if (drv_data->bytes_left == 0) { | |
173 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
174 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
175 | break; | |
176 | } | |
177 | /* FALLTHRU */ | |
178 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ | |
179 | if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) | |
180 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
181 | else { | |
182 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; | |
183 | drv_data->bytes_left--; | |
184 | } | |
185 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
186 | ||
187 | if (drv_data->bytes_left == 1) | |
188 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; | |
189 | break; | |
190 | ||
191 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ | |
192 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; | |
193 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
194 | break; | |
195 | ||
196 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ | |
197 | case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ | |
198 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ | |
199 | /* Doesn't seem to be a device at other end */ | |
200 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
201 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
202 | drv_data->rc = -ENODEV; | |
203 | break; | |
204 | ||
205 | default: | |
206 | dev_err(&drv_data->adapter.dev, | |
207 | "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " | |
208 | "status: 0x%x, addr: 0x%x, flags: 0x%x\n", | |
209 | drv_data->state, status, drv_data->msg->addr, | |
210 | drv_data->msg->flags); | |
211 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
212 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
213 | drv_data->rc = -EIO; | |
214 | } | |
215 | } | |
216 | ||
217 | static void | |
218 | mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) | |
219 | { | |
220 | switch(drv_data->action) { | |
221 | case MV64XXX_I2C_ACTION_CONTINUE: | |
222 | writel(drv_data->cntl_bits, | |
223 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
224 | break; | |
225 | ||
226 | case MV64XXX_I2C_ACTION_SEND_START: | |
227 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, | |
228 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
229 | break; | |
230 | ||
231 | case MV64XXX_I2C_ACTION_SEND_ADDR_1: | |
232 | writel(drv_data->addr1, | |
233 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
234 | writel(drv_data->cntl_bits, | |
235 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
236 | break; | |
237 | ||
238 | case MV64XXX_I2C_ACTION_SEND_ADDR_2: | |
239 | writel(drv_data->addr2, | |
240 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
241 | writel(drv_data->cntl_bits, | |
242 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
243 | break; | |
244 | ||
245 | case MV64XXX_I2C_ACTION_SEND_DATA: | |
246 | writel(drv_data->msg->buf[drv_data->byte_posn++], | |
247 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
248 | writel(drv_data->cntl_bits, | |
249 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
250 | break; | |
251 | ||
252 | case MV64XXX_I2C_ACTION_RCV_DATA: | |
253 | drv_data->msg->buf[drv_data->byte_posn++] = | |
254 | readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
255 | writel(drv_data->cntl_bits, | |
256 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
257 | break; | |
258 | ||
259 | case MV64XXX_I2C_ACTION_RCV_DATA_STOP: | |
260 | drv_data->msg->buf[drv_data->byte_posn++] = | |
261 | readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
262 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
263 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
264 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
265 | drv_data->block = 0; | |
266 | wake_up_interruptible(&drv_data->waitq); | |
267 | break; | |
268 | ||
269 | case MV64XXX_I2C_ACTION_INVALID: | |
270 | default: | |
271 | dev_err(&drv_data->adapter.dev, | |
272 | "mv64xxx_i2c_do_action: Invalid action: %d\n", | |
273 | drv_data->action); | |
274 | drv_data->rc = -EIO; | |
275 | /* FALLTHRU */ | |
276 | case MV64XXX_I2C_ACTION_SEND_STOP: | |
277 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
278 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
279 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
280 | drv_data->block = 0; | |
281 | wake_up_interruptible(&drv_data->waitq); | |
282 | break; | |
283 | } | |
284 | } | |
285 | ||
286 | static int | |
287 | mv64xxx_i2c_intr(int irq, void *dev_id, struct pt_regs *regs) | |
288 | { | |
289 | struct mv64xxx_i2c_data *drv_data = dev_id; | |
290 | unsigned long flags; | |
291 | u32 status; | |
292 | int rc = IRQ_NONE; | |
293 | ||
294 | spin_lock_irqsave(&drv_data->lock, flags); | |
295 | while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & | |
296 | MV64XXX_I2C_REG_CONTROL_IFLG) { | |
297 | status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); | |
298 | mv64xxx_i2c_fsm(drv_data, status); | |
299 | mv64xxx_i2c_do_action(drv_data); | |
300 | rc = IRQ_HANDLED; | |
301 | } | |
302 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
303 | ||
304 | return rc; | |
305 | } | |
306 | ||
307 | /* | |
308 | ***************************************************************************** | |
309 | * | |
310 | * I2C Msg Execution Routines | |
311 | * | |
312 | ***************************************************************************** | |
313 | */ | |
314 | static void | |
315 | mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, | |
316 | struct i2c_msg *msg) | |
317 | { | |
318 | u32 dir = 0; | |
319 | ||
320 | drv_data->msg = msg; | |
321 | drv_data->byte_posn = 0; | |
322 | drv_data->bytes_left = msg->len; | |
323 | drv_data->rc = 0; | |
324 | drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | | |
325 | MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; | |
326 | ||
327 | if (msg->flags & I2C_M_RD) | |
328 | dir = 1; | |
329 | ||
330 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
331 | dir ^= 1; | |
332 | ||
333 | if (msg->flags & I2C_M_TEN) { | |
334 | drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; | |
335 | drv_data->addr2 = (u32)msg->addr & 0xff; | |
336 | } else { | |
337 | drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; | |
338 | drv_data->addr2 = 0; | |
339 | } | |
340 | } | |
341 | ||
342 | static void | |
343 | mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) | |
344 | { | |
345 | long time_left; | |
346 | unsigned long flags; | |
347 | char abort = 0; | |
348 | ||
349 | time_left = wait_event_interruptible_timeout(drv_data->waitq, | |
350 | !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout)); | |
351 | ||
352 | spin_lock_irqsave(&drv_data->lock, flags); | |
353 | if (!time_left) { /* Timed out */ | |
354 | drv_data->rc = -ETIMEDOUT; | |
355 | abort = 1; | |
356 | } else if (time_left < 0) { /* Interrupted/Error */ | |
357 | drv_data->rc = time_left; /* errno value */ | |
358 | abort = 1; | |
359 | } | |
360 | ||
361 | if (abort && drv_data->block) { | |
362 | drv_data->state = MV64XXX_I2C_STATE_ABORTING; | |
363 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
364 | ||
365 | time_left = wait_event_timeout(drv_data->waitq, | |
366 | !drv_data->block, | |
367 | msecs_to_jiffies(drv_data->adapter.timeout)); | |
368 | ||
369 | if (time_left <= 0) { | |
370 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
371 | dev_err(&drv_data->adapter.dev, | |
372 | "mv64xxx: I2C bus locked\n"); | |
373 | } | |
374 | } else | |
375 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
376 | } | |
377 | ||
378 | static int | |
379 | mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg) | |
380 | { | |
381 | unsigned long flags; | |
382 | ||
383 | spin_lock_irqsave(&drv_data->lock, flags); | |
384 | mv64xxx_i2c_prepare_for_io(drv_data, msg); | |
385 | ||
386 | if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ | |
387 | if (drv_data->msg->flags & I2C_M_RD) { | |
388 | /* No action to do, wait for slave to send a byte */ | |
389 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
390 | drv_data->state = | |
391 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
392 | } else { | |
393 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; | |
394 | drv_data->state = | |
395 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
396 | drv_data->bytes_left--; | |
397 | } | |
398 | } else { | |
399 | drv_data->action = MV64XXX_I2C_ACTION_SEND_START; | |
400 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; | |
401 | } | |
402 | ||
403 | drv_data->block = 1; | |
404 | mv64xxx_i2c_do_action(drv_data); | |
405 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
406 | ||
407 | mv64xxx_i2c_wait_for_completion(drv_data); | |
408 | return drv_data->rc; | |
409 | } | |
410 | ||
411 | /* | |
412 | ***************************************************************************** | |
413 | * | |
414 | * I2C Core Support Routines (Interface to higher level I2C code) | |
415 | * | |
416 | ***************************************************************************** | |
417 | */ | |
418 | static u32 | |
419 | mv64xxx_i2c_functionality(struct i2c_adapter *adap) | |
420 | { | |
421 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; | |
422 | } | |
423 | ||
424 | static int | |
425 | mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
426 | { | |
427 | struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); | |
d1b2f0a9 | 428 | int i, rc; |
1da177e4 LT |
429 | |
430 | for (i=0; i<num; i++) | |
d1b2f0a9 JD |
431 | if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0) |
432 | return rc; | |
1da177e4 | 433 | |
d1b2f0a9 | 434 | return num; |
1da177e4 LT |
435 | } |
436 | ||
437 | static struct i2c_algorithm mv64xxx_i2c_algo = { | |
1da177e4 LT |
438 | .master_xfer = mv64xxx_i2c_xfer, |
439 | .functionality = mv64xxx_i2c_functionality, | |
440 | }; | |
441 | ||
442 | /* | |
443 | ***************************************************************************** | |
444 | * | |
445 | * Driver Interface & Early Init Routines | |
446 | * | |
447 | ***************************************************************************** | |
448 | */ | |
449 | static void __devinit | |
450 | mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) | |
451 | { | |
452 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); | |
453 | writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), | |
454 | drv_data->reg_base + MV64XXX_I2C_REG_BAUD); | |
455 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); | |
456 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); | |
457 | writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, | |
458 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
459 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
460 | } | |
461 | ||
462 | static int __devinit | |
463 | mv64xxx_i2c_map_regs(struct platform_device *pd, | |
464 | struct mv64xxx_i2c_data *drv_data) | |
465 | { | |
466 | struct resource *r; | |
467 | ||
468 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) && | |
469 | request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE, | |
470 | drv_data->adapter.name)) { | |
471 | ||
472 | drv_data->reg_base = ioremap(r->start, | |
473 | MV64XXX_I2C_REG_BLOCK_SIZE); | |
474 | drv_data->reg_base_p = r->start; | |
475 | } else | |
476 | return -ENOMEM; | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | static void __devexit | |
482 | mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) | |
483 | { | |
484 | if (drv_data->reg_base) { | |
485 | iounmap(drv_data->reg_base); | |
486 | release_mem_region(drv_data->reg_base_p, | |
487 | MV64XXX_I2C_REG_BLOCK_SIZE); | |
488 | } | |
489 | ||
490 | drv_data->reg_base = NULL; | |
491 | drv_data->reg_base_p = 0; | |
492 | } | |
493 | ||
494 | static int __devinit | |
3ae5eaec | 495 | mv64xxx_i2c_probe(struct platform_device *pd) |
1da177e4 | 496 | { |
1da177e4 | 497 | struct mv64xxx_i2c_data *drv_data; |
3ae5eaec | 498 | struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; |
1da177e4 LT |
499 | int rc; |
500 | ||
501 | if ((pd->id != 0) || !pdata) | |
502 | return -ENODEV; | |
503 | ||
5263ebb5 | 504 | drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); |
1da177e4 LT |
505 | if (!drv_data) |
506 | return -ENOMEM; | |
507 | ||
1da177e4 LT |
508 | if (mv64xxx_i2c_map_regs(pd, drv_data)) { |
509 | rc = -ENODEV; | |
510 | goto exit_kfree; | |
511 | } | |
512 | ||
513 | strncpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", | |
514 | I2C_NAME_SIZE); | |
515 | ||
516 | init_waitqueue_head(&drv_data->waitq); | |
517 | spin_lock_init(&drv_data->lock); | |
518 | ||
519 | drv_data->freq_m = pdata->freq_m; | |
520 | drv_data->freq_n = pdata->freq_n; | |
521 | drv_data->irq = platform_get_irq(pd, 0); | |
c7a46533 | 522 | drv_data->adapter.id = I2C_HW_MV64XXX; |
1da177e4 LT |
523 | drv_data->adapter.algo = &mv64xxx_i2c_algo; |
524 | drv_data->adapter.owner = THIS_MODULE; | |
525 | drv_data->adapter.class = I2C_CLASS_HWMON; | |
526 | drv_data->adapter.timeout = pdata->timeout; | |
527 | drv_data->adapter.retries = pdata->retries; | |
3ae5eaec | 528 | platform_set_drvdata(pd, drv_data); |
1da177e4 LT |
529 | i2c_set_adapdata(&drv_data->adapter, drv_data); |
530 | ||
531 | if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, | |
dfded4ae MG |
532 | MV64XXX_I2C_CTLR_NAME, drv_data)) { |
533 | dev_err(&drv_data->adapter.dev, | |
534 | "mv64xxx: Can't register intr handler irq: %d\n", | |
535 | drv_data->irq); | |
1da177e4 LT |
536 | rc = -EINVAL; |
537 | goto exit_unmap_regs; | |
538 | } else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) { | |
dfded4ae MG |
539 | dev_err(&drv_data->adapter.dev, |
540 | "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); | |
1da177e4 LT |
541 | goto exit_free_irq; |
542 | } | |
543 | ||
544 | mv64xxx_i2c_hw_init(drv_data); | |
545 | ||
546 | return 0; | |
547 | ||
548 | exit_free_irq: | |
549 | free_irq(drv_data->irq, drv_data); | |
550 | exit_unmap_regs: | |
551 | mv64xxx_i2c_unmap_regs(drv_data); | |
552 | exit_kfree: | |
553 | kfree(drv_data); | |
554 | return rc; | |
555 | } | |
556 | ||
557 | static int __devexit | |
3ae5eaec | 558 | mv64xxx_i2c_remove(struct platform_device *dev) |
1da177e4 | 559 | { |
3ae5eaec | 560 | struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); |
1da177e4 LT |
561 | int rc; |
562 | ||
563 | rc = i2c_del_adapter(&drv_data->adapter); | |
564 | free_irq(drv_data->irq, drv_data); | |
565 | mv64xxx_i2c_unmap_regs(drv_data); | |
566 | kfree(drv_data); | |
567 | ||
568 | return rc; | |
569 | } | |
570 | ||
3ae5eaec | 571 | static struct platform_driver mv64xxx_i2c_driver = { |
1da177e4 LT |
572 | .probe = mv64xxx_i2c_probe, |
573 | .remove = mv64xxx_i2c_remove, | |
3ae5eaec RK |
574 | .driver = { |
575 | .owner = THIS_MODULE, | |
576 | .name = MV64XXX_I2C_CTLR_NAME, | |
577 | }, | |
1da177e4 LT |
578 | }; |
579 | ||
580 | static int __init | |
581 | mv64xxx_i2c_init(void) | |
582 | { | |
3ae5eaec | 583 | return platform_driver_register(&mv64xxx_i2c_driver); |
1da177e4 LT |
584 | } |
585 | ||
586 | static void __exit | |
587 | mv64xxx_i2c_exit(void) | |
588 | { | |
3ae5eaec | 589 | platform_driver_unregister(&mv64xxx_i2c_driver); |
1da177e4 LT |
590 | } |
591 | ||
592 | module_init(mv64xxx_i2c_init); | |
593 | module_exit(mv64xxx_i2c_exit); | |
594 | ||
595 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); | |
596 | MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); | |
597 | MODULE_LICENSE("GPL"); |